KR100199189B1 - Digital receiving device of dss - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

It is a technology that demodulates original data through digital signal processing, synchronization tracking, and initial synchronization by adaptively changing threshold values according to spread signals.

2. Technical problem to be solved by the invention

When the initial synchronization is detected, the threshold is not adaptively assigned according to the environment in which the system is applied. Instead, it is fixed to the average value of the situation and compared with the envelope signal. Therefore, the probability of initial synchronization failure is high. It is to.

3. Summary of Solution to Invention

Early, functual, and latent signals are generated according to the spread signals and adaptively vary thresholds to achieve digital signal processing, synchronization tracking, and initial synchronization.

4. Important uses of the invention

It is applied to modem for mobile communication using direct spread spectrum communication method.

Description

Direct spread spectrum communication digital receiver

1 is a block diagram of a conventional analog receiving system.

2 is a block diagram of an asynchronous digital receiving system according to the present invention.

The present invention relates to a receiver of a direct spread spectrum communication method. In particular, a threshold value is adaptively changed according to a spread spectrum signal, thereby demodulating original data through digital signal processing, synchronization tracking, and initial synchronization. It is about a system.

In general, a spread spectrum communication system has a strong advantage against noise by spreading and processing data by spreading dozens or hundreds of times.

As shown in FIG. 1, digital signal processing is performed on the spread spectrum signal to demodulate original data. The operation of demodulating the data will be described with reference to FIG. 1.

The received digital signal is multiplied by the reference signal generated from the PN code generator 108 in the multiplier 101 and output to the band pass filter 102. The band pass filter 102 removes the high frequency component of the multiplied signal and outputs the high frequency component to the multiplier 103. The multiplier 103 squares the signal from which the high frequency component is removed and outputs the squared signal to the envelope detector 104 so as to ignore the influence of the modulated data. The envelope detector 104 detects the envelope from the squared signal and outputs it to one terminal of the comparator 105. The comparator 105 compares the detected envelope signal with a fixed threshold value V _r and determines that initial synchronization fails or a synchronization loss occurs when the value is smaller than the threshold value V _r . The above-described operation is repeated by shifting the signal by one chip. However, if the detected envelope signal is larger than the threshold value, it is determined that the time difference between the transmission signal and the reception signal is within 1 chip and enters the synchronization tracking process.

The receiver of the conventional digital spread spectrum communication system as described above is not adaptively given a threshold value according to the environment in which the system is applied, but the initial synchronization fails because the situation is fixed as an average value and compared with the envelope signal. There is a high probability of, and also difficult to track accurately during synchronization tracking.

Accordingly, an object of the present invention is to provide a receiver of a direct spread spectrum communication method which can be miniaturized and prevents malfunction due to noise.

Another object of the present invention is to provide a receiver of a direct spread spectrum communication method capable of preventing the occurrence of a synchronous tracking fail.

Another object of the present invention is to provide a receiver of a direct spread spectrum communication method that can shorten the initial synchronization time.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a direct spread spectrum receiver according to an embodiment of the present invention, and includes an amplifier 202, a BPF 203, a carrier generator 205, a mixer 204, and a BPF 206 in a received signal. Receiving unit 302 for removing a carrier wave and converting it into an intermediate frequency, an intermediate frequency oscillator 209 for generating an intermediate frequency signal, a mixer 210, and a low pass filter (hereinafter referred to as LPF) 213 And an I-channel converter 304 for removing an intermediate frequency component and extracting an I-channel component by mixing the intermediate-frequency converted signal with the generated intermediate frequency signal. A first A / D converter 215 for outputting the I-channel component signal extracted from 304 to the I-channel plate signal L digitally changed by the system clock SCLK signal, and the first A / D converter 215 Digital-converted I-channel late signal L by half-shifted by the system clock to output a punctual signal P A second delay for outputting an early (E) signal by half-shifting the first delay unit 217 to be output and the I-channel functional signal P output from the first delay unit 217 by the system clock. Group 218, a π / 2 phase shifter 211, a mixer 212, and an LPF 214 to mix the intermediate frequency converted signal with an intermediate frequency signal equal to or more than π / 2 to obtain an intermediate frequency component. A Q-channel converter 306 for removing the Q-channel component and extracting the Q-channel component, and outputting a digital signal of the Q-channel component signal extracted from the Q-channel converter 306. The Q-channel funnel signal P is shifted by half-chip shifting the Q-channel gate signal L output from the second A / D converter 216 and the second A / D converter 216 by the system clock signal. The third delay unit 219 and the Q channel punctual signal P output from the third delay unit 219 are shifted by half the chip by the system clock signal, and the Q channel early. A PN code generator 246 for generating a reference PN code by a predetermined control of the fourth delay unit 210 for outputting the call E, a reference PN code generated from the PN code generator 246, and the first PN code generator 246; The sixth multiplier 216 outputs the third Q channel despread signal by multiplying the Q channel early signal E output from the four delay unit 210, and the Q channel output from the third delay unit 219. A fifth multiplier 215 for multiplying the punctual signal P by the third Q channel despread signal output from the sixth multiplier 216 and outputting a second Q channel despread signal, and the second A / A fourth multiplier outputting the first Q channel despread signal by multiplying the Q channel late signal L output from the D converter 216 and the second Q channel despread signal output from the fifth multiplier 215. 214 and the first I channel despread signal output from the second multiplier 219 and the first Q channel despread signal output from the fourth multiplier 214 to multiply the third I channel despread. A third multiplier 213 for outputting a call, an I-channel punctual signal P output from the first delayer 219, and a third Q channel despread signal output from the third multiplier 213; A second multiplier 212 for multiplying and outputting a second I-channel despread signal, and an I-channel plate L output from the first A / D converter 215 and an output from the second multiplier 212 A first multiplier 211 outputting a first I channel despread signal by multiplying the second I channel despread signal, and a first to third I output from the first to third multipliers 211 to 213. A first-third accumulator (217-219) for inputting channel despread signals, cumulatively adding the respective input signals during one symbol duration, and dumping the addition result; 214-216), respectively, input the first-third Q channel despread signals, cumulatively add the respective input signals during one symbol duration, and dump the addition result. First-third multiplier 223 outputting the fourth-sixth accumulator replicator 220-222 and the tump output signal from the first-third accumulator replicator 217-219, respectively. -225), a fourth-fourth squarer 226-228 which square-operates the signals output from the fourth-th sixth accumulated replica unit 220-222, respectively, and outputs the first ruler. A gate adder 229 that adds and outputs the I-channel gate signal squared output from the multiplier 223 and the Q-channel gate signal squared output from the fourth power stage 226, and the second multiplier 224. A square adder 230 that adds and outputs an I-channel punctual signal output from a squared power and a Q-channel punctual signal output from a fifth squared power generator 227 and a third squared power from the third squarer 225. An early adder 231 for adding and outputting the output I channel late signal and the Q channel early signal squared output from the sixth power generator 228, and from the early adder 231; A subtractor 232 for subtracting and outputting a latent signal added from the late adder 229 from an acid output early signal, and the output added from the latet, functual and early adder 229-231; First to third square roots 233 to 235 for square-root-conducting the T-signal, punctual-signal, and early-signal, and outputting the I-channel and Q-channel converters. An adaptive threshold generator 242 for inputting a Q-channel signal output from 306 and adaptively generating a variable threshold by the func- tion code generated from the PN code generator 246, and first to third; A comparator 236-238, an oar gate 239, a synchronous detector 240, and an initial synchronous control unit 241 configured to output a square root operation output from the first-third root root 233-235; A variable outputted from the adaptive threshold generator 242 by inputting a functual signal and an early signal, respectively Initial sync controller 320, a subtractor 232, a fourth comparator 243, and a code track controller 244 which detects whether there is an initial sync and outputs a code search control signal for establishing the initial sync. Comparing the variable signal output from the adaptive threshold control unit 242 and the late signal and the early signal output from the first and third square roots (236,238) by comparing the difference between the signal and the early signal A synchronization search control unit 322 for generating a synchronization tracking control signal, a code search control signal for initial synchronization establishment output from the initial synchronization detection unit 320, and a synchronization tracking control signal output from the synchronization tracking control unit 322; It consists of a PN clock controller 245 that receives the input and generates a PN clock.

A preferred embodiment of the present invention will be described in detail with reference to FIG. 2 above.

The signal received at the antenna 201 is amplified by the amplifier 202 and passed through the BPF 203 and mixed with the carrier signal generated at the carrier generator 205 by the mixer 204 to remove the carrier wave, thereby intermediate frequency. After conversion, it passes through the BPF 206. At this time, the intermediate frequency generator 209 generates and outputs an intermediate frequency signal in order to make the high frequency signal into an intermediate frequency. The output signal of the BPF 206 is separated into an I-channel loop and a Q-channel loop so as to perform asynchronous detection, and the intermediate frequency components are removed from the mixers 210 and 212, respectively.

The I-channel spreading signal from which the carrier and the intermediate frequency components are removed from the mixer 210 is passed through the LPF 213, and the high frequency component is removed and applied to the first A / D converter 215.

The first A / D converter 215 converts the I-channel signal from which the high frequency component has been removed into a digital signal by the system clock, and outputs a rate signal L. The first delay unit 217 outputs a punctual signal P by half-chip shifting the I-channel gate signal L digitally converted from the first A / D converter 215 by the system clock. The second delay unit 218 outputs an early signal by shifting the I-channel punctual signal P output from the first delay unit 217 by the system clock.

The intermediate frequency signal multiplied by the Q channel loop is multiplied by π / 2 or more by the π / 2 phase shifter 211. The Q-channel spread signal from which the carrier and the intermediate frequency components are removed from the mixer 212 passes through the LPF 214, and then the high frequency component is removed and applied to the second A / D converter 216. The second A / D converter 216 converts the Q channel signal from which the high frequency component has been removed into a digital signal by the system clock, and outputs a Q channel rate signal L. The third delay unit 219 outputs a punctual signal P by half-chip shifting the Q-channel gate signal L digitally converted from the second A / D converter 216 by the system clock. The fourth delay unit 218 outputs the Q channel early signal E by half-shifting the Q channel functional signal P output from the third delay unit 219 by the system clock. At this time, the PN code generator 246 receives a predetermined PN clock to generate a reference PN code. The sixth multiplier 216 multiplies the reference PN code generated from the PN code generator 246 by the Q channel early signal E output from the fourth delay unit 210 to generate a third Q channel despread signal. Outputs The fifth multiplier 215 multiplies the Q channel functional signal output from the third delay unit 219 and the third Q channel despread signal output from the sixth multiplier 216 to despread the second Q channel. Output the signal. The fourth multiplier 214 multiplies the Q channel gate signal L output from the second A / D converter 216 and the second Q channel despread signal output from the fifth multiplier 215 to generate a first multiplier. 1 Outputs Q channel despread signal. The third multiplier 213 multiplies the I channel early signal E output from the second delayer 219 and the first Q channel despread signal output from the fourth multiplier 214 to form a third I channel. Output the despread signal. The second multiplier 212 multiplies the I channel functional signal P output from the first delay unit 219 and the third Q channel despread signal output from the third multiplier 213 to obtain a second I. Outputs the channel despread signal. The first multiplier 211 multiplies the I-channel plate L output from the first A / D converter 215 and the second I-channel despread signal output from the second multiplier 212 to obtain a first multiplier. Outputs the I channel despread signal. The first-third accumulator replicator 217-219 inputs the first-third I-channel despread signal output from the first-third multiplier 211-213, respectively, and outputs one symbol duration. Cumulatively add each and dump the output result. Fourth to Sixth Accumulator Replicators 220-222 Input first through third Q-channel despread signals output from the fourth and sixth multipliers 214 to 216, respectively, and output the respective input signals during one symbol duration. Cumulatively add each one and dump the result of the addition. The first-third multiplier 223-225 squares the signals output from the first-third accumulator replicator 217-219 and outputs the result. The fourth to sixth squarers 226 to 228 are squared on the signals output from the fourth to sixth accumulator replicators 220 to 222, respectively, and output. The gate adder 229 adds and outputs the I-channel gate signal squared output from the first square 223 and the Q-channel gate signal squared output from the fourth square 226. The functor adder 230 adds and outputs the I-channel func- tion signal squared output from the second square 224 and the Q-channel funnel signal output from the fifth square 227. The early adder 231 adds and outputs the I-channel rate signal squared output from the third square 225 and the Q-channel early signal squared output from the sixth square 228. The subtractor 232 subtracts and outputs the late signal added and output from the late adder 229 from the early signal added and output from the early adder 231. The first to third square roots 233 to 235 calculate square roots of the latet, punctual, and early signals that are added and output from the ratite, punctual, and early adders 229-231. The adaptive threshold generator 242 inputs the I-channel signal output from the LPF 213 and the Q-channel signal output from the LPF 214 and inputs the punctual code generated from the PN code generator 246. Thereby adaptively generating a variable threshold. The first-third comparator 236-238 outputs the latent signal, punctual signal, and early signal output from the first-third square root 233-235 by the square root from the adaptive threshold generator 242. The output is output to the oragate 239 in comparison with the generated variable threshold. At this time, if any one of the earliest, functual, and latent signals is larger than the variable threshold, the oragate 239 outputs an H IT signal. That is, the H IT signal means that one or more of the early, functual, and latent signals is larger than the threshold generated from the adaptive threshold controller 249, which means that the received partial PN code and reference partial PN code sequence are within 1 chip. Means match. When initial synchronization is performed using the early, functual, and latent signals described above, even if the PN code search is one chip, PN code search by chip can be achieved.

Also, in this case, PN code search is performed by one chip, so that initial synchronization time can be achieved relatively fast, and when the PN synchronization is done within one chip, the early, func- tional, and late signal changes compared to the threshold are relatively small. Make it relatively easy to implement.

On the other hand, in the present invention, when the synchronization is within 1 chip, the HIT signal is not immediately determined as the initial synchronization, but the false alarm (false alarm) or false tracking failure (false tracking) by the first synchronization detector 240 having a separate hysteresis. fail) D was prevented. That is, in the initial synchronization detector 240, even though the actual PN synchronization is not within 1 chip due to the influence of noise, when the H IT signal is output from the oragate 239, it is prevented or determined that the initial synchronization has been made. Even though the actual PN code synchronization is within 1 chip, the HIT signal does not occur due to the influence of noise. As a result, the code synchronization control unit 240 receives the determination signal as described above and outputs a code search control signal.

Among the generated early signal, punctual signal, and late signal, a signal related to initial synchronization is a punctual signal, and a signal related to synchronization tracking is an early signal. And a late signal. In this case, the characteristics of the early signal are first correlated for one period of the PN code when one data symbol is spread in units of one period of the PN code, and the early signal corresponds to the PN code. Typical characteristics are shown. However, when one data symbol is spread over a portion of the PN code sequence, the correlation is taken for a portion of the PN code sequence corresponding to one data symbol, so the early signal exhibits typical partial characteristics. Make tracking difficult

The initial synchronization is a process of synchronizing the phase between the received PN code and the reference PN code within 1 chip. In the conventional method, when the punctual signal is smaller than the set threshold, the initial synchronization is not performed by comparing the punctual signal with the set threshold. Therefore, when only the punctual signal is used, when the PN code search is performed by one chip for initial synchronization, the punctuation of the punctual signal becomes very large, and thus it is very difficult to set an appropriate threshold value to be compared. Therefore, the synchronization tracking adjusts the phase of the reference PN code synchronized with the phase of the received spread signal exactly within one chip and continuously maintains the phase synchronization of the two signals. For synchronous tracking, the signal from the first square root 233 and the early signal output from the third square root 235 are used. The two signals are subtracted from the subtractor 232 to obtain a reference PN code. An error signal reflecting the phase difference with the received certainty is output. At this time, the error signal output from the subtractor 232 is applied to the fourth comparator 243 and compared with the threshold generated from the adaptive threshold controller 242 in the fourth comparator 243 to operate the code tracking controller 244. To control. The code tracking controller 244 receives the late signal output from the first square root 233 and the early signal output from the third square root 235 and outputs the output signal from the fourth comparator 243. A PN clock control signal for maintaining the initial synchronization of the reference PN code within one chip period is generated and output to the PN clock control unit 245. The PN clock control unit 245 receives a code search control signal from the code synchronization control unit 241 and a PN clock control signal output from the code tracking control unit 244 and adjusts the speed according to the input of the two signals. Generate and output the clock.

As described above, the present invention enables miniaturization of the system by processing all signals after the carrier and intermediate frequencies are removed digitally, and improves reliability by preventing malfunction due to noise. There is an advantage that the initial synchronization time can be shortened by setting an initial synchronization by comparing the early, functual, and late signal with each other.

Claims (7)

A receiver of a direct spread spectrum communication system having a receiving means for removing intermediate carriers from a received signal and performing intermediate frequency conversion, comprising: PN code generating means for receiving a predetermined PN clock and generating and outputting a reference PN code; The digital I channel reception signal and the Q channel reception signal are received through a predetermined transmission path to generate a late signal, a functual signal, an early signal of the I channel, and a late signal, a punctual signal, and an early signal of the Q channel. Despreading means for despreading and outputting the generated I-channel rate signals, punctual signals, early signals, and Q-channel rate signals, punctual signals, and early signals according to the reference PN code; Receives the input signals of the I and Q channels despread from the means, funnel signals, and early signals, and accumulates and adds each of the inputs during one symbol duration, respectively. Accumulated replication means for outputting each of the 3 Q channel dump signals, and the first to third I channel dump signals and the first to third Q channel dump signals outputted from the accumulation replication means, respectively, to perform the first to third operations. Output as I-square square signal and first-third Q-channel square signal A squared operation means and a first I-channel squared signal output from the squared calculation means and a first Q-channel squared line are added to output a first addition signal, and the second I-channel squared signal and the second Q-channel squared signal are added. Adding means for adding and outputting as a second addition signal, and adding the third I-channel square signal and the third Q-channel square signal to output each as a third addition signal; A square root operation means for receiving the first to third addition signals and calculating square roots of the respective input signals and outputting the first to third operation signals; Adaptive threshold generation means for receiving the I-channel received signal and the Q-channel received signal and the reference PN code, obtaining a correlation between the received signals and the PN code, and generating and outputting an adaptive threshold corresponding thereto; Initial sync detection means for inputting the first-third operation signal calculated from the square root computing means and detecting the presence or absence of initial synchronization by comparing with the variable threshold output from the adaptive threshold control means, and the first calculated by the square root computing means. Comparing the difference value of the first and third operation signals with the variable threshold output from the adaptive threshold control means, respectively, to maintain the initial synchronization between the I and Q channel reception signals and the first to third PIN codes within one chip period. Code tracking control means for generating and outputting a PN clock control signal; And a PN clock control means for receiving the code search control signal and the PN clock control signal and generating and outputting a PN clock that is speed-controlled under the control of the two input signals. The apparatus of claim 1, wherein the despreading means comprises: a first A / D converter 215 for outputting the I channel component signal as an I channel plate signal L digitally changed by a system clock signal SCLK; A first delay unit 217 for outputting a punctual signal P by half-chip shifting the I-channel late signal L digitally converted from the first A / D converter 215 by the system clock; A second delay unit 218 for half-shifting the I-channel functional signal P output from the delay unit 217 by the system clock and outputting an early E signal, and digitally converting the Q-channel signal. The second A / D converter outputting as a gate (L) signal and the Q channel gate signal L output from the second A / D converter 216 are half-chip shifted by the system clock signal to perform a Q channel. The system clock includes a third delay unit 219 for outputting a punctual signal P, and a Q channel punctual signal P output from the third delay unit 219. The fourth delay unit 210 outputs the Q channel early signal E by half-chip shifting by the arc, and the Q channel early signal E output from the generated reference PN code and the fourth delay unit 210. The multiplier 216 outputs a third Q channel despread signal by multiplying and outputs the Q channel punctual signal P output from the third delay unit 219 and the sixth multiplier 216. A fifth multiplier 215 for multiplying the third Q channel despread signal and outputting a second Q channel despread signal, and a Q channel late signal L output from the second A / D converter 216. And a fourth multiplier 214 for outputting a first Q channel despread signal by multiplying the second Q channel despread signal output from the fifth multiplier 215, and outputted from the second delay unit 219. A third multiplier 213 for outputting a third I-channel despread signal by multiplying the I-channel early signal E by the first Q-channel despread signal output from the fourth multiplier 214, and the first multiplier 213 A second multiplier outputting a second I-channel despread signal by multiplying the I-channel punctual signal P output from the delay unit 219 and the third Q-channel despread signal output from the third multiplier 213. 212 and a first I-channel by multiplying an I-channel plate L output from the first A / D converter 215 and a second I-channel despread signal output from the second multiplier 212. And a first multiplier (211) for outputting a despread signal. 3. The apparatus of claim 2, wherein the initial synchronization detecting means comprises: a first signal for outputting a late signal, a funnel signal, and an early signal output from the square root calculation means by comparing with a variable threshold value generated from the adaptive threshold generating means; -An oragate that receives and compares a variable threshold value among early, punctual, and latet signals from the first and third comparators 126-238 and the first-third comparator 236-238, and logically combines and outputs an HIT signal. And an initial synchronous detection unit 240 for receiving a HIT signal from the ora gate 239 and outputting a determination signal for the fall alarm due to noise to prevent the false fail, and the initial synchronous detection unit 240. Direct spread spectrum communication receiver comprising a code synchronization control unit 240 for receiving a signal and outputting a code search control signal. The signal tracking control unit of claim 3, wherein the code tracking control unit receives the rate signal and the early signal output from the square root unit and subtracts the two signals to reflect an phase difference between the reference PN code and the received confidence code. A subtractor 232 for outputting an output signal, a fourth comparator 243 for comparing an error signal output from the subtractor 232 with a threshold value generated by the adaptive threshold controller 242, and an output from the square root operation means; A code tracking controller by generating a PN clock control signal for keeping the initial synchronization of the reference PN code within 1 chip period by inputting the received late signal and early signal, and outputting the signal output from the fourth comparator 243. 244) direct spread spectrum type receiver. A receiver of a direct spread spectrum communication system having a receiving means for removing intermediate carriers from a received signal and performing intermediate frequency conversion, comprising: PN code generating means for receiving a predetermined PN clock and generating and outputting a reference PN code; Receives a digital I-channel receiving signal through a predetermined transmission path to generate an I-channel rate signal, a funnel signal, and an early signal, and outputs the generated I-channel rate signal, punctual signal, and early signal to the reference PN. An I-channel despreading means for despreading and outputting each of the codes and a digital Q channel receiving signal through a predetermined transmission path to generate a late signal, a flat signal and an early signal of the Q channel, and generate the Q Q channel despreading means for despreading and outputting the latet signal, punctual signal, and early signal of the channel by the reference PN code, and the I channel despreading from the I channel despreading means and the Q channel despreading means. And receiving the late signal, the funnel signal, and the early signal of the Q channel, and cumulatively adding the respective input signals during one symbol duration to convert the first to third I channel dump signals and the first to third Q channel dump signals. Accumulated Replication Number Outputting Each However, the first-third I-channel dump signal and the first-third Q-channel dump signal output from the accumulating replication means are respectively squared to perform the first-third I-channel square signal and the first-third Q-channel Square calculation means for outputting a square signal, a first I-channel square signal and a first Q-channel square signal output from the square calculation means are added to output a first addition signal, and the second I-channel square signal and the first Addition means for adding 2 Q-channel squared signals and outputting them as a second addition signal, and adding the third I-channel squared signal and the 3rd Q-channel squared signal and outputting them as a third addition signal, respectively; A square root operation means for receiving an addition signal and outputting the respective input signals as square root operations and outputting the first to third calculated signals; Adaptive threshold generating means for receiving the I-channel received signal and the Q-channel received signal and the reference PN code, obtaining a correlation between the received signals and the PN code, and generating and outputting an adaptive threshold corresponding thereto; Initial sync detection means for inputting the first-third operation signal calculated from the square root computing means and detecting the presence or absence of initial synchronization by comparing with the variable threshold output from the adaptive threshold control means, and the first calculated by the square root computing means. 1, comparing the difference value of the third operation signal with the variable threshold output from the adaptive threshold control means, respectively, to maintain the initial synchronization between the I, Q channel reception signal and the first to 3PN codes within one chip period. Code tracking control means for generating and outputting a PN clock control signal; And a PN clock control means for receiving the code search control signal and the PN clock control signal, and generating and outputting a PN clock that is speed-controlled under the control of the two input signals. 6. The apparatus of claim 5, wherein the Q channel despreading means includes: a second A / D converter 216 for outputting the Q channel signal as a digitally converted plate (L) signal; A third delay unit 219 for outputting a Q channel punctual signal P by half-chip shifting the Q channel late signal L output from the second and second system clock signals, and the third delay unit 219. A fourth delay unit 210 for outputting the Q channel early signal E by half-chip shifting the Q channel punctual signal P outputted from the < RTI ID = 0.0 > system clock signal < / RTI > The sixth multiplier 216 outputs the third Q channel despread signal by multiplying the Q channel early signal E output from the four delay unit 210, and the Q channel output from the third delay unit 219. A fifth multiplier 215 for multiplying the punctual signal P by the third Q channel despread signal output from the sixth multiplier 216 and outputting a second Q channel despread signal; Outputs the first Q channel despread signal by multiplying the Q channel rate signal L output from the second A / D converter 216 and the second Q channel despread signal output from the fifth multiplier 215. Direct spread spectrum communication receiver, characterized in that consisting of a fourth multiplier (214). 6. The first A / D converter 215 according to claim 5, wherein the I-channel despreading means outputs the I-channel signal as an I-channel plate signal L digitally converted by a system clock signal SCLK. And a first delay unit 217 for outputting a punctual signal P by half-chip shifting the I-channel signal L digitally converted from the first A / D converter 215 by the system clock. And a second delay unit 218 for outputting an early E signal by half-shifting the I-channel functional signal P output from the first delay unit 217 by the system clock, and the second delay unit. A third multiplier 213 for outputting a third I-channel despread signal by multiplying the I-channel early signal E outputted from the device 219 and the first Q-channel despread signal output from the fourth multiplier 214. ) And a second Q channel despread signal output from the first delay unit 219 and a third Q channel despread signal output from the third multiplier 213 to obtain a second multiplier. A second multiplier 212 for outputting an I-channel despread signal, an I-channel latch L output from the first A / D converter 215, and a second I output from the second multiplier 212 And a first multiplier (211) for multiplying the channel despread signal and outputting the first I channel despread signal.