JPH075639Y2 - Junction isolation structure between semiconductor regions in an integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention provides a structure in which semiconductor regions in which integrated circuit devices are to be formed are bonded and separated from each other, that is, provided on one conductivity type semiconductor substrate. The present invention relates to a structure for dividing a semiconductor region or epitaxial layer having the other conductivity type into a plurality of semiconductor regions which are junction-separated from each other by a separation layer having one conductivity type.

[Conventional technology]

In an integrated circuit device, if all of the circuit elements that compose the integrated circuit device are formed in a common semiconductor region or an epitaxial layer, unnecessary interference occurs between the circuit elements and the circuit does not operate satisfactorily. It is often the case that, as is well known, the semiconductor region is divided into a plurality of regions to insulate or electrically isolate them from each other, and circuit elements are respectively formed in these semiconductor regions, and then a predetermined distance is provided between the circuit elements. It is common to make connections. There are roughly two types of means for separating into the multiple semiconductor regions, a dielectric separation method and a junction separation method. The former is superior in terms of separation performance, but the latter is more economical and is generally used. Has been done. The present invention relates to this joint separation structure, and as is well known, FIG. 3 shows an example of the basic structure.

In FIG. 3, reference numeral 1 denotes a semiconductor substrate, which is usually p-type. First, an n-type buried layer 4 is diffused in a predetermined range on its surface at a high impurity concentration, and then a semiconductor region is formed thereon. Then, the epitaxial layer 5 is grown over the entire surface as an n-type. Next, the separation layer 8 having a high p-type impurity concentration is deeply diffused from the surface of the epitaxial layer 5 in a frame-like or rope-like pattern until it reaches the semiconductor substrate 1 to form a plurality of epitaxial layers 5. Divide into semiconductor regions 10. A circuit element or a circuit element group forming an integrated circuit is built in each of the divided semiconductor regions 10.

A power supply voltage or a positive voltage close to the power supply voltage is applied to each semiconductor region 10 during operation of the integrated circuit, and the semiconductor substrate 1 is used in a grounded state. Therefore, the n-type semiconductor region 10 and the buried layer 4 and the p-type semiconductor region 10 are used. A voltage is applied to the pn junction between the semiconductor substrate 1 and the separation layer 8 in the reverse bias direction, whereby each semiconductor region 5 is separated from the semiconductor substrate 1 and the separation layer 8 in a so-called potential floating state. At the same time, the junctions of the semiconductor regions 10 are separated from each other.

The junction isolation structure of FIG. 4 is often used when the operating voltage of the integrated circuit is high and it is necessary to increase the thickness of the epitaxial layer 5 or the semiconductor region 10. The p-type embedded isolation layer 3 is embedded in the junction isolation structure. Similar to the layer 4, after being diffused and placed on the surface of the semiconductor substrate 1 in advance, the epitaxial layer 5 is grown to a desired thickness, and the p-type separation layer 8 is diffused from the surface and diffused upward from the lower side. It is connected to the buried separation layer 3 that comes. As a result, even when the thickness of the semiconductor region 5 is large, the width w of the separation layer 8 can be prevented from expanding as shown in FIG. By making it shallower, the time required for the thermal diffusion can be shortened.

[Problems to be solved by the device]

In the above-described junction isolation structure, since each semiconductor region 10 is electrically floating from the semiconductor substrate 1 and the isolation layer 8, there should be no interference between the circuit elements respectively built therein. However, in reality, the potential of each semiconductor region 10 can vary independently of each other with the operation of the integrated circuit.
There is a problem that some interference occurs through the junction capacitance of the pn junction. This will be described with reference to the equivalent circuit of FIG.

Transistors 20 and 21 shown on the left and right of FIG. 2 are field effect transistors as shown, for example, and are formed in the left and right semiconductor regions 10 of FIG. 3, respectively. The surface of the separation layer 8 at is the electrode film 14
It is assumed to be connected to the ground potential E via. Second
As shown in the equivalent circuit of the figure, both field effect transistors 20
Between each drain electrode D and the grounding point E of 21 and 21, for example, a kind of filter circuit composed of a pair of resistors R1 and R2, a pair of capacitors C and a resistor R3 is formed as shown. Has been done. As can be seen by comparing FIGS. 2 and 4, the resistor R1 is the internal resistance of the semiconductor region 10 and the capacitor C.
Between the buried isolation layer 3 and the isolation layer 8 and the semiconductor region 10.
A junction capacitance of the pn junction, a resistance R2 is an internal resistance of the buried separation layer 3 and the separation layer 8, and a resistance R3 is a connection resistance between the separation layer 8 and the ground electrode film 14.

As can be easily seen, looking at between the drain terminals D of both transistors 20 and 21, this filter circuit is a high-pass filter whose frequency characteristic is determined by the time constant of the product of the resistance value R1 + R2 and the capacitance value C. When the potential of the terminal D, that is, the potential of the semiconductor region 10 changes independently, mutual interference occurs between both transistors via this high-pass filter circuit, and the degree thereof increases as the operating frequency or operating speed of the transistor increases. . Even if the ground resistance R3 is reduced, mutual interference between the semiconductor regions cannot be avoided as long as there is a potential difference between the adjacent semiconductor regions 10 and the value fluctuates with time.

An object of the present invention is to obtain a junction isolation structure between semiconductor regions with good isolation performance capable of reducing mutual interference between such circuit elements in an integrated circuit device.

[Means for Solving the Problems]

According to the present invention, an object of the present invention is to form an integrated circuit in which a semiconductor region of the other conductivity type provided on a semiconductor substrate of one conductivity type is joined and separated from each other by a separation layer of the one conductivity type as described in the beginning. In order to divide the constituent circuit elements into a plurality of semiconductor regions to be respectively formed, the separation layer is formed of one conductivity type outer separation layer and one of the one having a high impurity concentration formed in the outer separation layer. An inner separation layer of a conductivity type, the impurity concentration of the outer separation layer is lower than the impurity concentration of the inner separation layer of the same conductivity type, and the depletion layer of the impurity concentration of the semiconductor regions of different conductivity types is spread. And a substantially equivalent impurity concentration value.

The outer separation layer and the inner separation layer constituting the separation layer according to the present invention have a two-step structure composed of a buried diffusion layer and a surface diffusion layer, respectively, which is separated especially when the thickness of the semiconductor region is large. This is desirable for narrowing the diffusion width of the layer to improve the utilization efficiency of the chip area and shortening the diffusion time.

[Action]

The present invention increases the effective impedance value in the operating frequency band of the integrated circuit of the high-pass filter circuit between adjacent semiconductor regions by reducing the aforementioned junction capacitance of the pn junction between the semiconductor region and the isolation layer. Focuses on that it is very effective in reducing interference. Therefore, in the present invention, as described above, the separation layer has a double structure composed of both inner and outer separation layers, and the inner separation layer is a high impurity concentration layer as in the conventional case, but the impurity concentration of the outer separation layer is the same. The impurity concentration value is lower than the impurity concentration of the conductivity type inner isolation layer and is substantially equivalent to the spread of the depletion layer of the impurity concentration of the semiconductor regions of different conductivity types.

As a result, the depletion layer, which has conventionally spread exclusively in the semiconductor region, also spreads to the outer isolation layer, so that the aforementioned junction capacitance C of the pn junction between the semiconductor region and the isolation layer is reduced to half. The capacitance component in the impedance of the above-mentioned high-pass filter circuit is doubled, which is reduced below. Further, since the impurity concentration of the outer separation layer is low, the above-mentioned resistance value R2, which is the internal resistance of the separation layer, becomes larger than in the conventional case, and the resistance component in the impedance also increases accordingly. Therefore, in the junction isolation structure according to the present invention, the effective impedance value in the frequency band in which the integrated circuit of the high-pass filter circuit between the semiconductor regions operates becomes larger than the conventional one,
Mutual interference between circuit elements formed in each semiconductor region can be effectively reduced.

Although the resistance value R1 increases as described above, the time constant, which is the product of the resistance value R1 + R2 and the capacitance value C, decreases, so the frequency characteristic of the effective impedance value of the high-pass filter circuit is Accordingly, the present invention can expand the frequency band in which the integrated circuit can safely operate without being affected by interference by the present invention.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. In this embodiment, the state at the time of completion of FIG.
In order to form the DMOS type or vertical type field effect transistors 20 and 21, the semiconductor region 10 is thicker than usual, for example, 20 μm.
That is all. Therefore, according to the present invention, the separation layer has a double structure including an inner separation layer and an outer separation layer, and the inner and outer separation layers further include a buried diffusion layer and a surface diffusion layer, respectively. It is said that Same figure (a) ~
Since the state up to the completed state is shown for each main step in (c), this order will be described below.

FIG. 1A shows the semiconductor substrate 1 alone. As shown in the figure, the substrate 1 is p-type as usual, and in this embodiment, the p-type outer buried isolation layer 2 and the high impurity concentration inner buried isolation layer 3 are both provided on the surface thereof. Then, the double layer structure is diffused in a usual manner in a rope-like pattern, and further, the buried layer 4 for the lower semiconductor region is diffused in an island shape with a high n-type impurity concentration in the mesh. FIG. 2B shows a state in which the n-type epitaxial layer 5 is grown on this. The epitaxial layer 5 has a thickness of 25 μm and an impurity concentration of about 10 ¹⁴ atoms / cm ³ . Due to the high temperature during the epitaxial growth, the outer buried isolation layer 2, the inner buried isolation layer 3 and the buried layer 4 below the semiconductor region are diffused upward in the epitaxial layer 5 by several μm as shown in the figure. This causes a so-called rise. In the present invention, it is advantageous to use boron having a large diffusion coefficient as the p-type impurity for the inner and outer buried separation layers 2 and 3.

FIG. 1 (c) shows a step of completing the separation layer. In this example, since a vertical field effect transistor is formed in each semiconductor region, for example, an n-type impurity is used for the drain contact layer 6 of this transistor before that. Is introduced or diffused at a high impurity concentration. For the separation layer, for example, boron is introduced as a p-type impurity into the double structure for the outer separation layer 7 and the inner separation layer 8 having a high impurity concentration, and the outer separation layer 7 is buried under high temperature as shown in the figure. 15 in this example so that the inner separation layer 8 is connected to the inner separation layer 2 respectively.
Heat is diffused to a depth of about μm. At the same time as this heat diffusion,
The drain contact layer 6 is also diffused so as to be connected to the buried layer 4.

By this step, the inner buried separation layer 3 and the inner separation layer 8 become the outer buried separation layer 2 and the outer separation layer 7 as shown in the figure.
A junction separation layer surrounded by is completed, and the epitaxial layer 5 is divided into a plurality of semiconductor regions 10 each having junction separation. The impurity concentration of the inner buried separation layer 3 and the inner separation layer 8 in the P-type separation layer having the inner-outer double structure is set to a high concentration of 10 ¹⁸ atoms / cm ³ or more as in the conventional case. The impurity concentration of the separation layer 2 and the outer separation layer 7 is the same as that of the n-type epitaxial layer 5 described above.
When it is about ¹⁴ atoms / cm ³ , it is appropriate to implement the present invention at 10 ¹⁶ atoms / cm ³ or slightly lower. When the impurity concentration of the n-type epitaxial layer 5 or the semiconductor region 10 and the impurity concentration of the p-type outer buried isolation layer 2 and the outer buried layer 7 are coordinated in this way, the
From the pn junction surface, the depletion layer can spread almost uniformly in the n-type region and the p-type region, and the junction capacitance can be effectively reduced.

To form the vertical field effect transistors 20 and 21 in the semiconductor region 10 as shown in FIG.
After the p-type channel forming layer 11 is diffused from the surface of, for example, in an annular pattern and the gate 12 of polycrystalline silicon or the like is provided thereon, the n-type source layer 13 is raised by using it as a mask as usual. The impurity concentration is also diffused in an annular pattern by the ion implantation method. As is well known, the surface of the p-type channel formation layer 11 sandwiched between the n-type source layer 13 and the semiconductor region 10 below the gate 12 serves as the n-type channel formation surface.

The surface of the source layer 13 and the surface of the channel forming layer 11 are short-circuited by the electrode film 14, and then the source terminal S is led out as shown in the figure. On the drain side, the drain terminal D is led out from the electrode film 14 thereon via the n-type semiconductor region 10, the buried layer 4 and the drain contact layer 6 as shown in the drawing, and can be controlled by the gate terminal G. Complete vertical n-channel field effect transistors 20 and 21 are completed. The ground terminal E is taken from the electrode film 14 which is in conductive contact with the surface of the inner buried separation layer 8 as shown in the figure.

As can be seen, the equivalent circuit of FIG. 1 (d) can be represented by the previously described FIG. As shown in FIG. 1 (d), the capacitor C in FIG. 2 is the junction capacitance of the pn junction between the junction separation layer having the double structure according to the present invention and the semiconductor substrate 1 and the semiconductor region 10. As described above, the capacitance value is smaller than in the case of the conventional structure, and the thickness of the outer buried separation layer 2 and the outer separation layer 7 is made slightly larger, so that it can be easily reduced to half or less of the conventional case. The resistor R1 in FIG. 2 is the same as the conventional one because it is the resistance of the semiconductor region 10 as described above, but the resistor R2 is the internal resistance of the separation layer, and in the case of the present invention, the outer buried separation layer 2 and the outer separation layer. Since the impurity concentration of No. 7 is low, it becomes considerably higher than the conventional one.

Therefore, as already mentioned in the section of action, the effective impedance value of the high-pass filter circuit between the semiconductor regions in the frequency band in which the integrated circuit operates becomes larger than the conventional one,
Mutual interference between circuit elements formed in each semiconductor region is reduced, and the time constant, which is the product of the resistance value R1 + R2 and the capacitance value C, usually decreases, so the frequency characteristic of the effective impedance value of the high-pass filter circuit is reduced. Is shifted toward higher frequencies, and the frequency band in which the integrated circuit can safely operate without being affected by interference is expanded as compared with the conventional case.

The present invention can be implemented in various modes, not limited to the above-described embodiments. For example, in the embodiment, the separation layer having a double structure according to the present invention is further made to have a two-step structure of a buried diffusion layer and a surface diffusion layer. However, when the epitaxial layer may be shallow, it is of course a one-step structure. Is enough. When the epitaxial layer needs to be thick as in the embodiment, if the two-step structure is used as in the embodiment, the width of the surface diffusion layer on the upper side is narrowed to improve the utilization efficiency of the chip area, and It is very effective in reducing the time required for diffusion.

Also in this two-stage structure, it is not always necessary that the embedded diffusion layer on the lower stage side has an internal / external double structure as in the embodiment.
It is also possible to simplify the process by forming a double structure only on the upper side.

[Effect of device]

As is clear from the above description, in the present invention, the semiconductor region of the other conductivity type provided on the semiconductor substrate of the one conductivity type is bonded and separated by the separation layer of the one conductivity type to form an integrated circuit. When dividing the circuit element to be formed into a plurality of semiconductor regions to be respectively formed, the separation layer is formed as an outer separation layer of one conductivity type and one conductivity type having a high impurity concentration formed in the outer separation layer. Of the inner separation layer, the impurity concentration of the outer separation layer is lower than the impurity concentration of the inner separation layer of the same conductivity type, and the impurity concentration of the semiconductor regions of different conductivity types is substantially equal to the spread of the depletion layer. Since the impurity concentration values are set to be equivalent to each other, the depletion layer spreads in both the semiconductor region and the outer isolation layer, the junction capacitance value of the pn junction between them decreases, and the internal resistance value in the isolation layer separates to the outer isolation layer. Low layer impurity concentration Minute only becomes higher than the conventional. Therefore, according to the present invention, the effective impedance value of the high-pass filter circuit between the adjacent semiconductor regions can be almost doubled as compared with the conventional one, and the mutual interference between the circuit elements formed in each semiconductor region can be effectively reduced. .

Furthermore, the time constant determined by the product of the junction capacitance value and the series resistance value in the high-pass filter circuit decreases, and the frequency characteristic of the effective impedance value shifts to the higher frequency side.
Due to the synergistic effect with this increase in effective impedance value,
The frequency band in which the integrated circuit operates safely without interference between its circuit elements can be expanded to about twice that of the conventional one.

Even if the present invention is carried out, the characteristics of the circuit elements respectively built in the respective semiconductor regions are of course no different from the conventional ones, and it is also necessary to increase the area of the integrated circuit device chip as seen from the examples. Therefore, by adopting the junction separation structure according to the present invention, it is possible to improve the operational reliability of the integrated circuit device and increase its operable frequency or operating speed at the same cost as the conventional one.

[Brief description of drawings]

1 and 2 relate to the present invention, and FIG. 1 is a partially enlarged cross-sectional view of an integrated circuit device showing an embodiment of a junction isolation structure between semiconductor regions according to the present invention in a state of each main process. Is an equivalent circuit diagram thereof. FIG. 3 and FIG. 4 are partially enlarged cross-sectional views of an integrated circuit device exemplifying different conventional junction separation structures. In the figure, 1: semiconductor substrate, 2: outer buried separation layer, 3: inner buried separation layer,
4: buried layer under semiconductor region, 5: epitaxial layer, 6: drain contact layer, 7: outer isolation layer, 8: inner isolation layer, 10:
Semiconductor region, 11: channel forming layer, 12: gate, 13: source layer, 14: electrode film, 20, 21: DMOS type or vertical field effect transistor, C: capacitor or junction capacitance, D: drain terminal, E: ground Terminal or ground potential, G: Gate terminal, R1
~ R3: resistance, S: source terminal, w: separation layer width.

Claims (1)

[Scope of utility model registration request] 1. A circuit element constituting an integrated circuit is formed by joining and separating a semiconductor region of another conductivity type provided on a semiconductor substrate of one conductivity type from each other by a separation layer of one conductivity type. A region which is divided into a plurality of semiconductor regions, the isolation layer being an outer isolation layer of one conductivity type and an inner isolation layer of one conductivity type having a high impurity concentration formed in the outer isolation layer. The impurity concentration of the outer isolation layer is lower than that of the inner isolation layer of the same conductivity type, and the impurity concentration of the semiconductor regions of different conductivity types is substantially equivalent to the expansion of the depletion layer. A junction isolation structure between semiconductor regions in an integrated circuit characterized by a concentration value.