JPH0754915B2 - Information compression / reproduction circuit and information compression / reproduction method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an information compression / reproduction circuit and an information compression / reproduction method for automatically detecting and compressing a repetitive pattern portion in a signal.

[Background of technology]

Conventionally, as one of the methods to trace a fault on a printed circuit board, the same test pattern signal as that of a good product is given to a defective product,
There is a method of comparing a node signal of a defective product with that of a non-defective product and making a determination based on whether the same operation as the non-defective product is performed. In this way, if there is a feedback loop in the printed circuit,
A method may be adopted in which the first place in the loop that operates differently from a non-defective product is determined as a defective place. In this case, it is necessary to constantly compare the signal movements of the non-defective product and the defective product. For this reason, a method of simultaneously comparing a good product and a defective product with a card tester is adopted, but there is a problem in that it is necessary to always secure a good product. In this case, it is possible to store the movement of a non-defective signal in a memory in advance and reproduce it for use, but there is a drawback that a memory with a large storage capacity is required.

[Object of the Invention]

The present invention, in order to solve the problems of the conventional method described above,
It is an object of the present invention to provide an effective means and method for compressing and storing information in a memory and reading it when necessary to reproduce and use original information.

[Structure of Invention]

The compression effect varies depending on the data string compression method and the data string. According to the present invention, a common data string which is a repeated data string can be efficiently compressed and reproduced by a simple circuit. As a method of extracting a common data string from a data string, the present invention focuses on the flow of data in the data string and focuses on the maximum value as the transition point and the change point of the data.
In other words, the maximum value of the data string is used as the delimiter for extracting the common data, and the data is compressed from the previously existing common data series.

The information compression / reproduction circuit of the present invention mainly compresses a data string composed of a plurality of data elements arranged in time series t ₀ , t ₁ , ... T _n-1 , t _n ,. An information compression / reproduction circuit for writing data in a memory or reading the written data from a main memory and reproducing the data sequence, wherein a first data selector and a first register for storing a data element from the first data selector A second register for sequentially storing the data elements transferred from the first register, a first comparator for comparing the output of the first register with the output of the second register, the time from the output of the first comparator A maximum value detection circuit that detects a maximum value between data elements of a series, a time series memory that uses the output of the second register as write data, and an address that specifies a write address and a read address of the time series memory. A circuit, a third register for storing the read data of the time series memory, a second comparator for comparing the output of the second register with the output of the third register, and the number of times that the second comparator produces a coincident output. A coincidence counter that counts the output of the second register when the second comparator produces a non-coincidence output, and when the non-coincidence output occurs after the coincidence output is produced, the coincidence counter output is selected as compressed data. A second data selector to
And a third comparator for comparing the output of the coincidence counter with the read compressed data of the main memory, and the first data selector selects the data string input at the time of compression and stores the data of the main memory at the time of reproduction. When the read data is compressed data, the output of the third register is selected, and when the read data is not compressed data, the read data is selected, and the address circuit detects the maximum value when the maximum value detection circuit detects the maximum value. Is configured to specify an address from the specified address at the time of writing when the maximum value of is detected, on condition that a coincident output is obtained by the second comparator, and at the time of compression, the output of the second data selector Is written in the main memory, and the output of the second register is transmitted as reproduction data during reproduction. It is.

Further, according to the information compression / reproduction method of the present invention, the input numerical data sequentially input are stored in the time series memory, and the input numerical data showing the maximum value and the numerical value showing the maximum value stored in the time series memory are stored. The i-th numerical value that follows the i-th input numerical data that follows the input numerical data that indicates the maximal value and that corresponds to the latest one excluding the input numerical data that indicates the maximal value in the data Compare the input numerical data with the numerical data stored in the time series memory so that the data correspond to each other, and if the comparison results show a match, write the input numerical data to the memory. No, the match counter is updated, and if the comparison result is a mismatch, the input numerical data when the mismatch is indicated is stored in the memory without updating the match counter. When the comparison result changes from coincidence to disagreement, the repeat count value including the count value of the coincidence counter and the compression flag is stored in the memory before storing the input numerical value data indicating the disagreement in the memory. In addition to clearing the coincidence counter, the numerical data string including the repeated count value read from the memory is reproduced and output as the numerical data string before compression.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of one embodiment when the present invention is applied to a card tester, FIG. 2 is a diagram showing a configuration of one embodiment of the information compression circuit shown in FIG. 1, and FIG. FIG. 4 is a diagram showing a detailed embodiment of the maximum value detection circuit shown in FIG. 2, and FIGS. 4 and 5 are diagrams for explaining the operation of the circuit shown in FIG. In the figure, 1 is a rise / fall detection circuit, 2 is a level reproduction circuit, 3 is a transition interval counter, 4 is a comparator, 5 is an information compression circuit, 6 is a main memory, 7 is a time series memory, and 8 is a maximum value address.・ Memory, 9 is a maximum value detection circuit, 10 is a time series memory address counter, 11 is a coincidence counter,
12 is a memory address counter, 91 is JK-FF, 92 is an AND gate, C1 is a first comparator, C2 is a second comparator, C3 is a third comparator, R1 is a first register, R2 is a second comparator. 2 registers, R3
Is a third register, and S1 to S3 are data selectors.

In FIG. 1, the rising / falling detection circuit 1 and the transition interval counter 3 constitute a data compression circuit by run-length coding, and the transition interval counter 3, the comparator 4 and the level reproduction circuit are serialized from the run-length code. It constitutes a reproducing circuit for reproducing data. Rise / fall detection circuit 1
Is supplied with a test signal DATA from a circuit under test (UUT) board and a strobe signal STB which is a DATA sampling signal from a card tester, and outputs a transition time point signal indicating the rising and falling edges of the signal DATA. The transition interval counter 3 counts the length between transition time points according to the transition time point signal supplied from the rising / falling edge detection circuit 1 or the comparator 4 through the selector with the strobe signal STB, and outputs a run length code. The comparator 4 compares the transition interval counter 3 with the run length code of the information compression / reproduction circuit 5 and outputs a transition time point signal when they match. The level reproduction circuit 2 outputs, as reproduction data, serial data which rises or falls according to the transition time point signal from the comparator 4. The information compression / reproduction circuit 5 of the present invention further compresses the data of the run length code output from the transition interval counter 3 and writes the compressed data to the main memory 6, or reads the compressed data from the main memory 6 to the run length. FIG. 2 shows the circuit configuration of the first embodiment for reproducing the code and transmitting the data of the run length code to the comparator 4.

In FIG. 2, the data selector S1 selects the run length code from the transition interval counter when performing data compression, and when the compression flag is set in the read data of the main memory 6 during data reproduction. Selects the contents of the third register R3, and selects the read data of the main memory 6 and sends it to the first register R1 when the compression flag is not set in the read data of the main memory 6 during data reproduction. The data selector S2 selects the contents of the coincidence counter 11 when the output of the second comparator C2 changes from a state showing coincidence to a non-coincidence at the time of data compression. Select the contents of register R2. The data selector S3 selects the contents of the maximum value address memory 8 when the output of the maximum value detection circuit 9 indicates that the maximum value has been detected, but otherwise selects the contents of the time series memory address counter 10. Select the content.

The first comparator C1 compares the values of the first register R1 and the second register R2, and the maximum value detection circuit 9 compares the value of the first register R1 with the value of the second register R2. The maximum value signal MAX is output when the state changes from the larger state to the smaller state, and the detailed configuration of the first embodiment is shown in FIG. In Figure 3, JK-FF91
When the Q terminal of the signal changes from the logic "1" state (R1> R2) to the R1 <R2 state, the AND condition of the AND gate 92 is satisfied and the maximum value signal MAX becomes the logic "1". Second comparator C2
Is for comparing the values of the second register R2 and the third register R3.
Is counted, and when the match state changes to mismatch, the value of the match counter 11 is written to the main memory 6 together with the compression flag through the data selector S2. Third comparator C3
Is when the data RD read from the main memory 6 is a repeated count value (compression flag is set),
The count value is compared with the value of the coincidence counter 11, and the content of the third register R3 is written into the first register R1 through the data selector S1 until the comparison results in coincidence.

The operation of the circuit for compressing the run length code input to the first register R1 through the data selector S1 and storing it in the main memory 6 will be described with reference to FIGS. 2 and 4. As described above, at the time of compression, the data selector S1 selects only the run length code which is the output from the run length code generation circuit (transition interval counter),
Also, the third comparator C3 is not used.

Now, it is assumed that the run length code input to the first register R1 through the data selector S1 during compression is (1122311223112234124125) as shown in FIG. As shown in FIG. 4, these run length codes are read from the first register R1 at the next transition time point signal and written in the second register R2. When these values are generalized and shown at the time of transition, the value of the first register R1 becomes the input data of t _n , and the value of the second register R2 becomes the input data of t _n-1 . The first comparator C1 compares the outputs of the first register R1 and the second register R2, and uses the maximum value detection circuit 9 to detect the point at which the maximum value is reached at the timing of T _n-1 . Maximum value detection circuit 9
As shown in FIG. 4, the timings at which the point at which is the maximum value is detected are t ₆ , t ₁₁ , t _17, and t ₂₀ .

The write data of the time series memory 7 is the output of the second register R2, and the output of the second register R2 is written every time. The address of the time series memory 7 at the time of writing is the data selector
Although the output of the time series memory address counter 10 is selected by S3, the address of the time series memory 7 when the maximum value detection circuit 9 specifies the maximum value is the address of the maximum value address memory by the data selector S3. 8 outputs are selected. The read data when the output of the maximum value address memory 8 is used as an address is set in the third register R3. Then, by the second comparator C2, the second register R2
And the contents of the third register R3 are compared. If they match, the output of the maximum value address memory 8 is set in the time series memory address counter 10, but if they do not match, the time series memory address -Only count up the counter 10. The maximum value address memory 8 and the third register R3 which is the read data of the time series memory 7 at the address input by the output of the maximum value address memory 8 when the maximum value is detected by the maximum value detection circuit 9 and the third register R3. 2 register R2
The output of the second comparator C2 by comparison when a mismatch between (t ₆ of
t ₁₇₎ only when the write output sequence memory address counter 10 and the output of the second register R2 to the address.
When the coincidence output is obtained by the second comparator C2, the coincidence counter 11 is counted up, and when they do not coincide, the coincidence counter 11 is cleared. Regarding the write data of the main memory 6, when the output of the second comparator C2 does not match, the data selector S2 selects the output of the second register R2, but the second comparator C2 outputs the match output until the last time. If there is a mismatch, the contents of the match counter before the match counter is cleared are selected by the data selector S2 and written to the main memory 6. At that time, the compression flag is also set to "1". In FIG. 4, “1” of the memory write data “1/4” at the timing t ₁₆ indicates the compression flag, and “4” indicates the value of the coincidence counter 11. This value "4" means that four of the run-length code from the next maximum value of the timing t ₆ "3", or "1122" is repeated.

Next, as shown in FIG. 4, the operation of the circuit in the case of compressing and reading the data stored in the main memory 6 and reproducing it will be described below.
This will be described with reference to FIGS.

The processing of the data RD read from the main memory 6 differs depending on whether it is a repeated count value. When the count value is not the repeat count value (the compression flag is not set), the data RD is written to the first register R1 through the data selector S1. However, if the count value is repeated (compression flag is set), the data
RD compares the content of the coincidence counter 11 with the third comparator C3. The content of the third register R3 is written to the first register R1 through the data selector S1 until the third comparator C3 agrees.

The operation of the other circuits is basically the same as the operation at the time of compression described above. However, in the case where the maximum value is detected in the maximum value detection circuit 9, and the data read from the main memory 6 specifies the repeat count value, the time-series memory address counter is used to match the reproduction timing.
It is necessary to count 10 by one and read the time series memory 7 by one. As described above, the second register R2
The signal output from is output to the run length reproduction circuit (comparator 4 shown in FIG. 1) as a reproduced run length code.

As described above, the present invention selects the maximum value as a feature of the pattern in the time series pattern and uses the maximum value as a trigger. Then, in response to the trigger issued at the maximum value, the set of maximum values is stored in the time series memory. It should be noted that the above description is for the case where the present invention is applied to the test of the circuit board, but it is not limited to the present invention and it can be widely used as a general data compression technique. There is no end.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, long data including a repeating pattern can be efficiently compressed by using a relatively simple mechanism, and the present invention saves memory capacity or transmits data. The role that can be played in improving the efficiency of

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of one embodiment when the present invention is applied to a card tester, FIG. 2 is a diagram showing a configuration of one embodiment of the information compression circuit shown in FIG. 1, and FIG. FIG. 4 is a diagram showing a detailed embodiment of the maximum value detection circuit shown in FIG. 2, and FIGS. 4 and 5 are diagrams for explaining the operation of the circuit shown in FIG. 1 ... rise / fall detection circuit, 2 ... level reproduction circuit,
3 ... Transition interval counter, 4 ... Comparator, 5 ... Information compression circuit, 6 ... Main memory, 7 ... Time series memory, 8 ...
Maximum value address memory, 9 ... Maximum value detection circuit, 10 ...
… Time series memory address counter, 11 …… Match counter, 12 …… Memory address counter, 91 …… JK−
FF, 92 …… and gate, C1 …… first comparator, C2 ……
2nd comparator, C3 ... 3rd comparator, R1 ... 1st register,
R2: second register, R3: third register, S1 to S3
...... Data selector.

Claims (2)

[Claims] 1. A data string composed of a plurality of data elements arranged according to a time series t ₀ , t ₁ , ... T _n-1 , t _n , ... Is compressed and written in a main memory or An information compression / reproduction circuit for reading the written data from a main memory and reproducing the data sequence, comprising a first data selector, a first register for storing a data element from the first data selector, and a first register. A second register for sequentially storing the data elements transferred from the first register, a first comparator for comparing the output of the first register with the output of the second register, and a time series data element from the output of the first comparator Maximum value detection circuit for detecting the maximum value of, a time series memory using the output of the second register as write data, an address circuit for specifying a write address and a read address of the time series memory, and the time series A third register for storing the read data of the memory, a second comparator for comparing the output of the second register with the output of the third register, and a coincidence counter for counting the number of times the second comparator produces coincidence output. , Second data for selecting the output of the second register when the second comparator produces a non-coincidence output and selecting the output of the coincidence counter as compressed data at the time when the non-coincidence output is produced after the coincidence output is produced. selector,
And a third comparator for comparing the output of the coincidence counter with the read compressed data of the main memory, and the first data selector selects the data string input at the time of compression and stores the data of the main memory at the time of reproduction. When the read data is compressed data, the output of the third register is selected, and when the read data is not compressed data, the read data is selected, and the address circuit detects the maximum value when the maximum value detection circuit detects the maximum value. Is configured to specify an address from the specified address at the time of writing when the maximum value of is detected, on condition that a coincident output is obtained by the second comparator, and at the time of compression, the output of the second data selector Is written in the main memory, and the output of the second register is transmitted as reproduction data during reproduction. Compression / playback circuit. 2. The input numerical data input in order is stored in a time series memory, and the maximum value of the input numerical data showing the maximum value and the numerical data showing the maximum value stored in the time series memory. So that the i-th numerical data that follows the latest numerical data and the i-th numerical data that follows the latest numerical data correspond to each other. , The input numerical data is compared with the numerical data stored in the time series memory, and if the comparison result shows a match, the match counter is updated without writing the input numerical data to the memory, When the comparison result does not match, the input numerical data when the mismatch is shown is stored in the memory without updating the match counter, and the comparison result does not match. If there is a change, before storing the input numerical data at the time of indicating a mismatch in the memory, store the repeat count value consisting of the count value of the match counter and the compression flag in the memory and store the match counter in the memory. An information compression / reproduction method which is characterized in that a numerical data string which is cleared and which includes a repeat count value read from the memory is reproduced and outputted as a numerical data string in a state before compression.