JPH0754631B2 - Dual port complementary memory - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to memory cells implemented in complementary (eg CMOS) technology that are independently accessible from two ports.

Description of the Prior Art Conventional memory systems store binary information in memory cells and access the cells in a standard sequence. When the address of the desired cell is provided to the memory subsystem, the requested data is returned. Generally, there is one information path for writing information to the cell and one path for reading information. These are typically multiplexed into a single bidirectional path, providing what is referred to as "single port" memory.

Traditional single-port memory is internally asynchronous.
That is, access times to a plurality of cells do not always occur at regular intervals. However, memories typically require a synchronous interface between them and the bus structures they use to communicate with various other hardware devices. This synchronization usually occurs through time slots multiplexed onto a shared address or data bus. This results in a significant reduction in the bandwidth of individual requests for memory data at the same rate as compared to asynchronous access to any individual memory. In addition, there are applications where synchronization cannot be maintained efficiently. In such cases, solutions are sought for element-level subsystems that provide multiple access paths to the storage array without touching timing issues. Such memories, which allow independent access to memory cells through multiple paths, are called "multiport" memories. The most common type is dual port memory. One problem with such multi-port devices is how to resolve the "conflict" that occurs when two ports request access to the same memory cell. The present invention solves this conflict problem.

SUMMARY OF THE INVENTION In the present invention, a memory cell is provided which comprises a bistable circuit storage element having two nodes of opposite voltage levels. One of the nodes, called the "access node", has a first access transistor of any conductivity type connected to it, which couples the node to the first access port. A second access transistor of opposite conductivity type is also connected to the access node, which connects the contact to the second access port. The first access transistor operates with one logic type (eg, positive logic), while the second access transistor operates with the opposite logic type (eg, negative logic). In this way all conflicts are avoided, even for the same cell. Bi-decision storage elements typically have two cross-coupled complementary inverter parts. Transistors are typically n-channel and p-
A channel field effect transistor is used, but it may be a bipolar type.

DETAILED DESCRIPTION OF THE INVENTION The following detailed description describes complementary (eg, CMOS) dual
Regarding port memory cells. As used herein, the term "access port" or simply "port" refers to a data path for "writing" that transfers information into or out of a memory cell, or "reading" that transfers information out of the memory cell. As shown in FIG. 1, a bistable circuit suitable for implementing the present invention typically includes two cross-coupled complementary inverters (M1-M2 and M3-M4).
The access of information to this bistable circuit is performed only from one node 203 called "access node". This means that the other node 204 can be designed as a true storage node that is not affected by read access requests to the access node. One access device (M5)
Also note that is the p-channel, while (M6) is the n-channel. p-Channel Access An access port that transmits data through a transistor is called a "p-channel" and is called an n-channel access.
The access port associated with the transistor is called the "n-port". The bit and word signals associated with n-channel devices are of the conventional positive logic form, but p
Signals and data associated with channel devices are negative logic unless inverted by additional circuitry. It is possible to read and write cells independently from individual ports with appropriate design compromises. In some applications, for example, where the associated circuitry produces a single result for storage in each cycle, thus requiring only one write port and one write per cycle. Does not need this.

The invention is suitable for implementation in all complementary transistor technologies, including field effect and bipolar technologies, and in particular complementary metal oxide semiconductor (CMOS) technology. However, other types of insulated gate field effect transistors and junction types can also be realized. Under certain processing conditions, it is possible that parasitic diodes may be created, so it is necessary to consider two possible types of cells, both of which are shown in FIG. The figure shows the difference due to the inclusion of the diodes (d1, d2) indicated by the dashed line in the drain lead of the PMOS load transistor.

A precharged bit to establish a known correct state on the bitline before the read cycle begins.
Lines 201 and 202 are used. In a conventional cell configuration with a true and a complementary bit line, steps are taken to properly precharge and balance this bit line pair. Usually, a short circuit device is used to achieve balance before achieving full precharge. This design uses one bit line per port, and also uses positive and negative logic so that the correct voltage on the bit line can be established by complementary precharge. That is, p
Bit line 201 is precharged to a low value (Vss) and n bit line 202 is precharged to a high value (Vdd). The access ports can also have the same logic type (both positive or both negative) by inserting one (or an odd number) inverter between the port and the memory cell. For example, a positive logic level can be provided at this port by inserting one bidirectional inverter between the p-channel access transistor and its associated port.

The read operation is accompanied by independent operation by the p- and n-channel access transistors, providing the effect corresponding to the cell read node. Table 1 shows the relationship between the read and write states on the bit and word lines and the actions taken by the access device. As used herein, the term "state" refers to the voltage at a particular location measured with respect to Vss. The “1” state indicates a high (positive) voltage,
A “0” condition usually indicates a low voltage near zero volts.
Logic states are also identical to voltage states, depending on whether positive or negative logic is used, respectively.
Or vice versa.

In the read operation, only one of the two access transistors performs an active operation. When the p-port is read (line 205 goes low) and the stored state is 1, device M5 conducts and p-bit
Charge line 201 from the Vss precharge level to a more positive level. However, when the stored state is 0, device M5 does not conduct because the gate, drain and source are all Vss. If n ports are read (node 206 goes high) and the stored state is 0, the device
M6 conducts and the n-bit line 202 is charged from the Vdd precharge level to a more negative level. However, when the stored state is 1, the gate, the drain, and the source are all Vdd, and thus the state is not conductive. Therefore, p- and n-
Even if both channel access transistors are simultaneously accessed, only one of them will conduct during a read operation. From this, the asynchronous, non-conflicting features of this cell are evident. Stored cell state accessed
Since the active / passive control of the transistors is controlled, there is no collision even when the same address is requested by both ports.

However, the write operation is not so simple. In the absence of an internal diode, the ability of the cell to write both states independently from individual ports depends on the access transistor writing to one logic value as the source follower, while It depends on the ability to write as a common source transistor for logic. In other words, a compromise of access device to inverter device ratio is required to obtain the optimum cell margin. If only one port is needed for writing, cell margin can be optimized independent of write contention issues.

If the diode (d1) is present and exhibits good cut-off characteristics when it is reverse biased, it is difficult to write 0 to the access node 203 only with the p-channel access device due to the isolation effect of the diode. . If the diode is designed to leak (although this is the preferred condition anyway), the p-channel access transistor can be written as a source follower. For the n-channel access transistor, there is no such constraint because it is directly connected to the access node 203 at the cross-coupling point to the storage inverter and the storage state can be directly controlled.

In the cell where the diodes d1 and d2 do not exist, it is possible to select the state of several sets such that the write operation can be performed from any port. However, there are some restrictions such as asynchronous writing to the same cell from both ports, or reading and writing at the same cell. These can be controlled through access protocols or arbitration to get an acceptable interface.

In the write operation, two access transistors and two complementary inverters are required because each port is required to have a function of writing either logic state in the cell.
There are four possible configurations for the transistors M1, M2. These four states are shown in FIG.
Two schematic diagrams show cell transistors that are actively involved (ie, conducting) in the write operation.

In the case of A and B, the stored memory state Vsm is logical 1
On the other hand, for C and D, Vsm is a logic zero.
Writing is accomplished by inverting the access node of M1 or M2 through the appropriate access device for that port. This is done by setting the corresponding bit line 202 or 201 to the appropriate logic level and activating port access transistor M6 or M5. Since the bit lines must both be set to 1 and 0 levels for writing, access transistors of any conductivity type are typically shared tabs (ie, within the same doped region of a substrate of semiconductor material). It is usually not feasible to boost the bit line to achieve the required drive. That is, when this is done, the transistor junction is forward biased. And p and n
Both types require board generators, and board placement requirements result in design constraints. Therefore,
It is assumed that 0 on the bit line is Vss and Vdd is 1, and boosting is limited to the voltage on the gate electrode of the access transistor. Here, “boosting” means a voltage higher than the power supply voltage, that is, Vdd.
Means to generate a voltage above or below Vss.
It is measured based on ss.

In the case of A in FIG. 2, the stored 1 is written into 0 by the source follower operation of the NMOS access device M6,
It is required to have sufficient gate drive to pull the common point 203 through the transmission points of the feedback inverters M3-M4 (see Figure 1). In the case of B, the PMOS access transistor is required to pull the same common node 203 through the transmission point, but in this case it acts as a common source connected to the transistor. C and D
, The function of the n and p access transistors are inverted and the stored logic state is 0, the access device pulls the common node 203 towards Vss.

To allow independent writing at individual ports, it is necessary to boost the wordline transmission gate above Vdd or above Vss for NMOS or PMOS transistors, respectively. The required gate boost can be known by making simplification assumptions on the operating conditions of the transistor.
For A and C where the source follower behavior is used,
The necessary assumption is that the access device operates in triode mode. This is reasonable as long as the access device gate voltage is boosted to at least V _DS + V _TH . Where V _DS is the drain-source voltage across the access transistor and V _TH is this threshold voltage. Therefore, the required gate drive can be calculated by forming the terminal current equation and solving for the word line voltage, W _WI , at the access transistor gate electrode (ie, node 205 or node 206). . If the gate drive does not meet the previous triode region assumption, the access device can be considered saturated. Suitable equations for the transmission characteristics of PMOS and NMOS transistors in the triode and saturation regions are well known in the art. For example, AS Grove (Physics and Technology of Simiconducto)
r Devices), Jiyoung Wheelie and Sons (J
Ohn Wiley and Sons, Inc.) Publishing, New York, 1967
See year.

In case of B and D, the access device is a common source
It works in mode and the required boost is again here
This can be seen by making assumptions about the operating conditions of the two transistors. Active storage device (M
2) is also in the triode region, but the transfer transistor remains in the saturation region until the storage node moves V _TH away from the stored value. The device then enters the triode region for the remainder of the write operation. To simplify the calculations, it can be assumed that the access device always stays in the triode region.

Next, regarding the required gate boost voltage for A, in which the NMOS access device is required to pull the drain of the common source NMOS transistor from Vss to the transmission point Vtr of the inverter M3-M4 to write to the memory cell. Consider. Depending on the size of the device, the threshold voltage, etc., an amount of boost above Vdd is required to reach Vtr. 2v ≤ Vtr ≤ 3v, V _TH = 0.75v, Vdd = 5v,
With a typical value of access device to load ratio of about 2: 1, four required boosts as a function of transmission voltage Vtr and β ratio of load to access device, A, B, C and B respectively. Was calculated for. The results of these calculations show that for A, for example, the gate should be boosted in the 6 to 17 volt range. For B, a boost of -1.5 to -13 volts is required; for C, 0.5 to -3.1 volts, and for D, 0.5 to 5.8 volts. This boost voltage is based on the negative power supply voltage Vss.

Single Write Port, Dual Read Port: PMOS Inverter Only p-channel transistor is required if a diode is present in the transistor, as it requires conduction through the reverse bias diode (d1) to discharge the access node 203. It is impossible to write 0 state at the access node with. Therefore, an n-channel device is used to write a 0. However, this can be assisted by a p-channel access transistor (M5). That is, the p-channel access transistor is turned on and used to discharge node 207 to a low voltage level when writing a zero. With this assistance, n-channel access
If the transistor (M6) does not have this assistance, the node
When the 0 state is stored at 203, the current that must be conducted when writing a 0 is reduced. If d1 is present, the PMOS port can only write the 1 state, so there is only one full write port coupled to the n-channel access transistor. (However, it is also possible to activate the p-channel access transistor to assist in writing a 1 and thereby assisting in writing a 0 as described above.) This single write port is connected to the array. Shared by devices that request write access. Here, the device to access is selected by arbitration. In this single write port configuration, the device ratio is n or p.
It is optimized to provide adequate write levels without boosting the channel wordlines (206 and 205 respectively). In addition, PMOS and NMOS access transistors are fixed to operate in the saturation region until cell switching occurs. This assumption is that the feedback threshold, Vtr, is usually the gate voltage of the access device at ports 206 and 205, respectively, at their final values.
Assumed to be reached before reaching Vdd and Vss.

FIG. 3 shows that both ports are active to write 1s and 0s when they are tied together to write a cell, ie when the p-channel access transistor (M5) assists the n-channel device (M6). Two circuits are shown below. In each case, the main write current is supplied by the access transistor operating in the common source mode, with the assistance of the device acting as the source follower.
In the case of E, the cell stores 0 (Vsm = 0). Logic 1
(0 at the access node) is written with the cooperation of both p and n channel access transistors. PM
Assuming OS word line 205 is Vss, the drive for NMOS word line 206 can be calculated. If a diode is present, as long as it is forward biased, the PMOS device will assist in writing a 0 level. If the diode is not present, it will assist until both M5 and M6 have been written.

F shows the case where a cell storing 1 (Vsm = 1) is written to 0. Again, both the n and p ports provide the current to write a 0 (0 at the access node). NM
Assuming OS word line 206 to be Vdd, the drive for PMOS word line 205 can be calculated.

The required gate voltage at 206 causes the NMOS access device to drive the common source POMS transistor to Vdd.
From E to the transmission point Vtr. The other port with a gate voltage of 205 is also calculated, and the PMOS access device is a common source NMOS.
It was also calculated for E, where the drain of the transistor is pulled from Vss to the transmission point Vtr. 2v ≤ Vtr ≤ 3v, V _TH =
Calculation results for typical values of 0.75v, Vdd = 5v and load to access device size ratios of about 2: 1 show that the required wordline 206 voltage is 1.2 to 3.3 volts for E, and If required word line
The 205 voltage is shown to be 2.0 to -2.9 volts. Over a wide range of parameters, NMOS gates above Vdd,
Alternatively, writing can be performed without boosting the PMOS gate below Vss.

If one wants to make the n and p bit line ports independent, it is necessary to establish a method for separating the reading and writing of a 1 on the n port and the reading and writing of a 0 on the p port. That is, it is necessary to prevent the bit line precharge voltage during the read operation from interfering with the data stored in the memory cell.
This requirement is necessary because, for any given gate voltage, there is a point where the read precharge level reaches the level at which it will be written and destroys the data in the cell. There are several ways to distinguish read / write. For example, a method of controlling the Qi passance ratio as found in a dynamic memory, a method of controlling the bit line voltage and impedance, etc. are used. In one read mode technique, the bitline is precharged to 2 / 3Vdd for the n port and
Precharged to 1 / 3Vdd. The read / write operation can be separated because the read level is lower than the write level. Sense amplifiers for the n and p ports are set near 1/3 Vdd and 2/3 Vdd for the n and p ports, respectively. The previous states for active and passive read disturb operations are retained and the active read causes the bit line to exceed the set amplifier threshold.

If the diode is present, the read-out proceeds in a similar manner as if the diode were not present. Access devices are directly connected to their corresponding inverter transistors. That is, the PMOS is connected to the PMOS, the NMOS is connected to the NMOS, and the diode is reverse biased for the stored 1 read from the NMOS port to provide additional isolation and also to store from the PMOS port. It is separated by a canceling forward voltage of the diode with respect to zero.

Although the above description has described the case where the present technology is realized in a four-transistor dual complementary invar memory cell, it can be realized in other bistable circuits. For example, non-complementary cross-coupled bistable circuits using 4NMOS transistors and others are well known in the art. Further, as mentioned above, bipolar transistors can be used in both the access device and the bistable storage circuit. In this case, both pnp and npn transistors have their control electrodes (eg, emitters) connected to the storage node.
The base of the access transistor is connected to the word line and the other control electrode (eg collector) is
Connected to one access port and the associated bit line. By doing so, as described above, a contention-free read operation from the cell is possible. Bipolar transistors are usually unidirectional devices. Therefore, it becomes easier to write 1 from one port and write 0 from the other port. Arbitration may be submitted to select the appropriate port for a write operation. Alternatively, bidirectional bipolar devices can be created by appropriate choice of emitter and collector geometry and doping levels.
In this case, writing can be performed from either port, and if necessary, assistance from the other port can be performed.

[Brief description of drawings]

FIG. 1 shows a dual port memory according to the invention implemented in complementary (eg CMOS) technology, and FIGS. 2 and 3 show various cases of active transistors during a write operation. . [Explanation of symbols for main parts] 201,202 …… Port 203,204 …… Node M1−M4 …… Information memory cell M5, M6 …… Access transistor

Claims (6)

[Claims] 1. A first port (eg, 201) and a second port
At least one information memory cell (eg, M1-M) adapted to be accessed from a port (eg, 202) of the
4) having a first node (eg 203) and a second node (eg 204) which are stable at opposite voltage levels and are switchable between the levels in response to an information signal. In an integrated circuit including a memory cell that includes a ballast circuit, the first conductivity type access transistor (eg, M5) passes through the first conductivity type access transistor when the voltage on the control electrode of the first conductivity type is low. Node (eg, 203) of the second conductivity type is coupled to the first port (eg, 201) and the voltage on the control electrode of a second conductivity type access transistor (eg, M6) is high. One node is coupled to the second port through the second conductivity type access transistor, and further, the second node (eg, 204) is connected to either of the ports. An integrated circuit characterized by being prevented from continuing. 2. The integrated circuit according to claim 1, wherein the bistable circuit is a second complementary inverter (eg, M3).
-M4) and a first complementary inverter (M1-
An integrated circuit that includes M2). 3. An integrated circuit as claimed in claim 1, further comprising an inverter coupled between one of said ports and an access transistor coupled to it, whereby a logic level at said port is An integrated circuit adapted to be inverted with respect to a first node. 4. The integrated circuit according to claim 1, wherein the first conductivity type access transistor is a P-channel field effect transistor, and the second conductivity type access transistor is n. An integrated circuit which is a channel field effect transistor, wherein the control electrode is its gate. 5. The integrated circuit of claim 4, wherein the voltage on the gate of the P-channel field effect transistor is applied to the bistable circuit at least during a portion of a write operation to the memory cell. An integrated circuit adapted to be boosted to a smaller negative voltage value than the applied negative power supply voltage. 6. The integrated circuit according to claim 4, wherein at least during a part of the write operation to the memory,
An integrated circuit adapted to boost the voltage on the gate of said n-channel field effect transistor to a positive and smaller voltage value than the negative power supply voltage applied to said bistable circuit.