JPS60179992A - Memory circuit - Google Patents

Abstract

PURPOSE:To accelerate both the reading speed and precharging speed by setting the precharging potential of a bit line at a high sensitivity area of a sense amplifier in case the simultaneous reading of two ports is designated to the same memory cell of a two-port RAM. CONSTITUTION:Bit lines 5 and 5' are set at the power supply voltage; while bit lines 6 and 6' are set at the ground potential respectively. Then a charge redistribution is produced between lines 5 and 6 as well as 5' and 6' when FET25-28 are turned on. In this case, the potentials of lines 5 and 6 set after the redistribution are equal to the mean value of the value at which both terminals are previously precharged and set at levels where the sensitivity of a sense amplifier is highest. The same value of potential is also obtained between lines 5' and 6'. Then the lines 5 and 6 are charged at the potential of a point (a); while lines 5' and 6' are charged at the potential of a point (b) respectively. Thus the sense amplifier can decide correctly ''1'' and ''0''.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides a 2-bot CMOS static RAM in which the same 1I5V data is transferred from both ports of the same memory cell.
&M-Relates to a storage circuit designed to increase the degree of freezing of the overflow.

(Prior Art) The configuration of a conventional 2-bot CMOS static RA IVI is shown in FIG. In the figure, 1 is the electrical voltage terminal, 2
is the brinyage switch drive signal input terminal, 3 is the signal input/output control terminal of the first boat, and 4 is 11 of the second boat.
Tsukijin output control terminal, 5.5' is the data output terminal of the ml boat (5°5' is a complementary signal), 6, 6' is the data output terminal of the R12 boat (6, 6' is a complementary signal) be.

Note that 5.5' and 6.6' are also referred to as bit lines.

Therefore, in the lead-out operation, by applying a high level signal to the terminal 2 in advance, the NMO8 transistors 7, 8, 9 act as precharge switches.
.
, 1.2 or 13°14 are turned on to form a flip-flop, transistors 15, 16, 17,
The signals of 18 memory cells are connected to bit lines 5, 5' or 6.
, 6' and is taken out by a sense amplifier (not shown).
rt” and rOJ are determined.

By the way, in the circuit of the above hpi, the gate transistors of both boats are composed of the same element, and most of them are used for the fast NMO8'. - The precharge potential of the bit line is close to the threshold voltage of the sense amplifier.
The ideal value is 11σ, which increases the sensitivity of the sense amplifier and enables faster readout. Since precharging to /2 requires a complicated circuit, the usual method is to connect the 'power supply voltage terminal l and each bit line 5°5', as shown in Figure 1. 6
．． It has a simple structure in which NMO8) Langisthu, 8, 9, and 10 are inserted as precharge switches between 6' and 6'. On this occasion, NMO8) Ranjstav,
When 8, 9, 10 are on, bit lines 5°5', 6
, 6' is charged only to a value of (lllA voltage) - (threshold voltage of NMO8), and the voltage level f:'K k i - is as close as possible to 1/2 of the pressure. , which prevents deterioration of read speed.

1- However, in the above conventional circuit, the following two
The points were marked as M. In other words, ■Since the precharge switch is used near the cutoff, the p-on resistance becomes large due to the backkate effect9, and the complementary data output j
It takes time to precharge the terminals (5, 57 or 6.6') to the same potential.

■When two boats of the same memory cell are selected at the same time, the stray capacitance of the pit S visible due to the frill-float circuit force is twice that of when only one boat is selected, and the read speed is halved. It becomes.

There were drawbacks such as.

(Objective of the Invention) The present invention has been proposed in view of the above points, and aims to increase the operating speed by guiding the 1 note charge potential (of the bit line during 2-vote access) to the highly sensitive head of the sense amplifier. In addition to increasing the speed, by configuring the precharge switch so that it does not operate near the cutoff, the total
It is an object of the present invention to provide a memory circuit in which it is possible to make one point access time equivalent to one boat access.

(Structure of the invention) In order to achieve the above object, the invention is based on the 2-port 1-CMO
In the S static RAM, a signal output switch tNMO8) is used to connect the memory cell and the first port, and a signal output switch t-PMO8) is used to connect the previous dC memory cell and the second port. Structure 1
In addition, a precharge circuit is provided to precharge the first boat to the ``local'' potential and the second boat to the ground potential, so that when both boats are accessed at the same time, the ``total'' address is The stain source according to the distribution is characterized by outputting a signal near the intermediate potential.
Next, an example of the present invention will be explained using Akira T. Shima's standard 1L model. It should be noted that the embodiments are merely illustrative, and it goes without saying that many changes and improvements can be made without departing from the scope of the present invention.

FIG. 2 shows an embodiment of a two-point CMOS static RAM according to the present invention, in which 1 is a voltage terminal, 2 and 2' are precharge terminals, and 3 is a main body voltage terminal. 1 is the signal output control terminal of the boat, 4 is the signal output control terminal of the second boat, 5, 5' is the data output terminal of the first boat (5, 5' are complementary signals), 6, 6
' is the data output terminal of the second port (6, 6' are complementary IDs). In addition, 5, 5'.

6 and 6' will also be referred to as the hit line.

We congratulate the following actions. First, the transistor 21 functions as a precharge switch by setting the terminal 2 to a high level and the terminal 2' to a low level.

Turn on 22, 23, and 24 and pit! 5.5
' is set to the galvanic voltage, and the bit lines 6 and 6' are set to the ground potential. After that, terminal 2 is set to low level, terminal 2' is set to high level, and transistors 21, 22, 23
.

Turn off 24.

Next, the contents of the memory cell consisting of transistors 29, 30, 31, and 32 are output to the bit line. This process will be explained below for the case of 1-vote read. Now, assuming that the contact points of transistors 29 and 31 are point a, and the contact points of transistors Shu and 32 are point yb, the potentials of these two points a and b are necessarily complementary due to the nature of a free-lag float. For this reason, for example, when the terminal 3f is set to high level and the transistors 25 and 26 are turned on, the bit line 5 becomes a
Charging of the bit line 5' progresses to the potential at point 'b' and to the potential at point b, creating a potential difference between both terminals. Then, this potential difference is amplified by a sense amplifier and used as -CBAMρ output data.

Next, in this circuit, terminal 3 is set to low level, terminal 4 is set to low level, and transistors 25, 26, 27°28
A case of 2-boat readout in which all cells are turned on and the contents of the memory cells are simultaneously output to the first boat and the second boat will be described. As mentioned above, since the bit itM5.5' is precharged to the power supply voltage and the bit line 6.6' is precharged to the ground potential, the transistors 25, 26, 2
When 7 and 28 are turned on, charge redistribution occurs between the hit lines 5 and 6 and the hit lines 5/+, e, and /. That is, since the bit line 5.degree.6 is exclusively traced by the transistors 25 and 27, charges are mutually .eta.L so as to cancel out the difference in potential between the two. In this case, if the free capacitances of bit line 5 and bit line 6 are equal, the pitch after redistribution is
The potential of ilff15.6 is 111, the average of the values at which both terminals are precharged! , that is, when p is 1/2 of the 0' voltage, the sensitivity of the sense amplifier becomes the lowest potential. Unfortunately, a similar operation occurs between the human lines 5' and 6'. Note that in general, in LSI, the lay act butter 7 is formed in a completely symmetrical shape, so the bit lines 5, 6.5'
, 6' have almost the same stray capacitance.

After this, bits KM5 and 6 are set to the potential at point a, and bit line 5'
, 6' are charged to point b'.

At this time, the bit lines 5, 6.5', 6' are near the potential at which the sense amplifier operates with high sensitivity, so the bit lines 5, 5', 6'
Even if the potential difference between bits #6 and 6' is small, the sense amplifier can correctly determine rlJ, rO, and J. Therefore, compared to the conventional circuit shown in FIG. 1, the bit line charge-up time can be reduced. In this way, this circuit brings the precharge potential of the bit line to the highly sensitive area of the sense amplifier when simultaneous two-board readout is specified for the same memory cell of a two-point RAM. The speed when reading 2 ports simultaneously has been improved. 'Also, regarding the precharge switch, PMO8k is used for the transistors 21 and 22 that charge the bit lines 5 and 5' to the power supply voltage.
Since NMO8 is used for the transistors 23 and 24 that charge the bit line 6 and 6' to the ground potential, they can be used in a shell region where the puncture gate effect is small, and can be used to charge the bit line 6.6' to the ground potential. It also has the feature of being able to

(Effects of the Invention) As described above, in the memory circuit of the present invention, the speed when two ports of the same memory cell are simultaneously accessed can be completely improved. If used for data memory of a processor, etc., x+
Operations using the same variables such as x and a' are normal operations! L11 performance is achieved at a computation speed that is approximately the same as the A-speed, and is particularly advantageous in terms of computation speed for processors that frequently perform operations such as x2 in statistical processing, one-legged signal processing, and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional 2-port CIVIOS static ram, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1......Power supply voltage terminal 2. 2'...Brinayage isote drive Ig input terminal 3...NL Ig input/output of boat I Control terminal 4... Second boat's first output control terminal 5.5'... First boat's data output terminal (bit number) 6.6'... Data output terminal (number of bits) of the second boat 21 to 24...Outside the transistors constituting the Brinayage switch, 26...Gate transistor of the first port 27, 28...Gate of the second boat Transistors 29 to 32... Transistors constituting a flip-flop Patent applicant: Nichifu Telegraph and Telephone Corporation

Claims (1)

[Claims] In 2-vote CMOS static RA IvI,
A signal output suite consisting of NMOs transistors connects the memory cell and the second boat, and a signal output suite PMOs connects the memory cell and the second boat.
Consisting of transistors, the &! A brinyage circuit is provided that precharges the voltage of the first boat and the ground potential of the second hole. A memory circuit characterized by outputting all signals near an intermediate potential.