JPH075429A - Method for driving active matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To improve gradation reproducibility, and to eliminate a flicker and prolong the life by making the amplitude of a display signal voltage, supplied to a signal line, different between the positive potential side and negative potential side based upon a polarity inversion reference potential. CONSTITUTION:In consideration of level shifts DELTAVBL and DELTAVWH in black level and white level, the amplitude of the display signal voltage VX supplied to the signal line is set to different values on the positive potential side and negative potential side about the polarity inversion reference potential VB so that an applied voltage VS is in a positive-negative symmetrical state with respect to an opposite common electrode potential VX. Namely, the amplitude of one polarity on the positive potential side is made smaller than the amplitude of the other polarity on the negative potential side. For the purpose, the point O' corresponding to the black level is set to the opposite common electrode potential VC of a liquid crystal cell and then the voltage VS which is symmetrical about the opposite common electrode potential VC at respective display levels from black to white evidently from a point O'P' or O'N' is applied to the liquid crystal cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Recently, active development of a high density active matrix type liquid crystal display device having a large number of pixels for pixel display has been actively conducted. In these liquid crystal display devices, a thin film transistor (T
FT) arrays are often used.

FIG. 7 is a diagram showing an example of the configuration of one pixel of a conventional active matrix type liquid crystal display device. Figure 7
, A signal line X connected to the drain electrode of TFT1 and an address line Y connected to the gate electrode of TFT1
And are provided orthogonally. Further, the source electrode of the TFT1 is connected to one end of the capacitance C _{LC of the} liquid crystal cell and the gate-display electrode capacitance C _GS caused by the gate electrode of the TFT1 and the source electrode also serving as the display electrode overlapping each other. .

That is, TFT of amorphous silicon
In a matrix display in which is used as a drive switching element, only the capacitance C _{LC of the} liquid crystal cell forming each pixel
The signal potential of the pixel is held during one scanning period, and therefore capacitors are not separately provided in parallel. As a result, the display area ratio of each pixel in the matrix display panel is improved. However, on the other hand, since the signal holding capacitor decreases, the gate-source capacitance C _GS
Can not be ignored due to its operation.

FIG. 8 is a waveform diagram for explaining the driving of the pixel shown in FIG. In FIG. 8A, the solid line waveform represents the scanning signal voltage V _Y supplied to the address line Y, and the broken line waveform represents the display signal voltage V _X supplied to the signal line X. Further, FIG. 8B shows the display signal voltage V _S held and written in the capacitance C _{LC of the} liquid crystal cell. That is, as shown in FIG. 8A, the scanning signal voltage V _Y has a frame scanning period T _F. Further, as shown in FIG. 8A, the display signal voltage V _X is inverted in polarity with respect to the polarity inversion reference potential V _B in each frame scanning cycle T _F.
When the scanning signal voltage V _Y and the display signal voltage V _X are supplied to the address line Y and the signal X, respectively, the capacitance C _{LC of the} liquid crystal cell has a liquid crystal having a waveform as shown in FIG. 8B. The cell voltage V _S is written and held, but a level shift ΔV occurs between the final write voltage and the hold voltage. Since this ΔV is superposed on the liquid crystal cell voltage, an imbalance occurs between the inverted positive and negative cell voltages. That is, it decreases by ΔV from the proper value during positive inversion and increases by Δ during negative inversion.

Conventionally, a proposal has been made in Japanese Patent Laid-Open No. 119328/1984 that attempts to equalize the positive and negative voltages applied to cells. That is, the drain voltage of the transistor is biased with respect to the gate voltage by a constant voltage corresponding to ΔV, so that ΔV is compensated.
In addition, as one of the modifications, compensation is performed by applying a bias voltage to the common electrode of the liquid crystal cell. However, this means does not essentially compensate for ΔV.

This level shift ΔV occurs due to the presence of the gate-display electrode capacitance C _GS , which results in the scanning signal voltage V _Y.
When the amplitude of V _G is V _G, it is given by V = {C _GS / (C _GS + C _LC )} · V _G. Here, the capacitance C _LC of the liquid crystal cell is defined by the cell gap d, the area of the display electrode A, and the dielectric constant of the liquid crystal material ε.
_{If LC} and the vacuum permittivity are ε ₀ , then C _LC = {(ε ₀ · ε _LC ) / d} · A is given, but the permittivity ε _LC of the liquid crystal material is the alignment state of liquid crystal molecules, that is, the applied voltage V since changes by _S, given as a function of the applied voltage V _S as _{C LC = K 1 · f (} V S). Therefore, the level shift ΔV is also a function of the applied voltage V _S and is given by ΔV = K ₂ · f (V _S ). Note that K ₁ and K ₂ are constants. Thus, it is understood that when the effective voltage applied to the liquid crystal cell takes various values in image display and the like, the value of the level shift ΔV also changes variously.

FIG. 9 is a diagram for explaining this situation.
The vertical axis V shows the values of the display signal voltage V _X and the voltage V _S applied to the liquid crystal cell. Further, the solid line OP or ON gives the amplitude of the display signal voltage V _X from the black level to the white level, and is represented by a straight line for convenience. Further, a horizontal line V _B passing through the point O indicates the polarity reversal reference potential of the display signal. If there is no level shift ΔV, the projection of the solid line OP or ON on the vertical axis is the display signal voltage V _X and at the same time the applied voltage V _S to the liquid crystal cell. At this time, the opposite common electrode potential of the liquid crystal cell is the polarity reversal reference potential V _B.
Should be used. However, in reality, since the level shift ΔV exists, when the polarizing plate is parallel in the TN type liquid crystal cell, the P point and the N point corresponding to the white level are shifted to the P ′ point and the N ′ point, respectively. Shift to point O'corresponding to the level. Here, the level shift amount ΔV _BL at the O point corresponding to the black level is larger than the level shift amounts ΔV _WH at the P point and the N point corresponding to the white level because the liquid crystal has a small dielectric constant, that is, the liquid crystal. This is because the molecules are almost perpendicular to the direction of the electric field and the capacitance C _{LC of the} liquid crystal cell is smaller than the point P or the point N corresponding to the white level.
Therefore, when the point O ′ is set to the common electrode potential V _C of the liquid crystal cell, the input display signal voltage V _X changes the polarity reversal reference potential V _B.
However, even if the positive and negative amplitudes are the same, the voltage V _S applied to the liquid crystal cell has different values on the positive side and the negative side with respect to the common electrode potential V _C.

[0009]

However, this means that a direct current is applied to the liquid crystal cell, which is not preferable in terms of life, and the fundamental frequency of the voltage V _S applied to the liquid crystal cell is Since it is halved, flicker occurs in the display. Further, if the common electrode potential V _C is increased from the case of FIG. 8, there is a point where flicker disappears, but in this state, gradation reproducibility in display is impaired,
After all, there is no ideal AC drive condition.

In the above-mentioned Japanese Patent Laid-Open No. 59-119328, ΔV _WH
Even if a bias voltage of a minute is applied to the gate with respect to the drain and the source, the curve V _{S in} FIG. 9 is obtained,
Similar problems will remain.

[0011]

According to the present invention, a display signal supplied to a signal line is polarity-reversed in relation to a frame scanning period, and a display having one polarity on the positive potential side with respect to a polarity-reversal reference potential. It is characterized in that the signal amplitude and the display signal amplitude of the other polarity on the negative potential side are set to different values.

[0012]

[Function] Capacitance between the gate and display electrode of the driving transistor,
Also, in consideration of the level shift amount caused by the capacity of the liquid crystal cell, the amplitude of the display signal is made different between the positive side and the negative side, and the positive / negative amplitude ratio of the display signal is preferably 1.5 in order to maintain driving quality. It is good to stop in the range of ~ 3. That is, the amplitude of the display signal voltage on the positive potential side with respect to the polarity inversion reference potential is V
1. When the amplitude of the display signal voltage on the negative potential side corresponding to the same gradation level as V2 is V2, the driving transistor of the n-channel TFT or the complementary TFT pair composed of n-channel and p-channel TFT In some cases V1: V2
= 1: 1.5 to 3 and the drive transistor is a p-channel T
In the case of FT, V1: V2 = 1.5 to 3: 1. As a result, an active matrix type liquid crystal display device can be obtained in which the voltage applied to the liquid crystal is substantially positive and negative and the same amplitude is used for AC driving.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view showing an embodiment of the present invention. Figure 1
As can be seen, in the liquid crystal display panel 10, n (integer) address lines Y ₁ , ..., Y _n and m (integer) signal lines X ₁ , ..., X _m are arranged orthogonally at equal intervals. To be done.
At each intersection of both lines, as shown in FIG.
20 and pixels 21 including pixel display electrodes are arrayed to form a matrix. These address lines Y _1, ..., Y _n and the signal lines X _1, ..., X _m is connected to the address line driving circuit 11 and the signal line driving circuit 12, respectively. Then, the address line drive circuit 11 generates a scanning signal from the vertical scanning start pulse and the vertical shift clock pulse supplied to the input terminals 111 and 112, and sequentially scans the address lines Y ₁ , ..., Y _n.
To drive. In addition, the signal line drive circuit 12 has input terminals 121, 12
Create a sample pulse from the horizontal scan start pulse and horizontal shift clock pulse supplied to 2 and input terminal
The display signal supplied to 123 is sampled and held, converted into a parallel signal, and the signal lines X ₁ , ..., X _m are driven. In the display signal polarity reversing circuit 13, when a unipolar display signal is input to the base of a transistor 134 in which a load resistor 132 and a variable load resistor 133 are connected to an emitter and a collector from an input terminal 131, a unipolar display signal is input to the emitter and the collector. Obtain a display signal of opposite polarity. These display signals are input to the switch circuit 135, and are output as display signals whose polarities are inverted for each frame scanning cycle by the switch control signal supplied to the control terminal 136, and are output via the puffer amplifier 137 and the output terminal 138. , Signal line drive circuit 12
It is supplied to the input terminal 123 of the. By the function of the variable load resistor 133, the amplitude of the display signal voltage on the positive potential side with respect to the polarity reversal reference potential can be adjusted to the negative potential side. After adjustment, it may be replaced with a fixed resistance. The polarity inversion reference potential is determined by the base bias applied to the transistor 134. Further, a voltage lower than the polarity reversal reference potential by a level shift ΔV _BL is applied to the voltage of the common electrode.

FIG. 3 is an equivalent circuit diagram showing an array of field effect transistors such as n-channel TFTs in this embodiment. Signal lines X ₁ , ..., X _m commonly connected to the drain of the field effect transistor 20 for each column. , address lines Y ₁ are commonly connected for each row to a gate of the field effect transistor 20, ... are provided so as to perpendicular to the Y _n. The source of the field effect transistor 20 is electrically connected to the pixel display electrode 21, and the electrode 21, the common electrode 22 and the two electrodes 2 are connected together.
The liquid crystal layer 23 sandwiched between 1 and 22 constitutes a liquid crystal cell, that is, a pixel. A switch composed of the field effect transistor 20 is provided in each of the liquid crystal cells arranged in the n-th row and the m-th column.

FIG. 4 is a sectional view showing a part of the liquid crystal display panel 10 of this embodiment. This liquid crystal display panel 10 has parallel TN type polarizing plates, and as shown in FIG. 4, a light shielding layer 31 is formed on a first transparent substrate 30, and an insulating film 32 is further formed so as to cover the light shielding layer 31. Has been formed. And the insulating film 32
Above the signal lines X ₁ , ..., X _m , a drain electrode 33 integrated with the signal lines X ₁ ,.
Alternatively, the source electrode 34 and the like integrated with the pixel display electrode 21 are formed of a transparent conductive film. Further, a semiconductor layer 35, for example, amorphous silicon is formed so as to cover the gap between the drain electrode 33 and the source electrode 34 located above the light shielding layer 31, and the gate insulating film 36 is further provided above the semiconductor layer 35. A gate insulating film 37 integral with the address lines Y ₁ , ..., Y _n is formed. The portion excluding the pixel display electrode 21 is covered with a protective film 38 such as polyimide, and the pixel display electrode is further formed.
A liquid crystal alignment film 39 is formed on the protective film and the protective film. On the other hand, the counter common electrode 22 and the liquid crystal alignment film 41 are sequentially formed on the second transparent substrate 40. In the color display panel, three primary color filters are provided between the substrate 40 and the counter common electrode 22. The first translucent substrate 30 and the second translucent substrate 40 are sealed at their peripheral portions with an interval of about 10 μm, and the liquid crystal 23 is enclosed in this gap to provide a liquid crystal display panel. 10 are formed.

Next, the operation of the liquid crystal display panel 10 will be described.
The address lines Y ₁ , ..., Y _n are sequentially scanned and driven by a scanning signal from the Y driver, and when T _F is a frame scanning period, the field effect transistors 20 are sequentially turned on for a period of T _F / n for each row. Be brought. When a display signal is simultaneously supplied to the signal lines X ₁ , ..., X _m in synchronization with this scanning, the voltage of this display signal is sequentially written into the capacitors row by row and held for a period of T _F. The held signal voltage is guided to the pixel display electrode 21, and excited according to the display signal voltage of the liquid crystal layer 23 between the pixel electrode 21 and the counter common electrode 22. In this way, an image or the like is displayed.

Hereinafter, the driving of this embodiment will be described with reference to FIGS. FIG. 5 is a diagram corresponding to FIG. 9, and the vertical axis V
Indicates the values of the display signal voltage V _X supplied to the signal line and the voltage V _S applied to the liquid crystal cell. The solid line OP or ON indicates the display signal voltage V _X from the black level to the white level.
For the sake of convenience, and is represented by a straight line for convenience. Further, a horizontal line V _B passing through the point O indicates the polarity reversal reference potential of the display signal. In this embodiment, in consideration of the level shifts ΔV _BL and ΔV _WH at the black level and the white level, the display is supplied to the signal line so that the applied voltage V _S is symmetrical with respect to the common electrode potential V _C. The amplitude of the signal voltage V _X is set to different values on the positive potential side and the negative potential side with respect to the polarity reversal reference potential V _B. That is, assuming a straight line of a desired applied voltage V _S having symmetrical amplitudes in both polarities passing through the common electrode potential V _C , the display signal voltage V is added by adding level shifts ΔV _BL and ΔV _WH at the black level and the white level. _X and the polarity reversal reference potential V _B are obtained. Specifically, the amplitude of one polarity on the positive potential side is made smaller than the amplitude of the other polarity on the negative potential side. PCH
For (phenyl, cyclo, hexane) type liquid crystal with ε parallel (dielectric constant in the direction of the liquid crystal molecular axis) 8 and ε perpendicular (dielectric constant in the direction perpendicular to the liquid crystal molecular axis) is Δε = ε parallel − ε vertical = 4, ε parallel = / ε vertical = 2, and in FIG. 5, assuming that the vertical axis unit is 1 V, ΔV _BL is 4 V, ΔV _WH is 2 V, and both positive and negative signal voltage ratios V _B are used as a reference. Then, 7/3 = 2.3.

It is not desirable that the positive / negative signal voltage ratio is extremely large. Therefore, it is preferable to select the liquid crystal material within a practical range of 1.5 to 3 of ε parallel / ε vertical. When a display signal voltage V _X having an asymmetrical amplitude in such a bipolar polarity as shown in the waveform diagram of FIG. 6 is supplied to the signal line,
By the level shifts ΔV _WH and ΔV _BL , the points P and N corresponding to the white level are shifted to points P ′ and N ′, respectively, and to the points O and O ′ corresponding to the black level. Therefore O '
By setting the point to the common electrode potential V _C of the liquid crystal cell, as can be seen from the dotted line O′P ′ or O′N ′, the liquid crystal cell is centered on the common electrode potential V _C and goes from black to white. A symmetrical voltage V _S is applied at each display level. As a result, this embodiment is excellent in the gradation expression of the display,
Moreover, it does not cause flicker and has a long life.

In FIG. 5, the level shift ΔV is taken into consideration only for the black level and the white level, but ideally, including the intermediate level, the gate-source / display electrode capacitance of the field effect transistor and the liquid crystal cell In consideration of the capacitance and the amplitude of the scanning signal supplied to the address line, the amplitude of the display signal voltage V _X supplied to the signal line at each display level should be set. At this time, OP and ON are not necessarily linear. . In addition, gamma correction may be applied to the display signal in consideration of the characteristics of the liquid crystal display device.
And ON are not straight lines.

Up to now, a field effect transistor having a structure in which the source and the drain are connected to the pixel display electrode and the signal line, respectively, has been used, but the setting of the source and the drain is optional, and conversely, It goes without saying that it is good. Further, the field effect transistor is an n-channel and p-type.
In the case of a complementary TFT pair composed of channel TFTs, it can be used in the same way as in the case of n-channel TFTs, but p
In the case of the channel TFT, the polarity of the voltage is reversed from that in the case of the n-channel TFT. That is, regarding the display signal voltage supplied to the signal line, the amplitude of one polarity on the positive potential side with respect to the polarity inversion reference potential is made larger than the amplitude of the other polarity on the negative potential side.

[0021]

As described above, in the active matrix type liquid crystal display device of the present invention, the amplitude of the display signal voltage supplied to the signal line is changed to the polarity inversion reference potential instead of applying the bias voltage to the polarity inversion reference potential. By changing the positive potential side and the negative potential side with respect to the potential and making the voltage applied to the liquid crystal substantially the same on the positive potential side and the negative potential side, good gradation reproducibility and flicker occur It can have a long service life.

[Brief description of drawings]

FIG. 1 is a schematic view showing an embodiment of the present invention.

FIG. 2 is a schematic plan view showing an example of an array of field effect transistors of the present invention.

FIG. 3 is an equivalent circuit diagram showing an example of an array of field effect transistors of the present invention.

FIG. 4 is a sectional view showing an example of a liquid crystal display panel of the present invention.

FIG. 5 is a diagram for explaining an example of a driving method of the present invention.

FIG. 6 is a diagram for explaining an example of a driving method of the present invention.

FIG. 7 is a diagram showing an example of a configuration of one pixel of a conventional active matrix type liquid crystal display device.

FIG. 8A is a waveform diagram of a scanning signal voltage and a display signal voltage. FIG. 8B is a waveform diagram of the display signal voltage written and held in the capacitance of the liquid crystal cell.

FIG. 9 is a diagram for explaining an example of a driving method of a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

20 …… Field effect transistor X _m …… Signal line Y _n …… Address line

Claims (1)

[Claims] 1. A liquid crystal cell having a plurality of address lines and signal lines arranged orthogonally to each other, scanning the address lines and supplying a display signal voltage to the signal lines in synchronization with the scanning. The liquid crystal layer between the pixel display electrode connected to the signal line via the n-channel thin film transistor and the common electrode facing the pixel display electrode is excited to display an image or the like. A driving method of a display device, wherein the display signal voltage is caused by a change in capacitance of the liquid crystal cell in which an amplitude on a positive potential side with respect to a potential of the common electrode at one display level depends on a voltage applied to the liquid crystal cell. In consideration of the potential fluctuation of the pixel display electrode, the amplitude is made smaller than the amplitude on the negative potential side with respect to the potential of the counter common electrode. Method for driving liquid crystal display device.