GB2034953A - MOS-FET array drive for liquid crystal matrix display - Google Patents

Abstract

A matrix display panel a.c. operated comprises gate lines 2 and perpendicular source lines 1 on a pair of substrates of which one carries a MOS-FET 3 array including one FET for each gate-source line intersection and the other carries a common electrode 19, possibly divided into strips parallel to the gate lines 2, and liquid crystal material between the FET's and the common electrode. The common electrode receives a voltage waveform differing between odd and even scanning frames. In a write mode, the source line is supplied with a pair of positive and negative pulses during odd frames and with zero during even frames. In a non-write mode, the source line is supplied with zero during odd frames and with a pair of positive and negative pulses during even frames. The voltage across a written intersection then alternates, but across an unwritten one is zero. <IMAGE>

Description

SPECIFICATION A matrix type liquid crystal display drive using MOS type field effect mode transistor array silicon substrate BACKGROUND AND SUMMARY OF THE IN VENTION The present invention relates to a liquid crystal display, and more particularly to a circuit for driving a matrix type liquid crystal display panel using MOS type field effect mode transistor (referred to as "MOS-FET" hereinafter) array silicon substrate.

Hughes Aircraft Company introduced a new concept of a matrix type liquid crystal display panel wherein an MOS-FET and a parasitic capacitor were implemented on an SOS (Silicon on Sapphire) or a conventional silicon substrate for each of picture elements.

While details of specification of such panel are fully apparent from "A Liquid Crystal TV Display using a Silicon-On-Sapphire Switching Array" by L. T. Lipton, M. A. Meyer and D.

O. Massetti, paper presented at the 1 975 Society for Information Display Symposium, New York and "A fully integrated MOS Liquid Crystal Video-Rate Matrix Dispaly." presented at International SID Symposium, Boston, Mass., April 1977, its structure and operating principle will be briefly discussed according to such technical article to give a better understanding of the present invention.

Fig. 1 shows a circuit including a MOS-FET and a parasitic capacitor Cs for a respective one of picture elements of the panel and Fig.

2 shows enabling voltage waveforms associated with the circuit of Fig. 1. In the given example the picture elements are only four and aligned in an X-Y matrix to provide a visual matrix display through a proper wiring pattern.

If the source voltage V, and the gate voltage V, are applied from the source electrode 1 and the gate electrode 2 of Fig. 1, then the MOS-FET 3 is placed into the conductive (ON) state so that the parasitic capacitor Cs 5 in parallel with the capacitor CLc 4 of the liquid crystal material is charged via the ON resistance RON of the MOS-FET from the source electrode 1. Therefore, the potential (V drain 1) at the drain electrode 6 varies pursuant to the following formula (1): -t Vdrain 1 = V,(1 - e ) (1) 1 where , = RON(C,c + Cs) Then, if the gate voltage at the gate electrode 2 is charged to a zero potential, the MOS-FET 3 is turned to the cut-off (OFF) state.This leads to that the capacitors CLc 4 and Cs 5 start discharging the cumulative charge thereon through the oFF resistance ROFF of the MOS-FET 3 and the resistance RLC of the liquid crystal material. Since the resis tances R0FF, RLC and RON are correlated as follows, ROFF > > RON, RC RLC > ROFF the process of discharging goes on quite slowly such that the potential (V drain 2) at the drain electrode is held considerably high for a relatively long period of time as defined by the following formula:: -t ' V drain 2 = V, e (2) 2 wherein T2 = (ROFF // RLC) (CLC + CS) As the history of these processes is appar ent from the voltage waveform chart of Fig. 2 the effective voltage at the drain electrode, namely, the effective voltage developing across the liquid crystal unit element is re markably high and assures a high contrast display irrespective of the voltage applied to the source electrode 1 with a small duty factor and a very low effective value.

The cell structure which operates pursuant to the above described principle is illustrated in Fig. 3. Nevertheless, two basic problems have been experienced in enabling the above illustrated display panel with enabling vol tages as indicated in Fig. 2.

(1) As the voltage-current characteristics I - lv) of the MOS-FET are symmetric with respect to the polarity as in Fig. 4, it is difficult to enable the liquid crystal panel with an alternating current voltage including no dc component. This shortens greatly the operat ing life of the liquid crystal panel.

(2) When viewing waveforms of enabling as indicated in Fig. 5 to enable all the picture elements other than one selected by a specific source electrode Stand a specific gate elec trode Gj, the MOS-FET for the selected or disabled one remains in the cut-off (OFF) state but the capacitors L,c + Cs are progressively charged via the OFF resistance ROFF. It is therefore possible that a voltage more than a given threshold voltage level Vth of the liquid crystal material may be applied thereto. The resulting voltage is in the form VLcj as indi cated in Fig. 5 and on-off switching is ef fected between the source voltage Vsj and the gate voltage Voj SO that, while the MOS-FET is in the OFF state, the drain voltage VD jj bears an increased effective value equal to or higher than that in the ON state.This causes an objectionable visual display or a difference in contrast corresponding to the number of the liquid crystal elements enabled at this mo ment.

Accordingly, Hughes Aircraft Company de voted the research activities to develop liquid crystal materials capable of being enabled with a dc voltage without shortening the operating life thereof in order to overcome the problem Ol - However, They were not comparable to those driven by an alternating current voltage. The problem )still remained unsolved and an attempt to ease the problem ( was made by increasing the ratio ROFF/RON of the MOS-FET.

It is therefore an object of the present invention to provide an enabling circuit for a liquid crystal display panel which is free of the above discussed problems Gland (g BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a prior art matrix type liquid crystal display using MOS FETs; Figure 2 is a timing diagram for the illustration of operation of the circuit of Fig. 1; Figure 3 is a cross sectional view of a matrix type liquid crystal display using MOS FETs; Figure 4 is a voltage-current graph of a conventional n-channel MOS-FET; Figure 5 is a timing diagram of the circuit of Fig. 1 in a specific operating state; Figure 6 is a timing diagram of a method of enabling a liquid crystal display according to the present invention;; Figure 7 is a timing diagram of another method of enabling the display according to the present invention; Figure 8 is a cross sectional view of a liquid crystal display used with the drive methods according to the present invention shown in Figs. 7 and 9; Figure 10 is a timing diagram of still another way of enabling the display according to the present invention; and Figures 11 and 12 are a circuit diagram and a timing diagram of an exemplary circuit for producing the enabling wave-forms according to the present invention.

DETAILED DESCRIPTION OF THE INVEN TION As noted earlier, the present invention is powerful to overcome the two problems associated with the prior art device. To resolve the problem 2, the liquid crystal display panel is enabled in accordance with a timing diagram of Fig. 6.

Fig. 6(a) shows waveform of the source voltage Vs which is applied to the (i)th source electrode and has positive and negative polarity components. A pulse width ratio of the positive and negative polarity components is such selected that charging and discharging are effected in the positive and negative directions to reduce an effective voltage value to zero, when the MOS-FET is in the OFF state, in order to compensate for variations in the characteristics of the MOS-FET with respect to the positive and negative polarities. Fig. 6(a) illustrates waveform of the voltage at the source electrode when the picture elements on the (i)th source electrode are subject to the write operation and non-write operation alternatively with respect to each other.It will be noted that the positive and negative pulses of the source voltage are reversed in phase between the odd and even frames to enable the panel in an alternating current fashion.

Figs. 6(b) - 7(d) illustrate waveforms of the gate voltages V,i Vow+ 1 and V0j+ 2 at the (j)th gate electrode through the (j+ 2)th gate electrode which are to be scanned in sequence. In the case where the positive pulse of the gate voltage is applied to the liquid crystal material in conformity with the pulse width of the source voltage, there is applied the gate pulse of the same pulse width as that of the positive pulse of the source voltage. On the other hand, in the case where the negative pulse of the gate voltage is applied to the liquid crystal material, there is applied the gate pulse of the same pulse width as that of the negative pulse of the source voltage. It will be noted that the positive and negative pulses are applied during the odd and even frames, respectively.

Accordingly, the source voltage Vs is applied when it is desired to write intelligence signals onto the electrodes sequentially supplied with the gate pulses as seen from Figs.

6(b) - 6(d). The respective electrodes are held at the zero potential when it is not desired to write. In the example as shown in Fig. 6, the (i,j)th and (i,j+ 2)th picture elements are written whereas the (i,j+ 1)th picture element is not written. The source voltage V5 at the (i)th as indicated in Figs. 6(a) is the voltage waveform which defines the write interval and the non-write interval with respect to the (i)th column picture elements.

The display operation is executed on the liquid crystal material in such a way that the respective ones of the picture elements selected by the source voltage and the gate pulse are supplied with the voltage which alternates in polarity at every field as seen from Figs. 6(e) - 6(g).

As stated above, according to the present invention, the source voltage is bipolar including the positive and negative components and of the varying pulse width to reduce the charging and discharging voltages to zero in the opposing directions when the MOS-FET is off. Even if nothing but one picture element is not desired to write as indicated in Fig. 5, such non-write picture element would never be supplied with voltage because of cross-talk.

Thus, the non-write picture element is written by no means.The display panel of the present invention enjoys a higher contrast and avoids any substantial difference in proportion to the number of the picture elements to be written.

The findings of the inventors' experiments demonstrate that the following pulse width ratios were suitable: pulse width of positive pulse = 0.2 - 0.2-0.05 pulse width of negative pulse One effective way to avoid the above mentioned problem (g according to the present invention will be described below with reference to a timing diagram of Fig. 7. When it is desired to write a selected one of picture elements, the unidirectional source voltage pulse Vs as shown in Fig. 7(a) is supplied to the source electrode of its associated MOS FET. The source voltage pulse is a negative one in the case where the MOS-FETs are of a P-channel and a positive one in the case where they are of an N-channel.The gate voltage pulse V0 as seen from Fig. 7(c) is applied in such a way that the MOS-FET is off during the odd frames and on during the even frames. Since the MOS-FETs are turned on during the odd frames and turned off during the even frames as seen from Figs. 7(a) and 7(c), the drain voltage VD(ON) of the MOS FETs will be in the waveform of Fig. 7(d). The waveform of Fig. 7(d) illustrates only the negative voltage side and, of course, includes a d.c. component. Pursuant to the teachings of the present invention, the common voltage V, with the opposite polarity as seen from Fig.

7(f) is supplied from the common electrode during the even frames. As a result, a differential voltage between the voltages of Figs 7(d) and 7(f), namely, the voltage waveform of Fig. 7(g), is applied across the liquid crystal material to perform the write operation. It is concluded from Fig. 7(g) that the voltage value and waveform of the common voltage Vc may be properly selected in line with the drain voltage VD for supply of an alternating voltage including no d.c. component to the liquid crystal panel.

When a selected picture element of the liquid crystal material is not desired to be written, the source electrode of its associated MOS-FET is supplied with the source voltage Vs(OFF) as seen from Fig. 7(b) together with the gate voltage pulse V0 of Fig. 7(c) in the way that the MOS-FET selecting that picture element is turned off during the odd frames and off during the even frames. Therefore, the drain voltage VD(OFF) of the FET is in the waveform as in Fig. 7(e) and supplied to one electrode of the picture element of the liquid crystal material. The common voltage Vc as seen from Fig. 7(f) is supplied from the common electrode during the odd frames with the resulting similarity in voltage polarity and waveform.Therefore, not potential difference stands between the two opposing electrodes of the panel with the drain voltage VD(OFF) as indicated in Fig. 7(h).

In order to apply the common voltage Vc to the common electrode of the liquid crystal panel in conformity with the uniformly spaced or scanned gate electrode in the above embodiments, it is necessary to make a transparent conductive film 31 in a stripe-like form in parallel with the gate electrodes. A cross sectional view of the resulting liquid crystal display panel is illustrated in Fig. 8 and an equivalent circuit diagram thereof is illustrated in Fig. 9 If it is desired to provide a half-tone display, the amplitude of the source voltage V5 and the common voltage should be varied in accordance with degree of writing. The drain voltage and the applied voltage across the liquid crystal material are illustrated in Figs 7(i) and 7(j).

As stated earlier, according to the present invention, the specific point in time where the MOS-FET is turned on or off differs between the odd and even frames by supplying a selected one of the picture elements on the display panel with the write voltage or reducing the write voltage to zero.

Accordingly, the MOS-FETs are responsive to only good property unidirectional pulses and achieves highly efficient enabling so that the panel is enabled with alternating voltage including no d.c. component to enjoy a relatively longer life.

As is obvious from Fig. 6(e), the voltage waveform applied across the liquid crystal material in the approach to the first problem (g is asymmetric with respect to the positive and negative polarities and contains a substantial amount of a d.c. component. In constrast, the approach to the first problem (t) is not powerful to overcome the second problem (2).

Still another embodiment of the present invention provides an effective measure to overcome both problems (g and (2), as seen from a timing diagram of Fig. 10.

Construction of the liquid crystal display panel is same as in Fig. 8 and its equivalent circuit as in Fig. 9.

Fig. 1 O(a) shows waveform of the source voltage on the (i)th column whereby the respective picture elements are enabled repeatedly in the sequence of the write operation, and the non-write operation. The negative and positive pulses are applied during the period from t, up to t2 and the zero voltage during the periods from t2 to t3 and from t3 to t4.

In order that the TFTs are turned on, off and off in sequence during the period from t, to t4 within the odd frames and turned off, on, and on during the period from t,' to t4' within the even frames, the source voltage is designed together with gate voltage such that the zero voltage stands from t,' to t2' and the negative and positive pulses are applied from t2' to t3' and the negative and posotive pulses are applied from t3' to t4'.

A pulse width ratio of the negative to the positive pulse is established as illustrated with respect to Fig. 7. Fig. 19(b) depicts waveform of the gate voltage on the (j)th line, Fig. 10(c) on the (j+ 1 )th line and Fig. 10(d) on the (j+ 2)th line. As is indicated in Figs. 1 O(b) - 10(d), the gate voltage pulse is sequentially applied to the gate electrodes for sequentially scanning the gate electrodes. Figs 1 9(e) through 1 9(g) depict waveform of the common voltage applied to the common electrode on the (j)th through (j+ 2)th lines, wherein the common electrodes Vq+1 ," Vcj+1 and Vq+2 are supplied to the common electrodes on the same line as the gate electrodes being scanned, during the even frames.

From the foregoing, it is clear that during the odd frames the source voltage on the (i)th column and the gate voltage on the (j)th line are supplied to turn on the MOS-FET at the intersection (i, j) so that the liquid crystal material at the specific picture element (i,j) is supplied with the source voltage and hence the voltage Vac1). This results in writing the specific picture element (i, j).

Since during the next succeeding line scanning the source voltage on the (i)th column is zero at the odd interval, the MOS-FET at the intersection (i, j+ 1) is in the off state and the voltage VLc,7+l across the (i,j+ 1) picture element is also zero.

The same procedure will be repeated during the second succeeding (j+ 2) line without performing the write operation. The procedure continues up to the last line to complete one frame scanning.

During the next succeeding frame, that is, the even frame, the operation of the MOS FETs is reversed. This is because the source voltage is supplied in association with voltage supply to the gate electrode in such a way that the MOS-FET (i,j) is off and the (ij+ 1) is on and the MOS-FET (i,j+ 2) is on.With respect to the picture element of which the associated MOS-FET is off, the voltage is supplied from the common electrode so that the liquid crystal material is supplied with the voltage in the direction opposite to that during the odd frame scanning (see Fig. 10(j)). For the picture element with the MOS-FET in the on state, the liquid crystal material is supplied with the source voltage Vsi and the common voltages V01+1 and V01+2 at the same time.

Since these voltages are identical in polarity, waveform and magnitude, no voltage is therefore applied as best seen from Figs. 1foci) and 10(j).

Fig. 11 shows a concrete circuit for producing the source voltage V of Fig. 10(a) which is to be supplied to the source electrode of the MOS-FET. In Fig. 12, there is illustrated an example of a circuit adapted to generate the common voltages of Figs. 10(e) through t O(g) which are to be supplied to the stripe-shaped common electrodes.

While in accordance with the teachings of the present invention the common electrode is aligned in a stripelike form to render the manufacture of the liquid crystal panel and the enabling circuit somewhat complicated, it is possible to use the MOS-FETs even with poor ROFF/RON and perform an ideal enabling operation as long as there is no difference in operating performances from one MOS-FET to another. The findings of the inventor's experiments indicate that a 1 28 line matrix display bore as high contrast as in a conventional static mode through the use of elements with ROFF/RON~300 It is obvious from those skilled in the art that the present invention is equally applicable to n-channel MOS-FETs by merely changing the polarity of the enable voltages as well as to MOS-FETs deposited on an SOS (Silicon On Sapphire) substrate.

The invention being thus described, it will be obvious that the same may be varied in may ways. Such modifications are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.

Claims (5)

1. A matrix type display device comprising: a matrix type display panel which comprises a plurality of gate lines, a plurality of source lines normal to the gate lines, a pair of substrates with one carrying a an MOS type field effect mode transistor array including a plurality of MOS type field effect mode transistors one for each of the intersections of the gate and source lines and the other carrying a common electrode and liquid crystal material interposed between the transistor array and the common electrode; and means for sequentially scanning said matrix type display panel, said scanning means for supplying the common electrode with the voltage of which the waveform is different between during odd scanning frames and during even ones, wherein upon operation of the MOS type field effect mode transistors an alternating voltage is supplied to a specific picture element of the panel to be written, whereas no substantial voltage is supplied to a specific picture element not to be written.

2. A matrix type display device comprising: a matrix type display panel which comprises a plurality of gate lines, a plurality of source lines normal to the gate lines, a pair of substrates with one carrying an MOS type field effect mode transistor array including a plurality of MOS type field effect mode transistors one for each of the intersections of the gate and source lines and the other carrying a common electrode and liquid crystal material interposed between the transistor array and the common electrode;;and means for sequentially scanning said matrix type display panel, said scanning means for supplying the common electrode with the voltage of which the waveform is different between during odd scanning frames and during even ones, wherein upon operation of the MOS type transistors said voltage having phase 180 out of that of the voltage applied to the common electrode is supplied for a specific picture element of the panel to be written, and that having the same phase as that of the voltage applied to the common electrode is supplied for a non-write picture element to overide the voltage applied thereto.

3. A matrix type display device compris- ing: a matrix type display panel which comprises a plurality of gate lines, a plurality of source lines normal to the gate lines, pair of substrates with one carrying an Mt)s type field effect mode transistor array including a plurality of MOS type field effect mode trans istorsOone for each of the interesections of the gate and source lines and the other carrying a common electrode and liquid crystal material interposed between the transistor array and the common electrode; means for sequentially scanning said matrix type display panel, said scanning means comprising; means for supplying the common electrode with the voltage of which the waveform is different between odd scanning frames and during even ones;; means for supplying the source line with a pair of positive and negative pulses during the odd scanning frames (or the even scanning frames) and supplying the same with the zero voltage during the even scanning frames (or the odd scanning frames) in a write mode; and means for supplying the source line with the zero voltage during the even scanning frames (or the odd scanning frames) and supplying the same with a pair of positive and negative pulses during the odd scanning frames (or the even scanning frames) in a non-write mode.

4. A matrix type display device comprising: a matrix LCD display panel having a plurality of picture elements each of which is controlled by the difference between the voltage at a common electrode on a first substrate of the panel and the voltage provided by a respective one of a plurality of MOS field effect transistors forming an array disposed on a second substrate of the panel, the panel having a plurality of gate lines and a plurality of source lines disposed normal to the gate lines for controlling the MOS field effect transistors, each of which is associated with a respective intersection of the gate and source lines; ;and drive means including means for sequentially scanning the gate lines and means operable to cause the voltage across each picture element to reverse each time the gate line of the respective MOS field effect transistor is scanned when that picture element is selected for display; wherein said drive means is selectively operable to apply a signal including both positive and negative components to a source line each time a gate line is scanned.

5. A matrix type display device substantially as herein described with reference to the accompanying drawings.