JPH0752736B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a III-V group compound semiconductor device, and more particularly, to a compound semiconductor device having electrodes suitable for a large-scale integrated circuit using GaAs. Regarding the method.

[Background of the Invention]

In an integrated circuit using a GaAs semiconductor as a substrate, a MES-FET that uses a metal-semiconductor contact Schottky barrier at the gate is used as a basic component. This FET is
As shown in the cross-sectional view of FIG. 1, an n-type channel layer 2 and an n ⁺ -type source region 3 formed by ion implantation in a substrate 1, a drain region 4 and a gate electrode 5 and a source formed on the respective surfaces thereof. It is composed of an electrode 6 and a drain electrode 7, and is operated by controlling the current flowing between the source electrode 6 and the drain electrode 7 through the channel layer 2 by the electric field applied to the gate electrode 5.

The conventional process for forming MES-FETs on a GaAs substrate is shown in Fig. 2 (1981 International Solid-State Circuits Conferen (IEEE International Solid-State Circuits Conference).
ce] FAM15.6, Feb. 1981). That is, first, as shown in FIG. 2A, an n-type channel layer 2 is formed on a GaAs substrate 1, and then a gate 5 made of a refractory metal is formed. Refractory metals include W, Ti-W alloys, W-Si alloys, W-
Al alloy, tungsten nitride WN, etc. are used. Next, as shown in (b), 2 × 10 ¹³ Si ⁺ ions 8 / cm ² are formed by ion implantation to form source / drain regions.
Drive in. According to this method, the source for the channel layer,
Since the drain region is formed in self-alignment, high performance
FET can be created. Next, as shown in (c), SiO ₂ , Si ₃ N
_After the insulating film 9 such as ₄ is laminated, it is annealed at 700 to 900 ° C. to activate the ion implantation region. Further, as shown in (d), the source and drain electrodes 6 and 7 are formed to complete the MES-FET. The reason for covering the insulating film 9 in (c) is 70
This is to prevent Ga and As on the surface of the GaAs substrate from vaporizing and crystallizing during high temperature annealing at 0 to 900 ° C.

In the above prior art, as shown in FIG. 2 (c), the insulating film 9 is directly coated on the gate electrode 5 made of refractory metal or refractory metal ceramics, and high temperature annealing is performed. Since the adhesive force between the metal or the refractory metal ceramics and the insulating film is weak, the insulating film is peeled off during annealing, and there is a drawback that a sufficient space cannot be provided between the insulating film and the gate electrode. .

[Object of the Invention]

An object of the present invention is to increase adhesiveness with a protective insulating film during annealing by using a gate electrode in which silicon is laminated on a refractory metal or a refractory metal ceramics, and to prevent film peeling of the insulating film. The object of the present invention is to provide a good method for manufacturing a compound semiconductor device in which no gap is generated between the insulating film and the gate electrode.

[Outline of Invention]

In the manufacturing process of a so-called gate precedent self-aligned MES-FET in which the source / drain regions are formed by the ion implantation method using the gate metal as a mask as described in the conventional example of FIG. 2, the gate metal is the source / drain region. It should not be altered or react with the GaAs substrate during the high temperature annealing at 700-900 ℃ to activate the GaAs. For this reason, the gate metal materials are generally W, Mo, Cr, Ta, Nb, V,
It has been proposed to use refractory metals such as Hf, Zr and Ti, and alloys thereof, or nitrides, borides, carbides and silicides of the refractory metals. The gate metal material is formed by an electron beam evaporation method, a sputtering method, a cluster ion beam evaporation method, a vapor phase chemical growth method (CVD method), or the like.

In the manufacturing process of the gate-first self-aligned MES-FET described here, as described in the explanation of FIG.
To activate the drain region, the surface of GaAs was SiO ₂ , Si ₃ N ₄ , and AlN.
It is common to protect with an insulating film such as and perform high temperature annealing. However, in our experiments, the insulating film such as SiO ₂ or Si ₃ N ₄ deposited on the high melting point gate metal material is peeled off during high temperature annealing, or a gap is formed between it and the gate metal material. It was discovered that It was also found that this film had gaps and gaps formed on the gate metal and extended to the GaAs coating portion, and a sufficient protective film effect could not be obtained. Such a film may have cracks or gaps because the adhesion between the high-melting point gate metal material and the insulating film is weak, and the high-melting point gate metal material shrinks due to high-temperature annealing. This is because the expansion coefficient is different and a large stress acts during annealing. To solve this problem, 1) prevent the gate metal material from shrinking even at high temperature annealing, 2) insulating film and gate metal material and GaAs
It is conceivable that the coefficient of thermal expansion of the substrate is made the same, and 3) the adhesive force between the insulating film and the gate metal material is increased. However, among these, the method of realizing 1) and 2) is extremely difficult, and the method of increasing the adhesive force of 3) is the most simple and effective.

The silicon deposited on the refractory metal material by a sputtering method, a vapor phase chemical growth method, a vapor deposition method, or the like is alloyed near the interface by high temperature annealing at 700 to 900 ° C., and the adhesive force with these refractory metals is Become extremely strong. Further, silicon is several 10ASiO ₂ is formed a natural oxide film on the surface, indicating very good adhesion when depositing an insulating film such as SiO ₂ or Si ₃ N ₄ thereon. The insulating film is formed by the well-known vapor phase chemical vapor deposition method, plasma vapor phase chemical vapor deposition method, sputtering method or electron beam evaporation method. That is, if the lower layer is made of a refractory metal, an alloy thereof, or a refractory metal ceramic as the gate electrode and the upper layer in contact with the insulating film is made of silicon, the problems of the prior art are solved.

Example of Invention

 Hereinafter, the present invention will be described with reference to examples.

In the embodiment, the case of using GaAs as the semiconductor substrate will be described, but other InP, InGaAs, AlGaAs, InAlAs, InGaAs
It can also be used for III-V group compound semiconductors.

FIGS. 3A to 3E show the manufacturing process procedure of the embodiment.
First, in (a), Si ⁺ ions are implanted into the surface of the GaAs substrate 1 by an ion implantation method at an acceleration voltage of 40 keV, and then 800
Anneal in hydrogen at 20 ° C. for 20 minutes to form the channel layer 2. Ion implantation concentration, when the acceleration voltage 40 keV, the depletion type FET 4 × 10 ¹² pieces / cm ^2, and an enhancement type in the FET 2 × 10 ¹² pieces / cm ^2. After the channel layer 2 is formed as described above, tungsten silicide (W ₅ Si ₃ ) 5 which is a refractory metal is deposited as a gate metal to a thickness of 300 nm by a sputtering method. Further, a silicon film having a thickness of 50 nm is deposited on the tungsten silicide layer 5. The silicon 5 was deposited by the same sputtering method as tungsten silicide. The sputtering apparatus used had two car sword electrodes in the same vacuum chamber, and after tungsten silicide was deposited, the silicon film 5 was continuously laminated without breaking the vacuum. The film thickness of the silicon 5 is preferably 10 nm or more and 1 μm or less. With a thickness of 10 nm or less, a natural oxide film of several nm is formed in air,
The target function may not be achieved because it may be removed by etching in a subsequent step such as washing with hydrofluoric acid. On the other hand, if the thickness is 1 μm or more, the film thickness of the gate metal becomes too thick, which may lead to breakage of wiring steps when integrated, which is not preferable. Taking into consideration the reduction due to hydrofluoric acid treatment in the subsequent cleaning due to the formation of a natural oxide film, and the fact that a uniform planar structure can be obtained even when integrated, the film thickness of silicon 5 is 30 nm to 10 nm.
Most preferably, it is 0 nm. The method for depositing the silicon 5 may be vapor phase chemical vapor deposition, electron beam vapor deposition, plasma vapor chemical vapor deposition, or cluster ion beam vapor deposition, in addition to sputtering.

Next, it moves to (b). Here, the well-known photolithography technology and the fluorine-based gases (CF ₄ , CHF ₃ , CF ₄ ,
The laminated film of the tungsten silicide 5 and the silicon 10 is processed into a predetermined size by dry etching using + H ₂ , NF ₃ , SF ₆ ). Then, the process proceeds to (c). 1.6 μm thickness over the entire surface
After coating with the photoresist 11 of 1., openings are provided in the source / drain regions by the lithography technique. Then, by the ion implantation method, the acceleration voltage is 175 keV and the concentration is 2 × 10 ¹³ pieces / c.
Si ² ions of m ² are implanted using the photoresist 11 as a mask to form the source region 3 and the drain region 4. Then, the process proceeds to (d). After completely removing the photoresist 11 used as the mask for the ion implantation time, the substrate temperature 430
A 200 nm-thickness SiO ₂ film 9 is formed by the vapor phase chemical growth method at ℃, and this is used as a protective film to anneal at 800 ° C. for 15 minutes in hydrogen to activate the source / drain regions. In addition to the above, the protective film 9 is also formed of Si ₃ N ₄ , SiO ₂ , Al ₂ O ₃ , AlN, BN, SiO _x N _y , which is formed by a plasma chemical vapor deposition method, a sputtering method, an electron beam evaporation method or the like. Etc. can be used similarly. After this, the source / drain electrodes 6, 7 such as AuG
By vapor-depositing e / Ni / Au, a FET using a semiconductor-metal Schottky junction is completed as shown in (e).

〔The invention's effect〕

According to the present invention, the refractory gate metal of a compound semiconductor and Ga
By inserting a silicon layer with a thickness of 10 nm to 1 μm, which has a strong adhesive force even when the temperature is high, between the insulating films that are protective films on the As surface, Stable FET characteristics can be obtained without film peeling or voids. Therefore, a GaAs large-scale integrated circuit using them can be manufactured with good controllability.

[Brief description of drawings]

FIG. 1 is a sectional structural view of an FET using a metal-semiconductor Schottky junction, FIG. 2 is a diagram showing a manufacturing process of a GaAs MES-FET according to a conventional technique, and FIG. 3 is a diagram for explaining an embodiment of the present invention. Is. 1 ... Semi-insulating GaAs substrate, 2 ... Channel layer, 3 ... Source region, 4 ... Drain region, 5 ... Refractory metal gate, 6 ... Source electrode, 7 ... Drain electrode, 8 ... Si
⁺ Ion, 9 …… GaAs surface protective insulating film, 10 …… silicon film, 1
1 ... photoresist

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junji Shigeta 1-280, Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Research Laboratory Hitachi, Ltd. Central Research Laboratory Makoto Onoda (56) Reference JP-A-56-73469 (JP, A) JP-A-51-147273 (JP, A) JP-A-59-119764 (JP, A)

Claims (2)

[Claims] 1. A step of depositing a first layer made of a refractory metal or a metal ceramic for forming a Schottky junction with the compound semiconductor substrate on the compound semiconductor substrate, and a film thickness of 10 nm or more on the first layer. A step of depositing a second layer of silicon having a thickness of 1 μm or less, a step of processing the first layer and the second layer by dry etching to form a gate electrode of a field effect transistor, and the gate electrode Forming a source region and a drain region by ion implantation using the mask as a mask, covering the gate electrode, the source region and the drain region with an insulating film, and annealing the source region after the insulating film covering process. And a method of manufacturing a compound semiconductor device, comprising the step of activating the drain region. 2. The method for manufacturing a compound semiconductor device according to claim 1, wherein the film thickness of the second layer is 30 nm or more and 100 nm or less.