JPH075186A - Speed detector - Google Patents

Abstract

PURPOSE:To reduce current consumption of a speed detector. CONSTITUTION:The speed detector comprises a sensor 1 principally producing a pulse corresponding to the position or the speed of an object 10 to be measured, a circuit 5 for generating reference clock signal Ck, and a counter 7 for measuring the time interval of a pulse from the sensor 1 based on the reference clock signal Ck. The speed detector further comprises a clock gate 6, disposed between the reference clock generating circuit 5 and the counter 7, for obtaining a speed signal based on a count received from the counter 7 and opened by a detection signal Sp received from the sensor 1 through an oscillation removing circuit 4, for example, whereas closed by a gate close signal received from the counter 7. When the count of the counter 7 is not required, the clock gate 6 is closed by the gate close signal to interrupt provision of the reference clock signal Ck to the counter 7 thus suppressing current consumption of the counter 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed detecting device. More specifically, the present invention relates to reduction in current consumption of a speed detection device.

[0002]

2. Description of the Related Art Conventionally, this type of speed detecting device is mainly
An encoder, a reference clock generation circuit, and a counter are provided, and an output pulse from the encoder is frequency-divided by a frequency divider and input to the counter, and a reference clock from the reference clock generation circuit is applied to the counter. The counter has been proposed as a device for counting the intervals of the output pulses with the reference clock and obtaining a speed signal based on the counted value (see Japanese Patent Laid-Open No. 1-276071).

According to such a speed detecting device, the time interval of the output pulse detected by the encoder can be accurately measured by the counter, and the speed signal can be obtained by the reciprocal of the measured value of the time interval.

[0004]

However, in this speed detecting device, the reference clock is always flowing from the reference clock generating circuit regardless of the presence or absence of the output pulse from the encoder. Even when the body is stopped, a part of the internal circuit of the counter continues to operate, and the reference clock flows due to the electrostatic capacity inside the counter and the current consumption increases. Therefore, it is extremely disadvantageous when the speed detecting device is incorporated by using a battery as a power source.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a speed detecting device capable of low current consumption.

[0006]

In order to achieve the above object, a velocity detecting device according to the invention of claim 1 generates a sensor for outputting a pulse according to the position or velocity of the object to be measured and a reference clock. A reference clock generating circuit, and a counter for measuring the time interval of the pulse from the sensor based on the reference clock from the reference clock generating circuit, in a speed detection device for obtaining a speed signal based on the measured value from the counter, The pulse from the sensor opens the gate,
A clock gate for closing the gate by the gate closing signal from the counter is provided between the reference clock generating circuit and the counter.

Here, it is desirable that the counter be capable of outputting an overflow signal or a constant count value as a gate closing signal.

Further, in order to achieve the above object, a speed detecting apparatus according to a fourth aspect of the invention is a sensor for outputting a pulse according to the position or speed of an object to be measured, and a reference clock generating for generating a reference clock. The circuit, the vibration elimination circuit that makes a detection pulse when a predetermined number of pulses are continuously input in the same rotation direction from the sensor, and the time interval between the pulses output from the vibration elimination circuit A counter for measuring based on a reference clock is provided, and a speed signal is obtained based on a measurement value from the counter.

Further, the vibration elimination circuit logically ANDs a flip-flop operated by a clockwise detection pulse or a counterclockwise detection pulse with a clockwise detection pulse and an output signal on the side inverted by the clockwise detection pulse. One logical product circuit, a counterclockwise detection pulse, a second logical product circuit that takes the logical product of the output signal on the side that is inverted by the counterclockwise detection pulse, and a logical sum that takes the logical sum of the outputs of the respective logical product circuits It is desirable to have a circuit.

[0010]

According to the present invention, the interval between pulses from the sensor capable of detecting the position or speed of the object to be measured is counted by the counter using the reference clock, and the reference clock signal is sent to the counter via the clock gate. The clock gate is closed by the gate closing signal when the count is not necessary, and the supply of the reference clock signal to the counter is stopped. Therefore, the reference clock signal is not supplied to the counter.

Further, according to the invention described in claim 4, when the vibration state is not detected by the vibration elimination circuit from the output pulse from the sensor capable of measuring the position or speed of the object to be measured, it is constant in the clockwise or counterclockwise direction. The detection pulse is prevented from being output from the vibration eliminating circuit and the speed detection is not started unless the rotation starts at an angle or more, that is, unless the pulse is continuously obtained for a predetermined number of pulses or more.
Therefore, the reference clock signal is not supplied to the counter or the like until the speed detection is surely required.

[0012]

The present invention will be described below with reference to the illustrated embodiments.

FIG. 1 shows an embodiment of the speed detecting device of the present invention. This speed detecting device is composed of a sensor element 2 and a pulse generating circuit 3, which outputs a pulse in accordance with the movement of a device under test 10, a vibration eliminating circuit 4, a reference clock generating circuit 5, a clock gate 6, and a counter 7. , A hold circuit 8 and a conversion circuit 9.

The sensor element 2 is composed of, for example, a magnetic sensor such as a magnetoresistive element. When the magnetic poles provided on the object to be measured 10 rotate, the A phase and the B phase (A phase and Outputs a detection signal of 90 degrees out of phase). The sensor element 2 is connected to the pulse generation circuit 3, and constitutes the sensor 1 which supplies the A-phase detection signal and the B-phase detection signal to the pulse generation circuit 3 and outputs a pulse according to the movement of the measured object 10. is doing.

The pulse generating circuit 3 has a clockwise (hereinafter abbreviated as CW) pulse and a counterclockwise (hereinafter abbreviated as CCW) pulse based on the supplied A-phase detection signal and B-phase detection signal. Is formed and output. The pulse generation circuit 3 is connected to the vibration elimination circuit 4 and is provided so that the CW pulse and the CCW pulse can be introduced into the vibration elimination circuit 4. The CW pulse and the CCW pulse output a pulse having a predetermined width under the condition of the logical product of the A phase and the B phase at the rising edge of the A phase in any rotation direction.

The vibration elimination circuit 4 is a circuit for preventing the detection pulse Sp from being generated by regarding the first n pulses in which the operation direction of the object to be measured 10 is reversed as vibration, and for example, the input CW pulse and CCW pulse. Based on the above, the predetermined pulse number n (the first pulse in the case of this embodiment) can be removed from the time when the CW pulse is changed to the CCW pulse or the CCW pulse is changed to the CW pulse, and the vibrations that come and go between the CW pulse and the CCW pulse The vibrations can be eliminated even when the above occurs, and the CW pulse and the CCW pulse after the number of predetermined pulses is exceeded can be output as the detection pulse Sp. The output of the vibration eliminating circuit 4 is the gate opening control terminal of the clock gate 6, the reset terminal of the counter 7, and the hold circuit 8.
Is connected to the control terminal of the gate, and the detection pulse Sp from the vibration elimination circuit 4 is supplied to the gate opening control terminal of the clock gate 6,
It can be supplied to the reset terminal of the counter 7 and the control terminal of the hold circuit 8.

The reference clock generation circuit 5 is a circuit that can generate the reference clock Ck. Reference clock generation circuit 5
The output terminal of is connected to the input terminal of the clock gate 6, and the reference clock Ck is input to the clock gate 6.

The clock gate 6 can open the gate by the detection pulse Sp to input the reference clock signal Ck from the reference clock generating circuit 5 to the counter 7, and close the gate by the gate closing signal Sc to output from the reference clock generating circuit 5. The reference clock signal Ck of 1 is not supplied to the counter 7.

The counter 7 starts counting after the count value becomes zero by the detection pulse Sp input to the reset terminal, and outputs an overflow signal (carry) to the clock gate 6 as a gate closing signal S _L. Here, the overflow signal S _L is for closing the clock gate 6 and stopping the clock supply to the counter 7, and may have a certain set value. That is, if the speed information is meaningless below a certain speed, the counter may be stopped at a counter value that is less than that speed. The output terminal of the counter 7 is connected to the input terminal of the hold circuit 8 so that the count value of the counter 7 can be given to the hold circuit 8.

The hold circuit 8 holds the count value of the counter 7 when the detection pulse Sp is input, and holds the count value until the detection pulse Sp is input next. The output of the hold circuit 8 is the conversion circuit 9
Of the hold circuit 8 and supplies the hold value of the hold circuit 8 to the conversion circuit 9.

The conversion circuit 9 is a circuit capable of converting the hold value into a speed signal and outputting the speed signal.

FIG. 2 shows an example of a specific configuration of the vibration elimination circuit in the above embodiment.

The vibration elimination circuit 4 shown in FIG. 2 comprises a JK flip-flop 41, a first AND circuit 42, a second AND circuit 43, and an OR circuit 44 as follows. . The CW pulse from the pulse generation circuit 3 is J
It is input to the J input terminal of the -K flip-flop 41 and the input terminal of the first AND circuit 42. The CCW pulse from the pulse generation circuit 3 is input to the K input terminal of the JK flip-flop 41 and the input terminal of the second AND circuit 43. The output signals from the first AND circuit 42 and the second AND circuit 43 are OR circuits 44.
Is input to each input terminal from. The detection pulse Sp is output from the output terminal of the OR circuit 44. In addition,
The clock input terminal of the JK flip-flop 41 is
The reference clock signal Ck is supplied.

The operation of the above embodiment will be described below. <Operation of the Embodiment Shown in FIG. 1> First, the operation of the embodiment shown in FIG. 1 will be described with reference to the timing chart of FIG. In FIG. 3, the horizontal axis represents time t, and the vertical axis represents A phase detection signal, B phase detection signal, and pulse generation circuit 3.
CW pulse and CCW pulse from, the count value of the counter 7, the overflow signal of the counter 7, and the output of the clock gate 6 are respectively shown.

When the object to be measured 10 rotates, the object to be measured 10
The A-phase detection signal and the B-phase detection signal are output from the sensor element 2 due to the change of the magnetic flux from the magnet provided in the. The A-phase detection signal and the B-phase detection signal are input to the pulse generation circuit 3, and a CW pulse and a CCW pulse are formed based on the A-phase detection signal and the B-phase detection signal. The CW pulse and CCW pulse from the pulse generation circuit 3 are input to the vibration elimination circuit 4.

The vibration removing circuit 4 removes a predetermined number of pulses, for example, the first pulse from the time when the CW pulse is changed to the CCW pulse or the CCW pulse is changed to the CW pulse based on the input CW pulse and CCW pulse, and at the same time, the CW pulse is removed. Even if a vibration coming and going between the pulse and the CCW pulse occurs, the vibration is removed. Then, after the removal operation at the time of inversion or when there is no vibration, the vibration removal circuit 4 outputs the detection pulse Sp from these CW pulse and CCW pulse. The detection pulse Sp of the vibration removing circuit 4 is supplied to the gate open control terminal of the clock gate 6, the reset terminal of the counter 7, and the control terminal of the hold circuit 8.

When the detection pulse Sp resets the counter 7 and opens the gate of the clock gate 6 at, for example, time t ₀ , the counter 7 receives a reference clock signal from the reference clock generation circuit 5 via the clock gate 6. Ck is input. Then, the counter 7 displays the time t
_{After 0} , the reference clock signal Ck is counted.

The count value of the counter 7 is a hall value every moment.
Input to the circuit 8 at time t ₁Shake again
When the detection pulse Sp is input from the motion elimination circuit 4, this
Time point (time t₁The count value in) is held by the hold circuit 8.
It will be held and the counter 7 will be reset.
Also, at this time, the clock gate 6 receives the gate closing signal.
S_LIs not input, clock gate 6 gate
Is still open, but temporarily the gate of clock gate 6
Even if is closed, the gate may be opened by the detection pulse Sp.
Becomes Therefore, the counter 7 again indicates the time t.₁Since
Then, the reference clock signal Ck is counted.

The value held by the hold circuit 8 is input to the conversion circuit 9. The conversion circuit 9 takes, for example, the reciprocal of the input value, converts it into a speed signal, and outputs the speed signal.

On the other hand, the counter 7 counts the reference clock signal Ck again after the time t ₁ . Count value of the counter 7 is inputted every moment to the hold circuit 8, at time t _2, the again, if the detection pulse Sp is input from the vibration eliminating circuit 4, the time (time t ₂₎
The count value of is held by the hold circuit 8, and the counter 7 is reset at this time (time t ₂ ). Then, the value held by the hold circuit 8 is input to the conversion circuit 9, and the conversion circuit 9 takes the reciprocal of the value and converts the value into a speed signal for output. The above operation is
The same applies from time t ₂ to time t ₃ .

Here, for example, when the detection pulse Sp is not input even when the time t ₄ is reached, the counter 7 is
The count value overflows, and the counter 7 resets itself and outputs an overflow signal. This overflow signal is input to the clock gate 6 as the gate closing signal S _L. As a result, the clock gate 6 closes the gate.

Therefore, the reference clock signal Ck is not input to the counter 7 until the detection pulse Sp is input to the clock gate 6 again (until the time t ₅ is reached) (see FIG. 3). . This makes the counter 7
Part of the internal circuit does not operate, and the reference clock signal C
k is also not affected by the internal capacitance of the counter 7. As a result, current saving can be achieved.

In the above embodiment, the overflow signal from the counter 7 or the constant count value of the counter 7 is used as the gate closing signal S _L. This gate closing signal S _L is used for switching between the low speed sensor and the high speed sensor. You can also Further, by using the speed signal or the like from the speed detection device, when the rotation is performed at an extremely low speed (including stop), the speed detection can be stopped to achieve low current consumption.

<Detailed Operation of Vibration Eliminating Circuit 4>
Next, the operation of the vibration elimination circuit 4 shown in FIG.
This will be described with reference to the timing chart of FIG. In FIG. 4, with respect to the time t shown on the horizontal axis, the vertical axis shows the reference clock signals Ck, CW pulses, CCW pulses, the Q output signal of the JK flip-flop 41, and the first AND circuit 4.
2 output signal Sa, second AND circuit 43 output signal S
b and the output signal Sc of the OR circuit 44 are shown, respectively.

At time t ₁₀ , the Q output of the JK flip-flop 41 is indefinite, so that it is indicated by XXX in the figure.

In this state, when time t ₁₁ is reached,
Since the CW pulse is "1", the reference clock signal Ck
At the rising edge of, the Q output of the JK flip-flop 41 is inverted to "1". However, immediately after the Q output of the JK flip-flop 41 is inverted to "1", the CW
Since the pulse is "0", the first AND circuit 4
The output signal Sa of No. 2 becomes "0". Therefore, the output signal Sc of the logical sum circuit 44 also remains "0".

After that, at time t ₁₂ , the CW pulse becomes “1” from time t ₁₂ to time t ₁₃ , and the Q output of the JK flip-flop 41 is “1”, so that time t ₁₂
At to time t ₁₃ the output signal Sa of the first AND circuit 42 becomes "1". Therefore, the signal Sc output from the OR circuit 44 outputs "1".

[0038] Similarly, reached at time t _14, the time t ₁₄ ~ time CW pulse becomes "1" until t _15, the Q output of the J-K flip-flop 41 is "1", the time t ₁₄
At to time t ₁₅ the output signal Sa of the first AND circuit 42 becomes "1". Therefore, the signal Sc output from the OR circuit 44 outputs "1".

By the way, after the time t ₁₅ , the sensor element 2 detects the reversal of the device under test 10, and the CW is performed at the time t ₁₆ .
It is assumed that the CCW pulse is generated from the pulse. At this time, since the CCW pulse is not "1", the J-K flip-flop 41 does not change even when the reference clock signal Ck rises.
Q output of is not inverted.

However, when the reference clock signal Ck rises at time t ₁₇ , the Q output of the JK flip-flop 41 is inverted to "0" because the CCW pulse is "1" at this time (time t). ₁₈ ). Therefore,
The inverted Q output of the JK flip-flop 41 becomes "1", the CCW pulse becomes "1" in the period from time t _{19 to} t ₂₀ , and the output signal Sb of the second AND circuit 43 becomes "1". 1 ”
Since the signal Sc of the OR circuit 44 becomes "1" (time t ₁₉ ~t _20). This means that, for example, the device under test 10
Is rotating clockwise, and when it is reversed and rotated counterclockwise, the pulse output first from the sensor 2 (that is, a predetermined number of pulses) is deleted.

By performing such an operation, for example, even in an oscillating state in which the CCW pulse is inverted to the CW pulse and the CW pulse is immediately inverted to the CCW pulse (time t _{20 to} t ₂₆ ), the first The output signals Sa and Sb are never output from the AND circuit 42 and the second AND circuit 43. This is because the first pulse inverted from the CCW pulse to the CW pulse (time t _{21 to} t ₂₂ ) is deleted by operating as described above, so the output signal Sa from the first AND circuit 42 is deleted. Is not generated (time t _{21 to} t ₂₃ ), and similarly, the first pulse in which the CW pulse is inverted to the CCW pulse (time t _{24 to} t ₂₅ ) is deleted by operating as described above. , The output signal Sb from the second AND circuit 43 is not generated (time t _{24 to} t ₂₆ ). Therefore, the signal S of the OR circuit 44
c becomes "0".

Since the vibration elimination circuit 4 shown in FIG. 2 operates as described above, the OR circuit 44 detects the vibration even when the vibration state in which the inversion is repeated between the CCW pulse and the CW pulse is repeated. The pulse Sp (signal Sc) is never output.

The vibration removing circuit 4 detects the detection pulse Sp (signal) after the measured object 10 does not vibrate and starts rotating CW or CCW by a constant pulse value or more (two or more pulses in the embodiment). Since Sc) is output, the speed detecting device does not start speed detection until the detection pulse Sp comes, so that the current consumption can be reduced.

As described above, in the present embodiment, the device for rotating the object to be measured 10 is explained, and the circuit for measuring the rotation by the sensor 2 is explained, but the present invention is not limited to this, and other Can also be applied to the example.

The above embodiment is one example of the preferred embodiment of the present invention, but the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. For example, in the present embodiment, the pulse of the sensor 1 is passed through the vibration removing circuit and then input to the clock gate 6 as the detection pulse Sp from which the vibration component is removed. However, the pulse of the sensor 1 is directly input to the clock gate 6. Then, the clock gate 6 may be opened by the pulse from the sensor 1 and the gate may be closed by the gate closing signal S _L from the counter 7.

[0046]

As described above, according to the first aspect of the invention, the interval of the detection pulse from the sensor capable of detecting the position or speed of the object to be measured is counted by the counter using the reference clock, and the reference is used. The clock signal can be supplied to the counter via the clock gate, and the clock gate is closed to stop the supply of the reference clock signal to the counter when the count is not needed. This is suitable when the power source is composed of a battery or the like.

According to the fourth aspect of the invention, when the vibration state is not detected based on the output pulse from the sensor capable of measuring the position or speed of the object to be measured, it starts to rotate clockwise or counterclockwise more than a certain amount. Unless the speed detection is started, the current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a speed detection device according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration example of a vibration elimination circuit used in the same embodiment.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

FIG. 4 is a timing chart for explaining the operation of the vibration elimination circuit of FIG.

[Explanation of symbols]

 1 sensor 2 sensor element 3 pulse generation circuit 4 vibration elimination circuit 5 reference clock generation circuit 6 clock gate 7 counter 8 hold circuit 9 conversion circuit 10 object to be measured

Claims (5)

[Claims] 1. A sensor for outputting a pulse according to the position or speed of an object to be measured, a reference clock generation circuit for generating a reference clock, and a time interval of pulses from the sensor as a reference from the reference clock generation circuit. In a speed detection device that includes a counter that measures based on a clock, and further obtains a speed signal based on a measurement value from the counter, the gate is opened by a pulse from the sensor, and the gate is closed by a gate closing signal from the counter. A speed detecting device, wherein a closing clock gate is provided between the reference clock generating circuit and the counter. 2. The speed detecting device according to claim 1, wherein the counter is adapted to output an overflow signal as a gate closing signal. 3. The speed detecting device according to claim 1, wherein the counter is configured to output a constant measurement value as a gate closing signal. 4. A sensor that outputs a pulse according to the position or speed of the object to be measured, a reference clock generation circuit that generates a reference clock, and a predetermined number of pulses continuously input in the same rotation direction from the sensor. And a counter for measuring the time interval of the pulse output from the vibration removing circuit based on the reference clock from the reference clock generating circuit. A speed detection device characterized in that it is configured to obtain a speed signal based on a value. 5. A first logical product that obtains a logical product of a flip-flop that operates by a clockwise pulse or a counterclockwise pulse, a clockwise pulse and an output signal on the side that is inverted by the clockwise pulse. A circuit, a second AND circuit that takes a logical product of the counterclockwise pulse and the output signal on the side that is inverted by the counterclockwise pulse, and a logical sum circuit that takes the logical sum of the outputs of the respective logical product circuits. The speed detecting device according to claim 4, wherein