JPH0750917B2 - CCD color image sensor drive circuit - Google Patents
CCD color image sensor drive circuitInfo
- Publication number
- JPH0750917B2 JPH0750917B2 JP59147762A JP14776284A JPH0750917B2 JP H0750917 B2 JPH0750917 B2 JP H0750917B2 JP 59147762 A JP59147762 A JP 59147762A JP 14776284 A JP14776284 A JP 14776284A JP H0750917 B2 JPH0750917 B2 JP H0750917B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- electrode
- color image
- drive circuit
- ccd color
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003384 imaging method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 （イ） 産業上の利用分野 本発明は、フレームトランスフア型のCCDカラー撮像素
子の駆動回路に関する。The present invention relates to a drive circuit for a frame transfer type CCD color image pickup device.
（ロ） 従来技術 フレームトランスフア型CCDカラー撮像素子のクロスゲ
ート電極構造に付いては昭和59年２月24日付のテレビジ
ヨン学会技術報告の予講集TEBS94−5ED774の第26頁にも
開示されている。第３図はこのクロスゲート電極構造を
示す平面図であり、第１層の第２電極（E2）…と第４電
極（E4）…（水平電極）は、基板上に縦方向に等間隔で
形成されたチヤンネルストツパ（ST）…に対し、直交す
る方向に交互に形成されている。また、第２層の第１電
極（E1）…と第３電極（E2）…（垂直電極）とは、前記
チヤンネルストツパ（ST）上に交互に形成されており、
電極が形成されない格子目部分を受光エリア（Ｄ）…と
している。この受光エリア（Ｄ）…は左側又は右側に第
１電極（E1）…又は第３電極（E3）…によつて蓄積エリ
ア（CL）（CR）…を形成しており、そのパターンは、水
平方向及び垂直方向に関して交互であり、第１電極（E
1）…及び第３電極（E3）…はそれぞれ同一形状とな
る。尚図中符号（OF）はチヤンネルストツパ（ST）内の
オーバフロードレインである。(B) Prior art The cross gate electrode structure of the frame transfer type CCD color image pickup device is also disclosed on page 26 of TEBS94-5ED774, a preliminary lecture of the technical report of the Television Society of Japan on February 24, 1984. ing. FIG. 3 is a plan view showing this cross-gate electrode structure, in which the second electrode (E2) ... And the fourth electrode (E4) ... (horizontal electrode) of the first layer are arranged on the substrate at equal intervals in the vertical direction. The formed channel stoppers (ST) are formed alternately in a direction orthogonal to each other. Further, the first electrode (E1) ... And the third electrode (E2) ... (vertical electrode) of the second layer are alternately formed on the channel stopper (ST),
The grid portion where no electrode is formed is defined as a light receiving area (D) .... The light-receiving area (D) ... are formed on the left side or the right side first electrode (E1) ... or the third electrode (E3) by ... in connexion storage area (C L) (C R) ..., the pattern , Alternating in the horizontal and vertical directions, the first electrode (E
1) and the third electrode (E3) have the same shape. The symbol (OF) in the figure is an overflow drain in the channel stopper (ST).
上述する構成に加えて、フレームトランスフア型のCCD
カラー撮像素子は、通常各受光部（Ｄ）…に対応してモ
ザイク状のカラーフイルタを配し、電極部分を遮光して
いる。尚このカラーフイルタに付いては周知に付き詳し
い説明を割愛する。In addition to the above configuration, a frame transfer type CCD
In the color image pickup element, a mosaic-shaped color filter is usually arranged corresponding to each of the light receiving parts (D) to shield the electrode part from light. The color filter is well known and will not be described in detail.
このフレームトランスフア型のCCDカラー撮像素子は、
インターレスを実現するため、転送に際し予め列方向の
光電変換出力をフイールド毎に組合わせを変えて２出力
づつ混合している。即ち、各列の光電変換出力は、第２
電極（E2）又は第４電極（E4）によつて混合される。混
合出力は、第１〜第４電極（E1）〜（E4）に入力される
転送用の駆動電圧により図中下方に転送される。尚、ク
ロスゲート電極の転送メカニズムに付いても周知に付
き、第１〜第４電極（E1）〜（E4）に印加すべき駆動電
圧波形（ψ１）〜（ψ４）を第５図に図示して詳しい説
明を割愛する。This frame transfer type CCD color image sensor is
In order to realize the interlace, the photoelectric conversion outputs in the column direction are mixed in advance by two for each field by changing the combination for each field. That is, the photoelectric conversion output of each column is the second
It is mixed by the electrode (E2) or the fourth electrode (E4). The mixed output is transferred downward in the drawing by the transfer drive voltage input to the first to fourth electrodes (E1) to (E4). The transfer mechanism of the cross gate electrode is well known, and the driving voltage waveforms (ψ1) to (ψ4) to be applied to the first to fourth electrodes (E1) to (E4) are shown in FIG. Omit detailed explanation.
上述する従来例に於て、撮像期間中垂直方向の第１電極
（E1）…及び第３電極（E3）…にはハイレベル（8V）の
電圧が印加され、水平方向の第２電極（E2）…及び第４
電極（E4）…にはローレベル（0V）の電圧が印加され
る。In the conventional example described above, a high level (8V) voltage is applied to the first electrode (E1) and the third electrode (E3) in the vertical direction during the imaging period, and the second electrode in the horizontal direction (E2) is applied. ) ... and the fourth
A low level (0V) voltage is applied to the electrodes (E4) ....
従って、撮像期間中、チャンネルストッパ（ST）の間を
蛇行する蓄積エリア（CL）（CR）及び第２、第４電極
（E2）（E4）の下の領域、即ち、転送期間に転送経路と
なるチャンネル領域の電位特性は第４図に示す様にな
る。このとき、蓄積エリア（CL）（CR）を分離する第
２、第４電極（E2）（E4）の下の領域のポテンシャルの
状態がフラットになる。そこで、カラーフィルタから漏
洩した光によって第２、第４電極（E2）（E4）の下の領
域に電荷が発生すると、その電荷が両側の蓄積エリア
（CL）（CR）に不規則に分流されてクロストークを生ず
ることが確認された。Therefore, during the imaging period, the storage area which meanders between the channel stopper (ST) (C L) ( C R) and a second, area under the fourth electrode (E2) (E4), i.e., the transfer period Transfer The potential characteristic of the channel region that serves as a path is as shown in FIG. At this time, the potential state in the region below the second and fourth electrodes (E2) (E4) separating the storage areas (C L ) (C R ) becomes flat. Therefore, the second by light leaked from the color filter, the charge in the area below the fourth electrode (E2) (E4) occurs irregularly on the charge on both sides accumulation area (C L) (C R) It was confirmed that they were shunted to cause crosstalk.
（ハ） 発明が解決しようとする問題点 そこで、本発明は、上述する点に鑑み、クロストークを
除去した新規なCCDカラー撮像素子の駆動回路を提案す
るものである。(C) Problems to be Solved by the Invention Therefore, in view of the above-mentioned problems, the present invention proposes a novel drive circuit for a CCD color image pickup device in which crosstalk is removed.
（ニ） 問題点を解決するための手段 本発明では、水平方向に形成したゲート電極を３値駆動
することにより撮像期間中水平方向に形成したゲート電
極に負電圧を印加することを特徴とする。(D) Means for Solving Problems The present invention is characterized in that a negative voltage is applied to the gate electrode formed in the horizontal direction during the imaging period by driving the gate electrode formed in the horizontal direction in three values. .
（ホ） 作 用 本発明によれば、撮像期間中水平方向に形成したゲート
電極下部のチヤンネル電位特性を急峻で対照的な特性と
することにより、光電変換によつて電極下に生ずる電荷
の不規則な移動を阻止するものである。(E) Operation According to the present invention, by making the channel potential characteristic of the lower portion of the gate electrode formed in the horizontal direction during the imaging period a steep and contrasting characteristic, the charge generated under the electrode due to photoelectric conversion can be prevented. It prevents regular movement.
（ヘ） 実施例 以下、本発明を前述するクロスゲート型のCCDカラー撮
像素子に採用した一実施例に付いて説明する。(F) Example Hereinafter, an example in which the present invention is applied to the above-described cross-gate type CCD color image pickup device will be described.
第１図は、本実施例の駆動回路を示す。本実施例によれ
ば発振回路（１）の出力を入力する分周回路（２）は、
等角的に位相を異にする４相分周出力（P1）（P2）（P
3）（P4）を導出する。第１位相と第３位相の分周出力
（P1）（P3）は、第１転送クロック発生回路（３）に入
力され、第２位相と第４位相の分周出力（P2）（P4）
は、第２転送クロツク発生回路（４）に入力される。一
方発振回路（１）の出力を計数入力とする切換制御回路
（５）は、フイールド周期で反転する第１制御信号と、
撮像期間（光電変換期間）中にハイレベルとなる第２制
御信号とを形成している。よつて両転送クロツク発生回
路（３）（４）は、Ａフイールドで第１〜第４位相の分
周出力（P1）（P2）（P3）（P4）をそれぞれ第１〜第４
モード切換回路（６）〜（９）の第１入力端子に入力し
続く、Ｂフイールドでは、第１位相の分周出力（P1）を
第３モード切換回路（８）に、また第３位相の分周出力
（P3）を第１モード切換回路（６）に、更に第２位相の
分周出力（P2）を第４モード切換回路（９）に、また更
に第４位相の分周出力（P4）を第２モード切換回路
（７）にそれぞれ入力する。即ちＡフイールドＢフイー
ルドでは、第１駆動電圧（ψ１）と第３駆動電圧（ψ
３）の位相が切換わり第２駆動電圧（ψ２）と第４駆動
電圧（ψ４）の位相が切換わることになる。この駆動電
圧波形は第２図に示されている。よつて転送時に於ける
駆動電圧の位相はフイールド毎に180゜反転することに
なる。更に、前記第１第３モード切換回路（６）（８）
の第２入力は8Vに規定され、第２第４モード切換回路
（７）（９）の第２入力は−8Vに規定されており、各モ
ード切換回路（６）〜（９）は、撮像期間中第２制御出
力を受けて第２入力を選択する。従つて、第２・第４電
極（E2）（E4）には−8Vの駆動電圧が印加されることに
なり、第４図に図示するチヤンネル電位特性図は点線で
示す様に対照的で而もスロープが急になり電極下のフラ
ツト部分は解消される。尚、上述する実施例は、クロス
ゲート型のCCDカラー撮像素子に本発明を採用するもの
であるが、ゲート電極構造に付いては、クロスゲートに
限らず通常のゲート構造のCCDカラー撮像素子にも採用
できることは言う迄もない。FIG. 1 shows a drive circuit of this embodiment. According to this embodiment, the frequency dividing circuit (2) for inputting the output of the oscillator circuit (1) is
Four-phase division output (P1) (P2) (P
3) Derive (P4). The frequency division outputs (P1) (P3) of the first phase and the third phase are input to the first transfer clock generation circuit (3), and the frequency division outputs (P2) (P4) of the second phase and the fourth phase.
Is input to the second transfer clock generation circuit (4). On the other hand, the switching control circuit (5), which uses the output of the oscillation circuit (1) as a count input, has a first control signal which is inverted at a field cycle,
The second control signal that is at a high level is formed during the imaging period (photoelectric conversion period). Therefore, both transfer clock generation circuits (3) and (4) output the divided outputs (P1) (P2) (P3) (P4) of the first to fourth phases at the A field, respectively.
In the B field, which continues to be input to the first input terminals of the mode switching circuits (6) to (9), the frequency-divided output (P1) of the first phase is fed to the third mode switching circuit (8) and to the third phase. The frequency division output (P3) is fed to the first mode switching circuit (6), the second phase frequency division output (P2) is fed to the fourth mode switching circuit (9), and the fourth phase frequency division output (P4) is further fed. ) Is input to the second mode switching circuit (7). That is, in the A field and the B field, the first drive voltage (ψ1) and the third drive voltage (ψ1)
The phase of 3) is switched, and the phases of the second drive voltage (ψ2) and the fourth drive voltage (ψ4) are switched. This drive voltage waveform is shown in FIG. Therefore, the phase of the driving voltage at the time of transfer is inverted by 180 ° for each field. Further, the first and third mode switching circuits (6) and (8)
Has a second input of 8V and a second input of the second and fourth mode switching circuits (7) and (9) of -8V. The mode switching circuits (6) to (9) are During the period, the second control output is received and the second input is selected. Therefore, a driving voltage of -8V is applied to the second and fourth electrodes (E2) and (E4), and the channel potential characteristic diagram shown in FIG. 4 is symmetrical as indicated by the dotted line. The slope becomes steep and the flat part under the electrode is eliminated. Incidentally, the above-mentioned embodiment adopts the present invention to a cross-gate type CCD color image pickup device, but the gate electrode structure is not limited to the cross gate, but is applicable to a normal gate structure CCD color image pickup device. Needless to say, it can be adopted.
（ト） 効果 よつて、本発明によれば撮像期間中に水平方向の電極に
対し負電圧を印加するだけでクロストークが解消でき、
その効果は大である。(G) Effect According to the present invention, crosstalk can be eliminated by simply applying a negative voltage to the horizontal electrodes during the imaging period.
The effect is great.
第１図は本発明の一実施例の回路ブロツク図、第２図は
同出力波形説明図、第３図はクロスゲート電極パターン
の説明図、第４図はチヤンネル電位特性説明図、第５図
は従来の駆動電圧波形説明図をそれぞれ示す。 （E1）（E3）……第１・第３電極、（E2）（E4）……第
２・第４電極、（Ｄ）……受光エリア、（CL）（CR）…
…蓄積エリア。FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the same output waveform, FIG. 3 is an explanatory diagram of a cross gate electrode pattern, FIG. 4 is an explanatory diagram of channel potential characteristics, and FIG. Shows a conventional drive voltage waveform explanatory diagram, respectively. (E1) (E3) …… First and third electrodes, (E2) (E4) …… Second and fourth electrodes, (D) …… Light receiving area, (C L ) (C R )…
… Storage area.
Claims (1)
平行に形成され、このチャンネルストッパと交差して撮
像期間中に電荷の蓄積エリアを分割する複数の電極が形
成されるフレームトランスファ型のCCDカラー撮像素子
に対し、多相の駆動電圧を供給する駆動回路において、
一定周期のクロックを分周して得た多相の分周出力に応
答して上記基板に対して正電圧となる第１及び第２の電
圧を交互に発生する手段と、上記基板に対して負電圧と
なる第３の電圧を発生する手段と、撮像期間中には上記
第３の電圧を選択し、転送期間中には上記第１及び第２
の電圧を選択して上記電極に供給する手段と、を備えた
ことを特徴とするCCDカラー撮像素子の駆動回路。1. A frame transfer type CCD color in which a plurality of channel stoppers are formed in parallel with each other on a substrate, and a plurality of electrodes are formed so as to intersect the channel stoppers and divide a charge storage area during an imaging period. In the drive circuit that supplies the multi-phase drive voltage to the image sensor,
A means for alternately generating first and second voltages that are positive voltages with respect to the substrate in response to a multiphase divided output obtained by dividing a clock of a constant cycle; Means for generating a third voltage that is a negative voltage, and the third voltage is selected during the imaging period, and the first and second voltages are selected during the transfer period.
And a means for selecting the voltage of and supplying the voltage to the electrodes, a drive circuit for a CCD color image pickup device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59147762A JPH0750917B2 (en) | 1984-07-17 | 1984-07-17 | CCD color image sensor drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59147762A JPH0750917B2 (en) | 1984-07-17 | 1984-07-17 | CCD color image sensor drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6126372A JPS6126372A (en) | 1986-02-05 |
| JPH0750917B2 true JPH0750917B2 (en) | 1995-05-31 |
Family
ID=15437589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59147762A Expired - Lifetime JPH0750917B2 (en) | 1984-07-17 | 1984-07-17 | CCD color image sensor drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750917B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2645927B2 (en) * | 1991-07-29 | 1997-08-25 | 三洋電機株式会社 | Solid-state imaging device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5346681A (en) * | 1976-10-09 | 1978-04-26 | Nippon Mektron Kk | Method of manufacturing laminated bus |
-
1984
- 1984-07-17 JP JP59147762A patent/JPH0750917B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6126372A (en) | 1986-02-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |