JPH0750815B2 - Method for manufacturing semiconductor optical integrated device - Google Patents

Method for manufacturing semiconductor optical integrated device

Info

Publication number
JPH0750815B2
JPH0750815B2 JP2222928A JP22292890A JPH0750815B2 JP H0750815 B2 JPH0750815 B2 JP H0750815B2 JP 2222928 A JP2222928 A JP 2222928A JP 22292890 A JP22292890 A JP 22292890A JP H0750815 B2 JPH0750815 B2 JP H0750815B2
Authority
JP
Japan
Prior art keywords
layer
laser
region
semiconductor
stripe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2222928A
Other languages
Japanese (ja)
Other versions
JPH04105383A (en
Inventor
達也 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2222928A priority Critical patent/JPH0750815B2/en
Priority to EP94118307A priority patent/EP0643461B1/en
Priority to EP91114272A priority patent/EP0472221B1/en
Priority to US07/750,172 priority patent/US5250462A/en
Priority to DE69128097T priority patent/DE69128097T2/en
Priority to DE69115596T priority patent/DE69115596T2/en
Publication of JPH04105383A publication Critical patent/JPH04105383A/en
Publication of JPH0750815B2 publication Critical patent/JPH0750815B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/10Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/16Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface
    • H01S5/164Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface with window regions comprising semiconductor material with a wider bandgap than the active layer

Landscapes

  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、光通信、光情報処理などに用いられる、半導
体レーザーや光導波路などを集積した半導体光集積素子
の製造方法に関する。
TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor optical integrated device, which is used for optical communication, optical information processing, and the like, in which a semiconductor laser, an optical waveguide, and the like are integrated.

[従来の技術] 光通信や光情報処理に用いられる光半導体デバイスに
は、よりいっそうの高性能化高機能化が要求されるよう
になってきている。そのためには、半導体レーザやフォ
トダイオードなどの素子単体の高性能化・高機能化はも
とより、それらの素子を組み合わせて集積化を行ってい
くことが重要である。各種素子を集積化して半導体光集
積素子(PIC;フォトニック・インテグレーテッド・サー
キット)を作製するにあたっては、各素子をいかに半導
体基板上に配置していくか、またいかに設計通りの構造
に作製するかが重要である。
[Prior Art] Optical semiconductor devices used for optical communication and optical information processing are required to have higher performance and higher functionality. For that purpose, it is important not only to improve the performance and functionality of individual devices such as semiconductor lasers and photodiodes, but also to integrate them by combining them. When manufacturing a semiconductor optical integrated device (PIC) by integrating various elements, how to arrange each element on the semiconductor substrate, and how to make the structure as designed Is important.

PICの従来例として、半導体レーザ(LD)2素子と合波
器,光導波路を集積した構造を第6図に示す。第6図
(a)はPICの概略を示す平面図、第6図(b)はPICの
構造を示す斜視図である。活性層3はレーザ領域のみに
存在し、ガイド層10はレーザ領域と導波路領域全体にわ
たって存在する。例として活性層3に波長1.55μm組成
のInGaAsPを用いた場合、ガイド層10には波長1.3μm組
成のInGaAsPを用いている。電流をレーザ領域のみに流
し、2つのレーザ素子間の電気的絶縁をとるために、高
抵抗InP13で埋め込まれた高抵抗埋め込み構造とし、メ
サエッチングを用いている。
As a conventional PIC example, a structure in which two semiconductor laser (LD) elements, a multiplexer, and an optical waveguide are integrated is shown in FIG. FIG. 6 (a) is a plan view showing the outline of the PIC, and FIG. 6 (b) is a perspective view showing the structure of the PIC. The active layer 3 exists only in the laser region, and the guide layer 10 exists in the entire laser region and the waveguide region. As an example, when InGaAsP with a wavelength of 1.55 μm is used for the active layer 3, InGaAsP with a wavelength of 1.3 μm is used for the guide layer 10. In order to flow an electric current only in the laser region and electrically insulate between the two laser elements, a high resistance embedded structure filled with high resistance InP13 is used and mesa etching is used.

このPICの作製工程を述べる。結晶成長には有機金属気
相成長法(MOVPE)を用いるのが一般的である。まず、
n−InP基板1の上に、n−InGaAsPガイド層10、InGaAs
P活性層3、p−InPクラッド層4を成長した後、SiO2
を選択マスクとして導波路領域のp−InPクラッド層
4、InGaAsP活性層3を除去し、InGaAsPガイド層および
p−InPクラッド層(図中には示されていない)を埋め
込み成長する。次に、SiO2膜をマスクとしてメサエッチ
ングし、Feドープ高抵抗InP層13を埋め込み成長する。S
iO2膜を除去した後、さらに、前面にp−InPクラッド層
5およびP+−InGaAsキャップ層7を成長する。レーザ領
域と導波路領域の間、および二つのレーザ素子の間に絶
縁用の溝をエッチングにより形成してから、全面にSiO2
膜21を堆積し、レーザ部の上部を窓開けしてp側のパッ
ド電極32を、また基板側にn側電極33を形成して完成す
る。この例では、二つのレーザ素子の発振波長の制御は
できないが、分布帰還型(DFB)溝にすれば、グレーテ
ィングのピッチを変えたり、多電極構造にするなどして
多波長光源とすることができる。
The manufacturing process of this PIC will be described. The metal organic vapor phase epitaxy (MOVPE) is generally used for crystal growth. First,
On the n-InP substrate 1, n-InGaAsP guide layer 10, InGaAs
After growing the P active layer 3 and the p-InP clad layer 4, the p-InP clad layer 4 and the InGaAsP active layer 3 in the waveguide region are removed by using the SiO 2 film as a selective mask, and the InGaAsP guide layer and the p-InP clad layer are removed. A layer (not shown in the figure) is grown by burying. Next, the SiO 2 film is used as a mask for mesa etching to bury and grow the Fe-doped high-resistance InP layer 13. S
After removing the iO 2 film, a p-InP clad layer 5 and a P + -InGaAs cap layer 7 are further grown on the front surface. After forming an insulating groove by etching between the laser region and the waveguide region, and between the two laser elements, SiO 2 is formed on the entire surface.
A film 21 is deposited, a window is opened in the upper part of the laser portion, a p-side pad electrode 32 is formed, and an n-side electrode 33 is formed on the substrate side to complete the process. In this example, the oscillation wavelengths of the two laser elements cannot be controlled, but if a distributed feedback (DFB) groove is used, the pitch of the grating can be changed, or a multi-electrode structure can be used to form a multi-wavelength light source. it can.

[発明が解決しようとする課題] このような、PICの作製には、導波路を形成する層構造
を精密に制御することが重要である。層厚はMOVPEなど
の気相成長法を用いれば充分に制御が可能であるが、導
波路幅は従来、SiO2などをマスクとして用いたメサエッ
チングにより制御しており、サイドエッチングなどによ
り充分な制御性が得られないなどの問題があった。
[Problems to be Solved by the Invention] In manufacturing such a PIC, it is important to precisely control the layer structure forming the waveguide. The layer thickness can be sufficiently controlled by using a vapor deposition method such as MOVPE, but the waveguide width is conventionally controlled by mesa etching using SiO 2 as a mask, and is sufficiently controlled by side etching. There were problems such as lack of controllability.

またレーザ領域の活性層と導波路領域のガイド層を形成
するために、活性層を全面に成長してから、導波路領域
の活性層を選択エッチングして除去し、ガイド層を埋め
込み成長していた。活性層とガイド層は光学的に結合
し、接合部分での散乱が少ない構造にする必要があり、
埋め込み成長によりそのような構造を作製するのは困難
であった。
In order to form the active layer in the laser region and the guide layer in the waveguide region, the active layer is grown over the entire surface, the active layer in the waveguide region is selectively etched and removed, and the guide layer is embedded and grown. It was The active layer and the guide layer must be optically coupled and have a structure that causes less scattering at the joint,
It was difficult to fabricate such a structure by buried growth.

[課題を解決するための手段] 上記の課題を解決するための光半導体集積素子の製造方
法は、半導体光集積素子の製造方法において、ストライ
プ方向で幅を変化させた2本の平行なストライプ状誘電
体薄膜を、結晶成長領域は一定の幅のストライプ状開口
部となるように半導体表面に形成する工程と、前記誘電
体薄膜をマスクとして、MOVPE成長により前記結晶成長
領域に量子井戸構造を含む半導体層を選択的に結晶成長
する工程とを有し、前記誘電体薄膜の幅の変化により、
前記結晶成長領域での半導体層の結晶成長速度を制御す
ることを特徴とする。
[Means for Solving the Problems] A method for manufacturing an optical semiconductor integrated device for solving the above-mentioned problems is a method of manufacturing a semiconductor optical integrated device, which comprises two parallel stripes whose widths are changed in the stripe direction. A step of forming a dielectric thin film on the semiconductor surface so that the crystal growth region becomes a stripe-shaped opening having a constant width; and using the dielectric thin film as a mask, a quantum well structure is included in the crystal growth region by MOVPE growth. And a step of selectively crystallizing the semiconductor layer, by changing the width of the dielectric thin film,
The crystal growth rate of the semiconductor layer in the crystal growth region is controlled.

[作用] 本発明の根本をなす平坦基板上の選択成長の様子を第1
図に示す。第1図(a)に示すように、(100)方位半
導体基板1上に選択成長用薄膜21を形成し、〈011〉お
よび〈01〉方向のストライプ状に薄膜21を選択的に
除去し、MOVPEによってDH構造を成長すると、第1図
(b)に示したように成長層の側面は〈01〉ストラ
イプに沿っては(111)A面が、また〈011〉方向に沿っ
ては(111)B面が形成される。また各成長層の表面は
(100)面を形成しており、界面も非常にフラットであ
る。混晶の組成も、薄膜のストライプ幅が極端に広くな
ければ面内で均一であり、光半導体素子やPICの活性層
や導波路層に充分適用できる。また側面は(111)面と
なるため、薄膜21のパターニングが精密であれば、成長
層幅の制御性も非常によくなるという特徴がある。
[Operation] First, the state of selective growth on a flat substrate, which is the basis of the present invention, will be described.
Shown in the figure. As shown in FIG. 1 (a), a selective growth thin film 21 is formed on a (100) oriented semiconductor substrate 1, and the thin film 21 is selectively removed in stripes in the <011> and <01> directions. When the DH structure is grown by MOVPE, as shown in FIG. 1B, the side surface of the growth layer is the (111) A plane along the <01> stripe and the (111) A plane along the <011> direction. ) Side B is formed. The surface of each growth layer forms a (100) plane, and the interface is very flat. The composition of the mixed crystal is uniform in-plane unless the stripe width of the thin film is extremely wide, and can be sufficiently applied to the active layer and the waveguide layer of the optical semiconductor element and PIC. Further, since the side surface is the (111) plane, if the patterning of the thin film 21 is precise, the controllability of the growth layer width is also very good.

また、この選択成長では、薄膜のストライプ幅を変える
ことによって、成長層厚を変化させることができる。。
第4図にストライプ幅と成長速度の関係を測定した結果
の一例を示す。ストライプ幅が広いほど成長速度は高く
なる。これは、薄膜上からマイグレーションして半導体
表面に到達する成長種の量が増加するためである。この
ことから、選択成長層の層厚を制御することが可能にな
る。量子井戸構造を選択成長して、ウェル層厚を変えれ
ば、量子井戸構造の等価屈折率や発光エネルギーを局所
的に変えることが可能になり、PIC作製の自由度が増
す。
Further, in this selective growth, the growth layer thickness can be changed by changing the stripe width of the thin film. .
FIG. 4 shows an example of the result of measuring the relationship between the stripe width and the growth rate. The wider the stripe width, the higher the growth rate. This is because the amount of growth species that migrate from the thin film and reach the semiconductor surface increases. From this, it becomes possible to control the layer thickness of the selective growth layer. By selectively growing the quantum well structure and changing the well layer thickness, it becomes possible to locally change the equivalent refractive index and the emission energy of the quantum well structure, which increases the degree of freedom in PIC fabrication.

[実施例] 第1の実施例として、多重量子井戸(MQW)構造の活性
層を有する分布帰還型(DFB)半導体レーザと電界吸収
型半導体光変調器をモノリシックに集積したPICへ応用
した結果について述べる。このPICは半導体レーザから
の発生した光を変調器で発振変調し、変調器側面から出
射するもので、従来の半導体レーザを直接変調した場合
と比べて、高速変調時のスペクトル広がり(チャーピン
グ)が狭いという特長があり、次世代光通信用デバイス
として研究開発が行われている。
[Embodiment] As a first embodiment, a result of application to a PIC in which a distributed feedback (DFB) semiconductor laser having an active layer having a multiple quantum well (MQW) structure and an electroabsorption semiconductor optical modulator are monolithically integrated will be described. Describe. This PIC oscillates and modulates the light generated from a semiconductor laser with a modulator and emits it from the side of the modulator. Compared to the case where a conventional semiconductor laser is directly modulated, the spectrum spread (chirping) during high-speed modulation It is characterized by being narrow, and is being researched and developed as a device for next-generation optical communication.

従来のレーザ領域の活性層(波長1.55μm組成)を全面
に成長してから、変調器領域の活性層を選択エッチング
して除去し、吸収層(波長約1.4μm組成)を選択成長
していた。活性層と吸収層は光学的に結合し、接合部で
の散乱が少ない構造にする必要があり、選択成長により
そのような構造を作製するのは困難であった。
Conventionally, an active layer in the laser region (wavelength 1.55 μm composition) was grown over the entire surface, then the active layer in the modulator region was selectively etched and removed, and an absorption layer (wavelength about 1.4 μm composition) was selectively grown. . The active layer and the absorption layer have to be optically coupled to each other and have a structure that causes less scattering at the junction, and it has been difficult to produce such a structure by selective growth.

一方、本発明を用いれば、SiO2膜の幅を変えることによ
り、選択成長したMQW構造の層厚を変えることができる
ので、活性層、吸収層を同時に成長することが可能とな
り、成長回数が減るばかりか、結合効率の高い接合を得
ることができる。第5図はMQWのウェル層をInGaAs、バ
リア層をInGaAsPとした時の、ウェル層厚とMQWの発光波
長の関係を計算した結果である。バリアのInGaAsPを波
長1.3μm組成と1.15μm組成にした場合について示し
てある。この図により、バリアを1.15μm組成にした場
合、ウェル厚約80Åで波長1.55μm、約30Åで1.4μm
となることがわかる。この計算結果と第4図のSiO2スト
ライプ幅と成長速度の関係より、レーザ領域はストライ
プ幅20μm、変調器領域はストライプ幅2μmとした。
On the other hand, according to the present invention, by changing the width of the SiO 2 film, it is possible to change the layer thickness of the selectively grown MQW structure, which makes it possible to grow the active layer and the absorption layer at the same time. Not only can the number be reduced, but a bond with high coupling efficiency can be obtained. FIG. 5 shows the calculation results of the relationship between the well layer thickness and the MQW emission wavelength when the MQW well layer is InGaAs and the barrier layer is InGaAsP. The figure shows the case where InGaAsP of the barrier has a wavelength of 1.3 μm composition and a wavelength of 1.15 μm composition. Based on this figure, when the barrier composition is 1.15 μm, the wavelength is 1.55 μm when the well thickness is about 80 Å and 1.4 μm when the well thickness is about 30 Å.
It turns out that From this calculation result and the relationship between the SiO 2 stripe width and the growth rate in FIG. 4, the laser region has a stripe width of 20 μm, and the modulator region has a stripe width of 2 μm.

第2図(a)はMQW構造を選択成長した状態を示してい
る。グレーティングはn−InP基板1のレーザ領域のみ
に形成し、その上にn−InGaAsPガイド層10(波長1.3μ
m組成、キャリア濃度1×1018cm-3、層厚1000Å)、MQ
W活性層兼吸収層11、p−InPクラッド層4(キャリア濃
度5×1017cm-3、層厚500Å)を選択成長した。MQWはウ
ェル数4で層厚はレーザ領域がInGaAsウェル厚78Å、1.
15μm組成InGaAsPバリア厚150Åであり、変調器領域が
ウェル厚34Å、バリア厚66Åであった。また活性層幅は
2.0μmであった。変調器側端面の反射率を抑制するた
めに端面に未成長領域を設けたウインドウ構造とした。
FIG. 2 (a) shows a state in which the MQW structure is selectively grown. The grating is formed only in the laser region of the n-InP substrate 1, and the n-InGaAsP guide layer 10 (wavelength 1.3 μm is formed thereon).
m composition, carrier concentration 1 × 10 18 cm -3 , layer thickness 1000Å), MQ
The W active / absorbing layer 11 and the p-InP clad layer 4 (carrier concentration 5 × 10 17 cm −3 , layer thickness 500 Å) were selectively grown. In MQW, the number of wells is 4 and the layer thickness is InGaAs well thickness 78 Å, 1.
The 15 μm composition InGaAsP barrier thickness was 150Å, the modulator region had a well thickness of 34Å, and a barrier thickness of 66Å. The active layer width is
It was 2.0 μm. In order to suppress the reflectance of the modulator-side end face, a window structure is provided with an ungrown region on the end face.

続いて全面にp−InP層5(キャリア濃度5×1017c
m-3、層厚0.5μm)を成長し、さらにSiO2膜をレーザ共
振器方向には幅10μm、間隔30μmのダブルストライプ
状に、またレーザと変調器の境界には幅10μmノシング
ルストライプ状にパターニングして、p−InP層(キャ
リア濃度1×1018cm-3、層厚1.0μm)およびP+−InGaA
sキャップ層7(層厚0.3μm、キャリア濃度1×1019cm
-3)を選択成長して活性層・吸収層への電流・電界の狭
窄、およびレーザ領域と変調器領域の電気的絶縁を図っ
た。最後に再びSiO2膜21を形成して活性層、吸収層の上
部に窓開けして、p側電極32をパッド状に形成し、基板
1側にもn側電極33を形成した。完成図が第2図(b)
である。へき開したレーザ領域長は400μm、変調器領
域長は200μmとした。また、レーザ側端面には反射率8
0%の高反射コーティングを施した。
Then, p-InP layer 5 (carrier concentration 5 × 10 17 c
m -3 , layer thickness 0.5 μm), and a SiO 2 film with a width of 10 μm in the laser cavity direction and a spacing of 30 μm in a double stripe shape, and a boundary between the laser and the modulator is a single stripe shape with a width of 10 μm. To a p-InP layer (carrier concentration 1 × 10 18 cm −3 , layer thickness 1.0 μm) and P + -InGaA.
s Cap layer 7 (layer thickness 0.3 μm, carrier concentration 1 × 10 19 cm
-3 ) was selectively grown to confine the current and electric field to the active layer and absorption layer, and to electrically insulate the laser region and the modulator region. Finally, the SiO 2 film 21 was formed again, a window was opened above the active layer and the absorption layer, the p-side electrode 32 was formed in a pad shape, and the n-side electrode 33 was also formed on the substrate 1 side. Completion drawing is Figure 2 (b)
Is. The cleaved laser region length was 400 μm, and the modulator region length was 200 μm. In addition, the laser side end face has a reflectance of 8
A 0% highly reflective coating was applied.

典型的な素子の発振しきい値電流は18mAで、最大CW光出
力は25mWであった。発振波長は1.545μmであり、変調
領域に−5V印加したときの消光比は25dBであった。ま
た、消光特性から見積もった結合効率は95%と高い値が
得られた。このように、本発明の選択成長により活性層
と吸収層を同時に成長する技術により、良好な結合導波
路構造が容易に作製できるこが確認された。
The oscillation threshold current of a typical device was 18 mA, and the maximum CW optical output was 25 mW. The oscillation wavelength was 1.545 μm, and the extinction ratio when applying −5 V to the modulation region was 25 dB. In addition, the binding efficiency estimated from the quenching property was as high as 95%. As described above, it was confirmed that a good coupled waveguide structure can be easily manufactured by the technique of simultaneously growing an active layer and an absorption layer by the selective growth of the present invention.

次に、第2の実施例として、第6図に示した2波長半導
体レーザアレイと光導波路を集積したPICを本発明の選
択成長を用いて作製した結果について第3図を参照しな
がら述べる。第3図(a)は、はじめにDH構造を選択成
長した際のSiO2膜21のパターンである。各領域ともSiO2
ストライプに囲まれた成長領域の幅は2μmであり、Si
O2ストライプ幅は一方のレーザ領域で15μm、もう一方
のレーザ領域と導波路領域は5μmとした。第3図
(c),(d)は完成した素子の断面図である(切断方
向は第3図(a)に示してある)。まずn−InP基板1
の上に、n−InGaAsPガイド層10(波長1.3μm組成、キ
ャリア濃度1×1018cm-3、層厚約1000Å)、n−InPエ
ッチングストップ層12(キャリア濃度1×1018cm-3、層
厚約400Å)、MQW活性層11、p−InPクラッド層4(キ
ャリア濃度5×1017cm-3、層厚約500Å)を成長した。M
QWはウェル数4で、層厚は一方のレーザ領域がInGaAsウ
ェル層70Å、InGaAsP(波長1.3μm組成)バリア厚150
Åであり、もう一方のレーザ領域がウェル厚50Å、バリ
ア厚110Åであった。次に第3図(b)に示すようにSiO
2膜をパターニングし、レーザ領域以外のp−InPクラッ
ド層4およびMQW活性層11、n−InPエッチングストップ
層12を選択エッチングし、ノンドープInGaAsP導波路層1
4(波長1.3μm組成、層厚1500Å)を埋め込み成長し
た。次に、第3図(c),(d)に示すように、p−In
P層5(キャリア濃度1×1017cm-3、層厚0.5μm)、p
−InP層(キャリア濃度1×1018cm-3、層厚10μm)、
およびP+−InGaAsキャップ層7(層厚0.3μm、キャリ
ア濃度1×1019cm-3)を選択成長した後、SiO2膜21の窓
開けしたレーザ活性層の上面にp側パッド電極32を、基
板側にn側電極33を形成した。レーザ共振器長300μ
m、レーザ間隔は50μm、導波路長は250μmとし、出
射端面はウィンドウ構造とした。
Next, as a second embodiment, the result of producing the PIC in which the two-wavelength semiconductor laser array and the optical waveguide shown in FIG. 6 are integrated by using the selective growth of the present invention will be described with reference to FIG. FIG. 3A shows a pattern of the SiO 2 film 21 when the DH structure is first selectively grown. SiO 2 in each area
The width of the growth area surrounded by stripes is 2 μm,
The O 2 stripe width was 15 μm in one laser region, and 5 μm in the other laser region and the waveguide region. 3 (c) and 3 (d) are sectional views of the completed device (the cutting direction is shown in FIG. 3 (a)). First, n-InP substrate 1
N-InGaAsP guide layer 10 (wavelength 1.3 μm composition, carrier concentration 1 × 10 18 cm -3 , layer thickness about 1000Å), n-InP etching stop layer 12 (carrier concentration 1 × 10 18 cm -3 , The MQW active layer 11 and the p-InP clad layer 4 (carrier concentration 5 × 10 17 cm −3 , layer thickness about 500Å) were grown. M
QW has 4 wells, and the layer thickness is InGaAs well layer 70Å in one laser region, InGaAsP (wavelength 1.3 μm composition) barrier thickness 150
The other laser region had a well thickness of 50 Å and a barrier thickness of 110 Å. Next, as shown in FIG. 3 (b), SiO
2 The film is patterned, and the p-InP clad layer 4 other than the laser region, the MQW active layer 11 and the n-InP etching stop layer 12 are selectively etched to obtain the non-doped InGaAsP waveguide layer 1
4 (wavelength 1.3 μm composition, layer thickness 1500Å) was embedded and grown. Next, as shown in FIGS. 3C and 3D, p-In
P layer 5 (carrier concentration 1 × 10 17 cm -3 , layer thickness 0.5 μm), p
-InP layer (carrier concentration 1 × 10 18 cm -3 , layer thickness 10 μm),
And the P + -InGaAs cap layer 7 (layer thickness 0.3 μm, carrier concentration 1 × 10 19 cm −3 ) were selectively grown, and then the p-side pad electrode 32 was formed on the upper surface of the laser active layer in which the SiO 2 film 21 was opened. The n-side electrode 33 was formed on the substrate side. Laser cavity length 300μ
m, the laser interval was 50 μm, the waveguide length was 250 μm, and the emission end face had a window structure.

このツインレーザの典型的な発振しきい値電流は15mA
で、発振波長は1.552μmと1.528μmであった。導波路
端面からの最大光出力は20mAであった。このように、ス
トライプ幅を変えることにMQWレーザの発振波長を変え
ることができ、こうした技術はさまざまな集積光デバイ
スへの応用が可能ある。
The typical oscillation threshold current of this twin laser is 15mA
The oscillation wavelengths were 1.552 μm and 1.528 μm. The maximum optical output from the end face of the waveguide was 20 mA. Thus, the oscillation wavelength of the MQW laser can be changed by changing the stripe width, and such a technique can be applied to various integrated optical devices.

なお実施例では導波路領域のMQW活性層11をエッチング
した後導波路層14を埋め込み成長する工程を用いたが、
SiO2ストライプの幅などの成長条件を変えることによっ
て、第1の実施例のように選択成長で一括形成すること
は可能である。
In the example, the step of etching the MQW active layer 11 in the waveguide region and then burying and growing the waveguide layer 14 was used.
By changing the growth conditions such as the width of the SiO 2 stripe, it is possible to collectively form by selective growth as in the first embodiment.

なお、上記各実施例においては、選択成長用マスクとな
る誘電体膜にSiO2膜を用いたが、Si3N4膜等他の誘電体
膜でもよい。
Although the SiO 2 film is used as the dielectric film serving as the selective growth mask in each of the above-described embodiments, other dielectric films such as Si 3 N 4 film may be used.

[発明の効果] 以上述べたように、本発明の作製方法を用いれば、メサ
エッチングが不要となり、均一な活性層、導波路幅が制
御よく作製できる。それだけでなく、マスク幅を変える
ことにより成長層厚を変えることができ、MQW構造の発
光波長や実効屈折率を変えることが可能である。これら
の技術を用いることにより、従来複雑なプロセスを必要
としていた各種半導体光集積素素子(PIC)を比較的容
易に、また制御性よく作製することが可能となった。
[Effects of the Invention] As described above, when the manufacturing method of the present invention is used, mesa etching is not required, and uniform active layers and waveguide widths can be manufactured with good control. Not only that, the growth layer thickness can be changed by changing the mask width, and the emission wavelength and effective refractive index of the MQW structure can be changed. By using these technologies, it has become possible to fabricate various semiconductor optical integrated devices (PICs), which conventionally required complicated processes, with relative ease and controllability.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の概念を表す構造図である。第2図は本
発明を用いて作製したDFB半導体レーザと半導体光変調
器とを集積したPICの作製方法と素子構造を表す図であ
る。第3図は本発明を用いて作製した2波長半導体レー
ザと光導波路との集積素子の作製方法と素子構造を表す
図である。第4図はストライプ幅と成長速度の関係を表
す図である。第5図はMQW構造のウェル厚と発光波長の
関係を表す図である。第6図は第3図と同じ2波長半導
体レーザと光導波路の集積素子の従来の作製方法による
構造を表す図である。 図中、1……n−InP基板、3……InGaAsP活性層、4…
…p−InPクラッド層、5……p−InPクラッド層、6…
…p−InP層、7……P+−InGaAsキャップ層、10……n
−InGaAsガイド層、11……MQW活性層、12……n−InPエ
ッチングストップ層、13……高抵抗InP埋め込み層、14
……InGaAsP導波路層、21……SiO2膜、32……p側電
極、33……n側電極、である。
FIG. 1 is a structural diagram showing the concept of the present invention. FIG. 2 is a diagram showing a manufacturing method and a device structure of a PIC in which a DFB semiconductor laser manufactured by using the present invention and a semiconductor optical modulator are integrated. FIG. 3 is a diagram showing a manufacturing method and a device structure of an integrated device of a two-wavelength semiconductor laser and an optical waveguide manufactured by using the present invention. FIG. 4 is a diagram showing the relationship between the stripe width and the growth rate. FIG. 5 is a diagram showing the relation between the well thickness of the MQW structure and the emission wavelength. FIG. 6 is a view showing the structure of the same two-wavelength semiconductor laser and optical waveguide integrated device as in FIG. 3 according to a conventional manufacturing method. In the figure, 1 ... n-InP substrate, 3 ... InGaAsP active layer, 4 ...
... p-InP clad layer, 5 ... p-InP clad layer, 6 ...
... p-InP layer, 7 ... P + -InGaAs cap layer, 10 ... n
-InGaAs guide layer, 11 ... MQW active layer, 12 ... n-InP etching stop layer, 13 ... High resistance InP buried layer, 14
... InGaAsP waveguide layer, 21 ... SiO 2 film, 32 ... p-side electrode, 33 ... n-side electrode.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体光集積素子の製造方法において、ス
トライプ方向で幅を変化させた2本の平行なストライプ
状誘電体薄膜を、結晶成長領域は一定の幅のストライプ
状開口部となるように半導体表面に形成する工程と、前
記誘電体薄膜をマスクとして、MOVPE成長により前記結
晶成長領域に量子井戸構造を含む半導体層を選択的に結
晶成長する工程とを有し、前記誘電体薄膜の幅の変化に
より、前記結晶成長領域での半導体層の結晶成長速度を
制御することを特徴とする半導体光集積素子の製造方
法。
1. A method for manufacturing a semiconductor optical integrated device, wherein two parallel stripe-shaped dielectric thin films whose widths are changed in a stripe direction are formed so that a crystal growth region becomes a stripe-shaped opening having a constant width. A step of forming a semiconductor surface, and a step of selectively crystallizing a semiconductor layer including a quantum well structure in the crystal growth region by MOVPE growth using the dielectric thin film as a mask, the width of the dielectric thin film Is controlled to control the crystal growth rate of the semiconductor layer in the crystal growth region.
JP2222928A 1990-08-24 1990-08-24 Method for manufacturing semiconductor optical integrated device Expired - Lifetime JPH0750815B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2222928A JPH0750815B2 (en) 1990-08-24 1990-08-24 Method for manufacturing semiconductor optical integrated device
EP94118307A EP0643461B1 (en) 1990-08-24 1991-08-26 Method for fabricating an optical semiconductor device
EP91114272A EP0472221B1 (en) 1990-08-24 1991-08-26 Method for fabricating an optical semiconductor device
US07/750,172 US5250462A (en) 1990-08-24 1991-08-26 Method for fabricating an optical semiconductor device
DE69128097T DE69128097T2 (en) 1990-08-24 1991-08-26 Method of manufacturing an optical semiconductor device
DE69115596T DE69115596T2 (en) 1990-08-24 1991-08-26 Method of manufacturing an optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2222928A JPH0750815B2 (en) 1990-08-24 1990-08-24 Method for manufacturing semiconductor optical integrated device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP8170997A Division JP2842387B2 (en) 1996-07-01 1996-07-01 Manufacturing method of semiconductor optical integrated device

Publications (2)

Publication Number Publication Date
JPH04105383A JPH04105383A (en) 1992-04-07
JPH0750815B2 true JPH0750815B2 (en) 1995-05-31

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Country Link
JP (1) JPH0750815B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2943510B2 (en) * 1991-08-09 1999-08-30 日本電気株式会社 Tunable semiconductor laser device
JPH07114307B2 (en) * 1991-09-04 1995-12-06 工業技術院長 Method of manufacturing optical functional element
US5565693A (en) * 1993-01-07 1996-10-15 Nec Corporation Semiconductor optical integrated circuits
JPH07118569B2 (en) * 1993-01-20 1995-12-18 日本電気株式会社 Method for manufacturing optical semiconductor element
JP2555955B2 (en) * 1993-11-11 1996-11-20 日本電気株式会社 Semiconductor optical amplifier and manufacturing method thereof
JP3007928B2 (en) * 1995-02-22 2000-02-14 日本電気株式会社 Method for manufacturing optical semiconductor device
JP2870632B2 (en) * 1995-07-13 1999-03-17 日本電気株式会社 Semiconductor optical integrated circuit and method of manufacturing the same
JP2914235B2 (en) * 1995-07-28 1999-06-28 日本電気株式会社 Semiconductor optical device and method of manufacturing the same
JP2914249B2 (en) * 1995-09-23 1999-06-28 日本電気株式会社 Optical semiconductor device and method of manufacturing the same
JP2842387B2 (en) * 1996-07-01 1999-01-06 日本電気株式会社 Manufacturing method of semiconductor optical integrated device
JP5047665B2 (en) * 2007-03-29 2012-10-10 アンリツ株式会社 Semiconductor light emitting device and manufacturing method thereof

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JPS50159971A (en) * 1974-06-13 1975-12-24
JPS6187385A (en) * 1984-10-05 1986-05-02 Nec Corp Buried-structure semiconductor laser
JPH069280B2 (en) * 1988-06-21 1994-02-02 松下電器産業株式会社 Semiconductor laser device

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