JPH0749918A - Signal processor - Google Patents

Abstract

PURPOSE:To constitute the signal processor so that it has a large dynamic range, and a signal processing of a high SN ratio can be executed by containing a connecting means for connecting rhe coupling capacity and a signal holding means, and a first amplifying means provided through a first switch means in both ends of the connecting means. CONSTITUTION:This signal processor is constituted of a capacity means 1 which becomes the coupling capacity for extracting an AC signal component of an input signal from an input terminal VIN, a reset means 3, a sampling means 6 which becomes a connecting means, a holding means 2 which becomes a signal holding means containing a capacitor and buffer means 5, 7 being adding means, and a switching means 4. The input characteristic of the buffer means also has the characteristic of an inclination 1 for passing through an origin. In this case, since only the signal component can be added substantially in order to cancel a noise component, etc., a dynamic range is enlarged, and also, an addition processing being excellent in an SN ratio can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for processing a plurality of individual signals used in information storage devices, photoelectric conversion devices and the like.

[0002]

2. Description of the Related Art In a semiconductor memory device or an image sensor represented by a read only memory (ROM),
A configuration is adopted in which an output signal from a signal source such as a memory cell or a photocell is sequentially output to the outside in a time series by an XY address system by vertical scanning and horizontal scanning using a shift register.

As described in Japanese Patent Application Laid-Open No. 63-86679, which is one of the conventional examples, signal processing for adding a plurality of signals has come to be performed in a photoelectric conversion device or the like.

[0004]

However, in the stage of processing a signal, further improvement is required in terms of expanding the dynamic range and improving the SN ratio.

[0005]

The present invention solves the above technical problems and has a large dynamic range and high S
An object of the present invention is to provide a signal processing device that can perform signal processing of N ratio.

According to an embodiment of the present invention, the above-mentioned object has a signal holding means for holding an input signal from a signal source, and a coupling capacitance provided on the signal source side. And a signal holding means for connecting the signal holding means and a first amplifier means provided at both ends of the connecting means via first switch means.

[0007]

According to the embodiment of the present invention, since only the signal components can be substantially added to cancel the noise components and the like, the dynamic range is expanded and the addition processing excellent in the SN ratio is performed. be able to.

[0008]

【Example】

(Embodiment 1) FIG. 1 shows a first embodiment of the present invention. In this embodiment, a capacitance means 1 serving as a coupling capacitance for taking out an AC signal component of an input signal from the input terminal V _IN , a reset means 3, a sampling means 6 serving as a connecting means, a holding means 2 serving as a signal holding means, And buffer means 5 and 7 as addition means and switching means 4. The input / output characteristic of the buffer means 5 has a characteristic of inclination 1 passing through the origin as shown in FIG.

Next, using the timing chart of FIG.
The operation of this embodiment will be briefly described.

First, at time T ₁ , when the pulses of φ _RS and φ _SH become High level, the MOS transistor is turned off.
The N state is set, and the node 8 and the hold capacitor 2 are initialized by the voltage applied to the terminal V _CL . At time T ₂ , φ _RS becomes Low level, and MOS transistor 3
Is turned off, and the node 8 and the hold capacitor 2 are in a floating state.

Next, at time t ₃ , when the input signal 1 rises, the potential of the hold capacitor 2 in the floating state is raised via the capacitor 1. The voltage rise width at this time is

[0012]

[Outer 1] C ₁ ... Capacitance value of capacitance means 1 C ₂ ... Hold capacitance value VS ₁ ... Represented by voltage value of signal 1.

Next, at time t ₄ , when φ _SH falls, hold capacitor 2 is disconnected from node 8, and thereafter, even if the input signal falls at time T ₅ , it is not affected by the fall of the input signal. . On the other hand, the potential of the node 8 drops as the input voltage falls.

Next, at time T ₆ , when the pulse of φ _SW goes to the high level, the output of the buffer 5 goes to the node 8
, And the node 9 and the node 8 have the same potential. At time T ₆ , when the φ _SW pulse becomes Low level, the switching MOS transistor 4 is turned off,
The node 8 is disconnected from the buffer 5, then at time T ₇ , the pulse of φ _SH goes to High level, the sampling MOS transistor 6 is turned on, and at time T ₉ , the next input signal 2 is input to the input terminal. When given, the voltage of the hold capacitor 2 rises,

[0015]

[Outside 2] V _S2 ... It becomes the voltage value of the signal 2, and the analog addition of the input signal can be realized. By repeating the above operation

[0016]

[Outside 3] Can be added. As shown in the equation (1.3), it is clear that C ₁ >> C ₂ should be set in order to increase the addition gain.

(Embodiment 2) In the first embodiment, the input signal is (reference voltage)-(input signal 1)-(reference voltage)-
(Input signal 2) is given in time series, but for example, the output signal from the photoelectric conversion element is the reference voltage − (dark signal output signal (N1) of first pixel) −reference voltage− (first pixel When the input signal is given in time series of (bright output signal (S1))-reference voltage- (dark output signal (N2) of second pixel) -... {(S1 signal)-(N1 signal)} Calculation of + {(S2 signal)-(N2 signal)} + can also be performed. Therefore, it becomes possible to add the noise-free optical signal components in each pixel.

A brief description will be given with reference to the timing chart of FIG.

At time T ₁ , the N1 signal is applied to the input terminal, and then, at time T ₂ , the pulses of φ _RS and φ _{SH go to} the high level, the MOS transistors 3 and 6 are turned on, and the hold capacitance is changed. Initialized to V _CL .

Next, at time T ₃ , the pulse of φ _RS becomes Low level and the MOS transistor 3 is turned off, the hold capacitor 2 becomes in a floating state, and then at time T ₄ , the input signal is at the reference level. When you fall to
In the hold capacity 2,

[0021]

[Outside 4] The voltage of is obtained.

Further, at time T ₅ , S is applied to the input terminal.
When 1 signal is given, the hold capacitor 2

[0023]

[Outside 5] The voltage of is obtained.

Next, before the S1 signal falls, at time T ₆ , a low-level pulse is applied to φ _SH to turn on the MOS.
By turning off the transistor 6, the potential of the hold capacitor 2 is not affected by the fall of the S1 signal at time T ₇ .

Next, at time T ₈ , after the next N ₂ signal is input, at time T ₉ , a high-level pulse is applied to φ _SW to turn on the MOS transistor 4, and the node 8 is turned on. The buffer 5 makes the same potential as the hold capacitor 2.

Next, a low level pulse is applied to φ _SW to turn off the MOS transistor 4, and at time T ₁₀ , a high level pulse is applied to φ _SH ,
The MOS transistor 6 is turned on.

At this point, the node 8 and the node 9 (2.
Becomes a voltage given by 2), then, N2 signal falls at time T _11, S2 when the signal rises at time T _12, the hold capacitor 2,

[0028]

[Outside 6] Becomes a voltage given by, and at time T ₁₃ , φ _SH becomes L
When the ow level pulse is applied, the MOS transistor 6
When is turned off, the potential of the hold capacitor 2 is held.

By repeating this operation,

[0030]

[Outside 7] The voltage of can be obtained.

In the present embodiment, for example, when the offset voltage of the input signal is large and the input signals are added as they are, the circuit is saturated by addition at most several times, and when the offset voltage is input to the N signal, it is effective. The dynamic range can be increased. Further, when the output signal of the photoelectric conversion device is used as the input signal of this circuit, by adding the output voltage in the dark as the N signal, the addition operation of only the optical signal component becomes possible, which is effective.

(Embodiment 3) In the embodiment described so far,
The buffer 5 has been described as having ideal characteristics as shown in FIG. However, in reality, there is a finite offset voltage Vof as shown by the alternate long and short dash line in FIG. In this case, in the configuration of FIG. 1, since the feedback is performed by the buffer for each addition operation, the offset voltage is also added, and the error increases as the number of additions increases.

In this embodiment, an accurate addition operation can be performed even if the buffer 5 has an offset voltage, and its configuration is as shown in FIG.

The operation of this embodiment will be briefly described with reference to the timing chart of FIG.

In FIG. 7, five signals are input as input signals. First, from time T ₁ to T ₆ , the reference level is input to the input terminal, during which the addition operation shown in the first embodiment is performed. Repeat 5 times. The system that operates at this time is a system that includes the capacitor 1, the sampling MOS 62, the hold capacitor 22, the switching unit 12, the buffer 5, and the switching unit 4. During this period, a low level pulse is applied to φ ₁ and a high level pulse is applied to φ ₂ ,
Since the transistor 11 is in the OFF state and the transistor 12 is in the ON state, the operation is exactly the same as that of the first embodiment. Therefore, the calculation error voltage for five times is held in the hold capacitor 22.

Next, after time T ₆ , when five input signals are input, the calculation result including the calculation error for five times is held in the hold capacitor 21.

During this period, φ ₁ is at high level, φ
_A low level pulse is applied to 2, the MOS transistor 11 is in the ON state, and 12 is in the OFF state.
The operating system is a system including a capacitor 1, a sampling MOS 61, a hold capacitor 21, a switching unit 11, a buffer 5, and a switching unit 4. After the above operation is completed, a difference operation is performed between the hold capacitors 21 and 22, and an addition operation result without error can be obtained.

In this embodiment, the period in which the offset voltage of the buffer 5 is added and the period in which the signal is added are completely separated. However, the signal itself is added in one signal addition. It goes without saying that the period for performing the operation and the period for adding the offset voltage of the buffer may be alternately provided. In this case, an error-free addition result can be obtained even if the number of input signals is unknown.

FIGS. 8 and 9 show an example of a signal processing device for comparison with the present invention. As shown at timings T ₂ , T ₃ and T ₅ , the input signal V _IN from the signal source rises. The noise n was appearing. According to the present invention, it is possible to remove such noise n and obtain a signal having a large dynamic range with an improved SN ratio.

(Fourth Embodiment) With the configuration of the first embodiment, an addition operation of analog signals is performed.

[0041]

[Outside 8] It is described that it is desirable to set C ₁ >> C ₂ in order to increase the gain. However, if C ₁ is increased, the chip size is increased, which leads to an increase in cost, and if C ₂ is reduced to the parasitic capacitance level of the node 9, random noise such as clock noise and thermal noise may increase. To be worried.

The present embodiment has been made in order to solve the above problems, and has a structure as shown in FIG. That is, the buffer means 52 is provided in front of the sampling MOS transistor 6.

The operation of this embodiment will be briefly described below with reference to the timing chart of FIG.

First, in the period from time T ₀ to T ₁ , φ _RS and φ _SH
A high-level pulse is applied to, and the node 8 and the node 9 are initialized to V _CL . Next, at time T ₂ , when the input signal 1 is input from the input terminal V _in , the potential of the node 8 changes.

[0045]

[Outside 9] Only rises. At this time, by designing very small C _S,

[0046]

[Outside 10] Can be

Next, at time T _3, High to φ _SH
By applying a level pulse, the potential of the node 8 is written in the hold capacitor 2 using the buffer 52.
At this time, the input characteristic of the buffer 52 needs to be the same as that of the buffer 5.

After that, when the pulse of φ _SH falls to the low level, the sampling MOS transistor 6 is turned off.
Even if the input signal falls and the potential of the node 8 drops after that, it is not affected.

Next, at time T ₄ , φ _SW goes high.
When a level pulse is applied, the MOS transistor 4 is turned on and the potential of the hold capacitor is written in the node 8. When the input signal 2 is further input,

[0050]

[Outside 11] Then, the addition result of the signal 1 and the signal 2 is obtained.

By repeating the above operation,

[0052]

[Outside 12] The addition operation given by can be realized. According to this embodiment, the addition gain can be increased and the hold capacitance can be increased, and a stable output can be obtained.

Although the connecting means is provided between the coupling means and the holding means in the above-mentioned embodiments, this may not be provided separately.

Further, in the above embodiments, the PN junction capacitance or the MOS capacitance can be used as the hold capacitance and the coupling capacitance, and in addition, as shown in FIG. 12, the hold capacitance is the output amplifier of the latter stage. Input capacity of
There is no problem even if the input capacitance of the feed pack amplifier is used, and in that case, CZ can be reduced, so that the gain of the circuit can be improved.

(Fifth Embodiment) FIG. 13 shows a fifth embodiment of the present invention.

The present embodiment differs from the first embodiment in that the output amplifier is an inverting amplifier, and it is easy to subtract signals by performing the same driving as in the first embodiment. Be understood. Further, here, as the inverting amplifier, for example, a common-emitter amplifier shown in FIG. 14 may be used without any problem.

(Sixth Embodiment) Further, in the circuit presented in the first embodiment, the subtraction can be performed by changing the pulse timing.

FIG. 15 shows a timing chart of the sixth embodiment according to the present invention. The operation will be briefly described below with reference to the circuit diagrams of FIG. 15 and FIG.

First, at time T1, φ _RS and φ _SH are set to H level.
When the high level pulse is applied, the MOS transistors 3 and 6 are turned on, and the nodes 8 and 9 are initialized to the voltage V _CL . Next, at time t ₂ , the input signal rises, but at this time, the nodes 8 and 9 are still in the reset state. At time t ₃ , when the pulse of φ _RS falls, the MOS transistor 3 is turned off, but M
The OS transistor 9 is in the ON state, and the nodes 8 and 9 are conducting. In this state, when the input signal falls at time t ₄ , the nodes 8 and 9 are swung downward via the clamp capacitor 1.

Thereafter, at time t ₅ , φ _{SH is set} to Low.
Level, turn off the MOS transistor 9,
The potential of the node 9 is held. In addition, in the subsequent time t _6, even if joined by the second input signal, node 9 because that is disconnected from the clamp capacity, not affected. Next, at time t ₇ , a high-level pulse is applied to φ _SW to make the potential of the node 8 the same as that of the node 9, and then the time t ₈
At, a high level pulse is applied to φ _SH to bring the nodes 8 and 9 into conduction, and then the pulse of φ _SW is lowered at T9 to make the node 8 floating. Then, at time T ₁₀ , when the input signal falls, the node 9 is swung downward, and as a result, as in the first embodiment,

[0061]

[Outside 13] Is obtained. By repeating this operation as many times as necessary

[0062]

[Outside 14] The subtraction operation of can be realized.

Although the subtraction method has been described above, it will be easily understood that the subtraction can be performed by inverting the input signal itself.

Further, it is possible to provide a plurality of input terminals.

(Embodiment 7) FIG. 16 shows a seventh embodiment of the present invention.

In this embodiment, the input carbon is V _IN1 and V _IN2 is 2
Terminals are provided and clamp capacitors 201, 211 are provided accordingly.
Two sample hold switches 206 and 216 and two feedback switches 204 and 214 are provided.

The operation is exactly the same as that of the first embodiment, and the input may be performed in two systems simultaneously or in a time-division manner.

The clamp capacitance values 201 and 211 are
If you design with different values, input from V _IN1 and V
It is possible to give different weights with the input from _IN2 .

Furthermore, by connecting an inverting amplifier output to one of V _{IN1 and} V _IN2 , addition and subtraction can be performed simultaneously or in time division.

[0070]

According to the present invention, the adverse effects of rising and falling of the input signal can be suppressed, only the signal components can be added substantially, and the dynamic range can be increased.
The SN ratio can be improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a graph showing characteristics of a buffer circuit used in the present invention.

FIG. 3 is a timing chart for explaining the operation of the signal processing device according to the first embodiment.

FIG. 4 is a timing chart for explaining the operation of the signal processing device according to the second embodiment of the present invention.

FIG. 5 is a graph showing another characteristic of the buffer circuit used in the present invention.

FIG. 6 is a circuit configuration diagram of a signal processing device according to a third embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the signal processing device according to the third embodiment.

FIG. 8 is a circuit diagram of a conventional signal processing device.

FIG. 9 is a timing chart for explaining the operation of the conventional signal processing device.

FIG. 10 is a circuit diagram of a signal processing device according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart for explaining the operation of the signal processing device according to the fourth embodiment.

FIG. 12 is a diagram showing a modification of the first embodiment.

FIG. 13 is a circuit diagram of a fifth embodiment.

FIG. 14 is a circuit diagram of a main part of the fifth embodiment.

FIG. 15 is a timing chart of the sixth embodiment.

FIG. 16 is a configuration diagram of a seventh embodiment.

Claims (9)

[Claims] 1. A connection having a signal holding means for holding an input signal from a signal source and a coupling capacitance provided on the signal source side, the connection connecting the coupling capacitance and the signal holding means. Means and
A signal processing device, comprising: first amplifier means provided at both ends of the connecting means via first switch means. 2. The signal processing device according to claim 1, wherein the signal holding means includes a capacitor. 3. The second connecting means is selectively connected.
The signal processing device according to claim 1, further comprising: 4. A second means for outputting the signal of the holding means.
The signal processing device according to claim 1, further comprising: 5. The signal processing device according to claim 1, further comprising third switch means for connecting a connection point between the coupling capacitor and the connection means to a predetermined telegraph. 6. The signal processing device according to claim 1, further comprising a plurality of holding means, and a plurality of connecting means for connecting each holding means to the coupling capacitor. 7. A third device between the coupling capacitor and the connecting means.
The signal processing device according to claim 1, further comprising: 8. The signal processing device according to claim 1, wherein the holding means includes an input capacitance of the first amplifier. 9. The signal processing device according to claim 1, wherein each of the signal sources, the coupling capacitance, and the connection means has a plurality of sets.