JPH0749853A - Program-correctable microcomputer - Google Patents

Abstract

PURPOSE:To provide a microcomputer which can have its program corrected at plural places by one dummy ROM interruption processing circuit without increasing the capacity of a RAM irrelevantly to the number of the correction places. CONSTITUTION:This system consists of the (one-chip) microcomputer 1 and an EEPROM 12 which are both connected to a serial i/O bus 11 and can have a mutual communication, and a correction data writing device 13. The microcomputer 1 is constituted of a CPU 2, a RAM 3, a ROM 4, a pseudo ROM processing circuit 5, and a serial i/O part 8 through an internal bus 9. A desired address value for an interruption process for modifying the program in the ROM 4 is previously set in the pseudo ROM process circuit 5 and when the desired value is reached, the CPU 2 is automatically made to perform the interruption process, thereby executing a program other than that in the ROM 4 during the execution of the program in the ROM 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention uses a pseudo ROM to
The present invention relates to a one-chip microcomputer capable of executing a correction program for writing a program for correcting an inconvenient part of a main program.

[0002]

2. Description of the Related Art Conventionally, a memory device such as a ROM has been provided.
In a chip microcomputer, if some instructions are found to be inconvenient during actual use at the addresses created and stored in the ROM during design, that is, the program When it became necessary to correct the above, it had to be manufactured again and rewritten to a new program.

To solve this problem, Japanese Patent Laid-Open No. 1-232447 discloses a one-chip microcomputer having an internal memory for storing the correction data and a plurality of interrupt PC comparison registers in order to modify the program at a plurality of locations. ing.

Further, in Japanese Laid-Open Patent Publication No. 57-155642, in order to correct an arbitrary address, the correction start address is compared with the PC value, and after it is detected that they coincide with each other, the interrupt processing is used for correction. A one-chip microcomputer that jumps to a modified address in ROM is disclosed.

[0005]

However, since the one-chip microcomputer disclosed in the above-mentioned Japanese Patent Laid-Open No. 1-232447 provides a memory and a register by predicting the number of modifications, there are many points to be modified. The hardware had to be increased so much that it was estimated.

Further, in the one-chip microcomputer disclosed in JP-A-57-155642,
When there are a plurality of correction points, there is a drawback that a plurality of interrupt processing circuits are required, but no countermeasure method is disclosed.

Therefore, according to the present invention, regardless of the number of correction points,
An object of the present invention is to provide a microcomputer capable of modifying a program at a plurality of locations with one pseudo ROM interrupt processing circuit and without increasing the capacity of RAM.

[0008]

In order to achieve the above-mentioned object, the present invention provides a one-chip microcomputer provided with a serial communication interface circuit capable of communicating with an external memory and an external device via an external bus, in which a predetermined value is set in advance. A latch means for storing an address value is compared with an address value stored in the latch means and a program counter value during execution of the main program while the main program stored in the main memory of the one-chip microcomputer is being executed. By doing so, it comprises an interrupt generation means for generating an interrupt at an arbitrary address, and a program correction means for executing the correction program stored in the external memory via the external bus by the generation of the interrupt while reading it out at once. To provide a microcomputer capable of executing a modification program .

[0009]

[Operation] The microcomputer configured as described above
Code No. is assigned to each subroutine module. The subroutines that need to be corrected are recorded, and when the subroutines that need to be corrected are executed, the address that requires an interrupt or the correction program at the time of an interrupt is read from the EEPROM at once. The increase / decrease of bytes due to the increase / decrease of the correction location is adjusted by adjusting the capacity of the EEPROM without using the memory capacity of the RAM for other processing in the microcomputer.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a conceptual diagram of the configuration of a microcomputer capable of executing a correction program according to the present invention. The present invention relates to a microcomputer (1 chip microcomputer) connected via a serial i / O bus 11.
1, EEPROM 12, and correction data writing device 13
Each block consists of a serial i /
By loading data on the O-bus 11, bidirectional communication is possible.

Since the correction data writing device 13 generally writes at the time of manufacture, it may be removed when shipped to the user. This microcomputer 1
Via the internal bus 9, CPU2, RAM3, ROM
4, a pseudo ROM processing circuit 5 and a serial i / O unit 8. The CPU 2 is a ROM for the internal sequence control and logical operation of the microcomputer 1.
4 are sequentially executed according to the instructions written as a program in advance.

The RAM 3 is used as a working area for temporarily storing intermediate processing data such as calculation or storing adjustment values (including flags) transferred from the EEPROM 12 when the program is executed. The serial i / O unit 8 is the serial i / O bus 1
In the data communication performed via 1, the serial data of 8 bits to 16 bits per unit word is transmitted / received to / from the EEPROM 12 or the correction data writing device 13.

The transmitted / received data at this time is sent to the RAM 3 via the internal bus 9 of the microcomputer 1 if necessary.
It is also stored in the PC value latch unit 7 in the pseudo ROM processing circuit 5. The PC comparison register section 6 in the pseudo ROM processing circuit 5 compares the value held in the PC latch section 7 with the address value (program counter value) of the address bus of the internal bus 9, and the values match. Then CP
The interrupt request signal 10 is output to U2. That is, if an arbitrary address value for which interrupt processing is desired is set in advance in the PC value latch unit 7 in the pseudo ROM processing circuit 5, when the value of the program counter becomes equal to the value of the PC value latch unit 7. , CPU2 can be made to perform an interruption process automatically. In other words, if one pseudo ROM processing circuit 5 is provided, a program other than the ROM 4 can be executed during execution of the program in the ROM 4.

For example, in a normal main routine, there are a plurality of subroutine modules. When it is desired to change the program for some of the subroutine modules, a module code N is used as an identification code for distinguishing each subroutine module in advance.
O. Allot it.

Next, FIG. 2A shows the concept of the subroutine module identification code, and FIG. 2B shows an example of its format. As described above, the subroutine routine of various sizes exists in the normal main routine. Therefore, in order to avoid confusion, the module code NO. give.

As shown in FIG. 2 (b), the lower 6 bits (bit 5 to LSB) per byte are used as the module code NO. , If the remaining 2 bits (MSB, bit6) represent the number of correction points in the module, the maximum number of modules that can be handled is 64 (3F (H) to 0 (H)), and the maximum number of correction points is 4 points. (3 (H) to 0 (H)).
Of course, if the number of bits is increased, the number of modules to be handled and the number of correction points can be increased.

As described above, the module code NO. The subroutine module to which is given is to perform rewriting and correction of the ROM 4 shown in FIG. 1 if the correction execution address value, the correction execution interrupt address value and the correction program necessary for executing the interrupt processing are secured in the EEPROM 12. Even without it, the follow-up correction is possible. If there is no correction, it is not necessary to secure the memory area of the EEPROM 12, and the memory capacity of the EEPROM 12 is not wasted.

In FIG. 3, the data is secured in the EEPROM (hereinafter,
An example of the data format at the time of the interrupt processing will be shown. The data format of FIG. 3 assumes an 8-bit / address EEPROM, but there is no restriction on the bit length, and there is no inconvenience even if a 16-bit / address EEPROM is used.

First, in the head address @ 0XX (H) of the pseudo ROM correction data area, the number of correction points and the module code NO. To store. The next 1 byte represents the total number of bytes used in the EEPROM that this module needed to modify. Addresses after (start address + 2) store a correction execution address (number of bytes used, start address), a correction execution interrupt address (upper address, lower address), and a correction program sequentially.

In the case of the example shown in FIG. 3, three correction points are assumed in one module (module code No .: 1A (H)). Therefore, the number of bytes required to specify the lower address value of the first correction execution interrupt address is 14 bytes. However, the number of bytes used with * is not particularly required because the number of bytes of each correction program can be found by subtracting the value of each correction program start address. In this example,
The number of used bytes in the first to third correction program areas is a value (38 bytes) obtained by subtracting the 14 bytes from the total number of used bytes (52 bytes).

Next, referring to FIG. An example of a flowchart when the subroutine module of m is executed is shown. First, code NO. When the m sub-module is executed, EEPR
The code No. is selected from the correction execution flags transferred from the OM 12 to the flag area of the RAM 3. The flag of m is searched (step S1).

These code NO. The flag of FIG.
1 bit is allocated to each flag area of the RAM (the flag area is assigned from address 100 (H) in the figure) as shown in FIG. When the bit of "1" is "1", there is correction, and when it is "0", there is no correction (@ 1, @ 3, @ 14, etc. in the figure are code numbers with correction).

Similarly, the corresponding code No. The presence or absence of the flag of m is determined (step S2), and if there is no flag (NO), it is determined that there is no correction, and the process immediately proceeds to step S5 described later to execute the main program of the subroutine module, and the subroutine module After the main program execution is completed (step S7), the process returns to the main routine.

However, if it is determined in step S2 that the flag is present (YES), communication with the EEPROM is started,
Code NO. m “Number of corrections, module code N
O. "Reference area". As described above, pseudo R
If the start address @ 0XX (H) of the OM correction data area is predetermined, the next 1 byte (start address +
By referring to the total number of used bytes in 1), the following module code No. The address of the reference area is known.
That is, as shown in FIG. 9, the module code NO. The reference area can be searched and vice versa.

The code No. obtained in this way. m, the number of correction points S and the code No. The address of the pseudo ROM correction data area of m is stored (step S3). At the same time, the nth correction execution interrupt address is held in the PC value latch unit 7 in the pseudo ROM processing circuit 5 of the microcomputer 1 in FIG. 1 (step S4). After that, while executing the main program of the subroutine module (step S5), the process waits for the nth interrupt request generation (step S6).

Next, when the nth interrupt request is issued to the CPU 2 in the microcomputer 1 of FIG. 1 (YES), execution of the program starts from the address designated by the interrupt vector table. At this time, the number of bytes used for the n-th correction execution address is set to EEPROM1.
2, the nth correction program is written in the correction execution area of the RAM based on the data (step S8), and the nth correction location is executed (step S9). Then, the value of the number of correction points S is determined (step S10), and when S = 0 (YES), the process proceeds to step S5. If S ≠ 0 (NO), the number S of correction points is decremented (step S11), then the process proceeds to step S4 and the above-described processing is executed again.

FIG. 5 is a branch diagram showing how the flowchart shown in FIG. 4 is executed. In the figure, S1, S4 and S8 correspond to step S1, step S4 and step S8 in FIG. Further, (1) to (16) represent the order of branching (branching is executed in ascending order of the number). In this example, modification interruptions are generated three times and the program is modified three times.

Next, FIG. 6 shows a configuration example in which a microcomputer capable of executing a correction program according to the first embodiment of the present invention is mounted on an actual camera and controlled. In this camera, a microcomputer 25 that performs the entire sequence and control of the camera
And a distance measuring unit (AF) 21 for measuring the distance to the subject
And a photometric unit (AE) 22 for measuring the brightness of the subject,
EERPOM that stores the adjustment values of the camera and the ROM correction data that is a feature of the present invention with a flash 23 that charges and emits a flash and an electrically rewritable nonvolatile memory
24, an external communication connector 30 for connecting a camera adjuster and a device for writing ROM correction data, a drive unit 29 including a plurality of motors and a photo interrupter for operating each unit, and the drive unit. It is composed of switch groups 27, 28 and the like for executing a predetermined operation of each block of 29 and a motor driver 26 for driving each motor.

The drive unit 29 drives a shutter, a motor M _S , a film winding and rewinding motor M _W , a zoom lens driving motor M _Z, and a focus lens driving motor M _L. A switch SW _L for detecting the initial position of the focus lens, a photo interrupter Pi _L for detecting the unit drive amount (position) of the focus lens, a photo interrupter Pi _Z for detecting the position of the zoom lens, and a perforation of the film are detected. A photo interrupter Pi _W , a switch SW _S for detecting the initial position of the shutter, and a magnet Mg for closing the shutter. Each block executes a predetermined operation by operating the switch groups 27 and 28.

Next, FIG. 7 shows a main flow chart in the control operation of the camera configured as shown in FIG. First, when the power (battery) is turned on, the power-on reset functions, and after setting the stack pointer inside the microcomputer 25 (step S21), the input / output ports and registers are initialized (step S2).
2).

Next, by executing the ROM correction data setting subroutine, the correction execution flag indicating whether or not the main subroutine module in the main flow chart is corrected is set to E.
RA from EPROM 24 to microcomputer 25
Transfer is set to the flag area of M (not shown) (step S23).

Then, the next interrupt setting (step S24)
Then, enable the necessary interrupts. After that, a battery check is performed (step S25), and if it is good, the sequence proceeds to the camera. First, power SW ON / OFF
Check the state (step S26), and if OFF,
The LCD display is turned off (step S27), and at the same time, the energy saving mode in which no current flows through the ports is selected (step S28), that is, the standby mode is set (step S29).

However, the power SW is turned on in step S26.
If so, the LCD is displayed (step S30), and charging of the strobe is started (step S31). Then 1
The state of the st release SW is judged (step S32),
If it is pressed (ON), release processing is performed (step S36). However, if the 1st release SW is not pressed (NO), it is determined whether the zoom-up SW or the zoom-down SW is pressed (step S33), and if it is pressed (ON), zoom processing is performed (step S33). Step S37).

Further, if the zoom SW is OFF, it is judged whether or not the strobe mode SW is pressed (step S
34), if the strobe mode SW is pressed, the strobe mode process is performed (step S38). If the strobe mode SW is not pressed (step S35), it is determined whether or not the mode SW is pushed next (step S35). ), If pressed (YES), the mode SW process (step S39) is performed. The above flow chart is for power SW
Is repeated until is turned off.

FIG. 8 shows an example of the release process in the subroutine module in the main flow chart of FIG. Here, @ 1 to @ 5 in the figure are code numbers.
Represents the allocated subroutine module.

In this release process, first, 1s
After the t-release is turned on, the AF unit AF21 shown in FIG.
And the photometric unit AE22 to measure the distance (step S4
1), followed by photometry (step S42). Then, the ON / OFF state of the second release is judged (step S43). If the second release is OFF, it is judged whether or not the first release is ON (step S44), and ON.
If it is, the state is maintained, and if it is OFF, the release process is interrupted and the process returns to the main flow. here,
The 1st release SW and the 2nd release SW are two-step switches, and the 1st release S is the 1st release S.
W is a switch that turns on the second release SW in the second stage.

When the second release is turned on, the focus lens is driven (step S45), the focus is adjusted, and the shutter is driven to perform exposure (step S4).
6). Finally, wind the film (step S47),
The release process ends.

In the above-mentioned release processing, when each subroutine module is executed, the code NO. (Here, the code numbers corresponding to @ 1 to @ 5 are set at the beginning of the program of the subroutine module.)
The flag area of the RAM as shown in 0 is searched.

For example, @ 1 to @ 5 in FIG. 8 are @ 1 in FIG.
If it corresponds to ~ @ 5, each bit is set to "1" in the @ 1, @ 3, and @ 5 subroutine modules (distance measurement, focus lens drive, and film winding). Is found to occur. Therefore, when these subroutine modules are executed, the processes of steps S3 to S11 in the flowchart of FIG. 4 are performed.

FIGS. 11 and 12 show how two positions are actually corrected in driving the focus lens of the @ 3 subroutine module. In the figure, the right side of the one-dot broken line drawn vertically is a flowchart showing the contents of the main program of the @ 3 subroutine module, and the left side is a modification program for the main program by the pseudo ROM interrupt processing of the present invention. It is a flowchart of a part.

First, the processing for determining the state of the switch SW _L for detecting the initial position of the focus lens in step S57 is performed from the state detection of the correction execution flag in step S51 which is normally set. Here, only the characteristic part will be described.

Next, the Pi _L pulse width count is started immediately after the focus lens driving is started (step S5).
8), Pi _L in order to measure the time for one pulse cycle
Rise detection is performed (step S59). Then, edge detection (step S60), damage timer timing (step S69), and damage timer time limiter (0.5) are detected until the rise of the pulse for each cycle is detected.
s) Form a series of loops for detection (step S8).

The first correction execution interrupt is generated after the time limiter of the damage timer is detected. That is, the M _L motor in the main program is turned off (step S7
Since the execution of 1) becomes inappropriate, the pseudo ROM interrupt process causes the flow chart of S1 (steps S73 to S73).
After executing the correction program as shown in 75), the main program is returned to the damage mode (step S72) again.

Similarly, even when the second correction execution interrupt is generated, the execution of the M _L motor BRK (step S77) in the main program becomes improper, and as shown in the flowchart of S2 (steps S78 to S79). After executing the correct patch, it returns to the main program again.

As described above, in each of the subroutine modules, the interrupt processing is generated with respect to an arbitrary plurality of addresses, so that the non-rewritable ROM can be easily modified. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and applications can be made without departing from the scope of the invention.

[0046]

As described above, according to the one-chip microcomputer of the present invention, even after the manufacture, the desired correction program is added to the pre-installed EEPROM so that the ROM cannot be rewritten. Since it is possible to make corrections (including data changes) when executing the program, even if a defect in the program that needs correction is discovered just before or during production, the ROM at design time
It is possible to easily deal with corrections such as defects and improvements without needing to change the mask.

As described in detail above, according to the present invention, regardless of the number of correction points, it is possible to modify the program at a plurality of points with one pseudo ROM interrupt processing circuit and without increasing the capacity of the RAM (one chip). A computer can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a concept of a configuration of a microcomputer capable of executing a correction program according to the present invention.

FIG. 2A is a diagram showing an example of a subroutine module identification code of the present invention, and FIG. 2B is a diagram showing an example of its format.

FIG. 3 is a diagram showing an example of a data format secured in the EEPROM shown in FIG. 1 at the time of interrupt processing.

4 is a code No. in the microcomputer shown in FIG. It is a flow chart of one example of execution of a subroutine module of m.

FIG. 5 is a branch diagram showing how the flowchart of FIG. 4 is executed.

FIG. 6 is a diagram showing a configuration example in which a microcomputer capable of executing a correction program as an embodiment according to the present invention is mounted on an actual camera and controlled.

7 is a main flowchart for explaining a control operation of the camera shown in FIG.

8 is a flow chart for explaining a release process in a subroutine module in the main flow chart shown in FIG.

FIG. 9 is a module code NO. It is a figure which shows an example of a reference area.

FIG. 10 is a diagram showing an example of a flag area of a RAM in this embodiment.

FIG. 11 is a first half of a flowchart showing an example in which correction is performed at two points in driving the focus lens of the subroutine module in the present embodiment.

FIG. 12 is a second half of a flowchart showing an example in which correction is performed at two points in driving the focus lens of the subroutine module in the present embodiment.

[Explanation of symbols]

1, 25 ... Microcomputer (1 chip microcomputer), 2 ... CPU, 3 ... RAM, 4 ... ROM,
5 ... Pseudo ROM processing circuit, 6 ... PC comparison register section, 7
... PC value latch unit, 8 ... Serial i / O unit, 9 ... Internal bus, 10 ... Interrupt request signal, 11 ... Serial i / O bus, 12,24 ... EEPROM, 13 ... Corrected data writing device, 21 ... Distance measurement Section (AF), 22 ... Photometric section (A
E), 23 ... Strobe, 26 ... Motor driver, 27,
28 ... Switch group, 29 ... Drive unit, 30 ... External communication connector.

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[Procedure amendment]

[Submission date] May 23, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

Next, when the nth interrupt request is issued to the CPU 2 in the microcomputer 1 of FIG. 1 (YES), execution of the program starts from the address designated by the interrupt vector table. At this time, the n-th correction execution address and the number of used bytes are stored in the EEPROM 1
2, the nth correction program is written in the correction execution area of the RAM based on the data (step S8), and the nth correction location is executed (step S9). Then, the value of the number of correction points S is determined (step S10), and when S = 0 (YES), the process proceeds to step S5. If S ≠ 0 (NO), the number S of correction points is decremented (step S11), then the process proceeds to step S4 and the above-described processing is executed again.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

The drive unit 29 drives a shutter, a motor M _S , a film winding and rewinding motor M _W , a zoom lens driving motor M _Z, and a focus lens driving motor M _L. A switch SW _L for detecting the initial position of the focus lens, a photo interrupter Pi _L for detecting the unit drive amount (position) of the focus lens, a photo interrupter Pi _Z for detecting the position of the zoom lens, and a perforation of the film are detected. photointerrupter Pi _W, a switch SW _S for detecting the initial position of the shutter, and a magnet Mg for closing the shutter. Each block executes a predetermined operation by operating the switch groups 27 and 28.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 12

[Correction method] Change

[Correction content]

[Fig. 12]

Claims (1)

[Claims] 1. A one-chip microcomputer provided with an external memory and a serial communication interface circuit capable of communicating with an external device via an external bus, latch means for storing a predetermined address value in advance, and the inside of the one-chip microcomputer. Interrupt generating means for generating an interrupt at any address by comparing the address value stored in the latch means with the program counter value during execution of the main program during execution of the main program stored in the main memory And a program correction means for executing the correction program stored in an external memory through an external bus when the interruption occurs, while executing the correction program.