JPH0748656B2 - Phase synchronization circuit - Google Patents

Description

The present invention relates to a phase locked loop circuit in a synchronous modulator / demodulator.

(Prior Art) Generally, in a transmission system using multi-phase PSK modulation or quadrature amplitude modulation, a timing component is first extracted from a modulation signal received by a data modem or the like, a timing phase is detected, and reception including the data modem or the like is performed. It is necessary to establish synchronization within the system. Phase synchronization circuits for this purpose have been disclosed in Japanese Patent Laid-Open Nos. 56-119552, 56-35551 and 57-173243.

FIG. 3 is a block diagram showing the configuration of a conventional phase locked loop circuit. In the figure, reference numeral 301 is a reference signal input terminal, 302 is a sample circuit, 303 is a quantization circuit, 304 is an up / down counter, 305 is a programmable counter, 306 is a N frequency dividing counter, 307 is a phase synchronization signal output terminal, and 308 is 308. A clock signal input terminal, 309 is an output signal of the sample circuit 302, and 310 is an output signal of the up / down counter 304. Here, the reference signal input to the reference signal input terminal 301 is to be extracted from the received signal in the receiving section of the synchronous modulation / demodulation apparatus (not shown) through a filter or the like. Therefore, the amplitude and phase of this reference signal are subject to large instantaneous fluctuations. The up / down counter 304 integrates the quantized output of the quantization circuit 303. For example, the input “1” counts up and the input “0” counts down. The output frequency of the divide-by-N counter 306 when the output signal 310 is not in phase control is set to have a nominal value that matches the reference signal. The clock signal input to the clock signal input terminal 308 is obtained from an independent oscillation source of the receiving unit, and the N frequency dividing counter 306 in the state where the phase control is not performed.
The output signal of does not always match the phase and frequency of the reference signal. This is because, as described above, the reference signal is extracted from the received signal, and its oscillation source is on the transmitting side and is different from the independent oscillation source of the receiving section.

Next, the operation will be described, but the reference signal is assumed to be a sine wave for simplification. Here, FIG. 4 shows the signal waveform of each part of FIG. As can be seen from FIG. 4, the reference signal is a sine wave. Further, the signal waveform 307A is a signal obtained from the phase synchronization signal output terminal 307 and is a signal when the phase is advanced as compared with the reference signal, and the signal waveform 307B is when the phase is delayed as compared with the reference signal. It is a signal.

First, the sample circuit 302 samples the reference signal at each rising edge of the signal waveforms 307A and 307B and obtains, as its output signal 309, a negative value for the signal waveform 307A and a positive value for the signal waveform 307B. This sample output is quantized by the quantization circuit 303, and the up / down counter 304 is controlled by the quantized output. Here, the simplest quantization is to encode positive and negative and is converted into a logical "1" or "0". The output signal 310 from the up / down counter 304 is based on the up count value and the down count value set in advance according to the magnitude of integration. Therefore, there are three states: when the count is equal to or more than the set up count (state 1), between the set up count and the down count (state 2), and when the count is less than or equal to the set down count (state 3).

In this state 2, the programmable counter 305 is controlled as a 1 / M counter. As a result, the nominal clock frequency is output to the phase synchronization signal output terminal 307 together with the 1 / N counter of the N frequency division counter 306.

In this state 1 or state 3, the programmable counter 30
5 is controlled as a 1 / (M + 1) or 1 / (M-1) counter. As a result, the phase is advanced or delayed.

Further, the up-down counter 304 gives a constant down-count to the state 1 and a constant up-count to the state 3 after the phase advance or delay control by the state 1 or the state 3 in order to enhance the integration effect.

(Problems to be Solved by the Invention) However, in the above-mentioned conventional circuit, it is necessary to reduce the integration of the up / down counter in order to absorb the frequency deviation on the transmission side, but with this, the reference signal On the other hand, there is a problem in that the output jitter increases and equivalently becomes noise, which deteriorates the demodulation performance of the receiving unit.

The present invention is to solve these problems, and provides a phase synchronization circuit that can follow the frequency deviation on the transmission side without increasing the output jitter and can significantly reduce the noise due to the output jitter. The purpose is to do.

(Means for Solving Problems) In order to solve the above problems, the present invention provides first means for sampling a reference signal extracted from a received signal based on a phase synchronization signal and quantizing the sample output. , First
Connected to a stage subsequent to the means, integrating the quantized signal by the first means, third means for dividing the phase synchronization signal by two, and output signal of the third means for phase Fourth means for controlling the phase based on a clock signal independent of the synchronization signal, a first integrator for integrating the sample output value of the phase synchronization signal which is the output signal of the first means, and the first integrator. A sample circuit that samples each time the output of the integrator is out of the predetermined value range, a second integrator that integrates the output value of this sample circuit, and each time the output of this second integrator overflows. Fifth means having a detector for outputting an overflow detection signal, and the phase of the output signal of the third means is inverted according to the overflow detection signal output by the fifth means and the output signal from the second means. Let me 4th
And a sixth means for supplying the above means.

(Operation) According to the present invention having the above technical means, the following operations are performed.

The reference signal extracted from the received signal is sampled by the first means based on the fed back phase synchronization signal and the sampled output is quantized. The second means integrates the signal quantized by the first means. On the other hand, the fed back phase synchronization signal is divided by two by the third means. Then, the first integrator integrates the sample output value of the phase synchronization signal which is the output signal of the first means. The sampling circuit samples each time the output of the first integrator is out of the range of the predetermined value. Then, the second integrator integrates the output value of the sample circuit, and outputs an overflow detection signal every time the integrated output overflows. The sixth means inverts the phase of the output signal of the third means according to the output overflow detection signal and the output signal from the second means, and supplies the inverted signal to the fourth means. And
The signal supplied to the fourth means is subjected to phase advance control or lag control by the fourth means on the basis of an independent clock signal to become a phase synchronization signal.

Therefore, the present invention can solve the above problems and provide a phase locked loop circuit that can suppress output jitter and absorb frequency deviation.

(Embodiment) An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 101 is a reference signal input terminal, 102 and 111 are sample circuits, 103 is a quantizer circuit, 104 is an up / down counter, 105 is a 1/2 frequency divider circuit, 106 is a switch circuit, 107 is a programmable counter, and 108 is N. A frequency dividing counter, 109 is a phase synchronization signal output terminal, 110 and 112 are perfect integrating circuits, and 113 is an overflow detector. Here, the perfect integrating circuits 110, 11
2 is composed of an adder and a register. The reference signal is input to the sample circuit 102 via the reference signal input terminal 101. The sample signal to the sample circuit 102 is the output signal from the N frequency division counter 108. The output signal of the sample circuit 102 is input to the quantization circuit 103 and the perfect integration circuit 110. The quantized signal from the quantization circuit 103 is input to the up / down counter 104. The output signal of the up / down counter 104 is input to the switch circuit 106. And N
The output signal of the frequency dividing counter 108 is input to the 1/2 frequency dividing circuit 105, and the output signal of the 1/2 frequency dividing circuit 105 is input to the switch circuit 106. The output signal of the switch circuit 106 is input to the programmable counter 107, and the clock signal is further input via the clock signal input terminal 114 to the programmable counter 1.
Entered in 07. And the programmable counter 107
Is output to the N frequency dividing counter 108, and the output signal of the N frequency dividing counter 108 is output to the phase synchronization signal output terminal 109. The output signal of the perfect integrating circuit 110 is the sample circuit 111.
And the output signal of the sample circuit 111 is input to the complete integration circuit 112. Then, the output signal of the complete integration circuit 112 is input to the overflow detector 113, and the output signal of the overflow detector 113 is supplied as the sample signal of the sample circuit 111 and also input to the switch circuit 106.

Next, the operation of the embodiment will be described.

First, the reference signal input to the sampling circuit 102 from the reference signal input terminal 101 is sampled by the output signal of the N frequency dividing counter 108. This sample output is the quantization circuit 103.
Is quantized in and input to the up / down counter 104. The up / down counter 104 integrates the output of the quantization circuit 103 and outputs an overflow signal or an underflow signal when the integrated value exceeds a predetermined range. This overflow signal or underflow signal is supplied to the switch circuit 106.

The output signal of the N frequency division counter 108 is the 1/2 frequency division circuit 10
2 shows the signal waveform of each part of the circuit of the present embodiment by 5
As you can see from the figure, it is divided by two. At this time, if the phase is not controlled, the output signal of the switch circuit 106 has the same waveform as the output signal of the 1/2 divider circuit 105. When such an output waveform is input to the programmable counter 107,
When the output waveform of the switch circuit 106 is “1”, the programmable counter 107 outputs the phase-advancing control, that is, 1 / (M−1) counter, and the “0” output, the phase-lag control, that is, 1 / (M + 1) counter. Control over the waveform. In this case, the advance / lag control is repeated for each cycle of the output signal of the N frequency division counter 108, and as a result, the phase is not controlled. Next, if the phase is controlled, the output waveforms A and B of the switch circuit 106 in FIG. 2 are obtained.

That is, the fact that the up / down counter 104 outputs the overflow signal means that the timing of sampling with respect to the reference signal is delayed, and in this case, the phase advance control is performed. The phase advance control is performed by the switch circuit 106 shown in FIG.
As in the output waveform A of, only the section of "1" increases by a half cycle. This is the output of the 1/2 divider circuit 105 inverted from the point of. On the other hand, the up / down counter 104
The output of the underflow signal means that the timing of sampling has advanced with respect to the reference signal, and in this case, the lag control is performed. In the lag control, as in the output waveform B of the switch circuit 106 in FIG. 2, the “0” section is increased by a half cycle. This is the output of the 1/2 divider circuit 105 inverted from the point of.

Next, the sample output of the sample circuit 102 is also input to the complete integration circuit 110. In the perfect integration circuit 110, the DC component of the phase error of the sample output of the sample circuit 102,
That is, the frequency deviation is integrated. This integrated value is output to the overflow detector 1 described later by the sampling circuit 111.
Every overflow detection by 13 is sampled. The value sampled by the sampling circuit 111 is further integrated by the perfect integration circuit 112. The output of the complete integration circuit 112 is supplied to the overflow detector 113. The overflow detector 113 outputs an overflow detection signal when the output value of the perfect integration circuit 112 exceeds a predetermined value.

When this overflow signal is supplied to the sampling circuit 111, the sampling circuit 111 samples the integrated value of the perfect integrating circuit 110. That is, the complete integration circuit 110 is a circuit that integrates the frequency deviation of the sampled output of the sampling circuit 102, and this integrated value is sampled every time the complete integration circuit 112 overflows. Here, if the frequency deviation of the sample output of the sample circuit 102 is large, the rate of increase of the integral value of the perfect integrating circuit 110 and the perfect integrating circuit 112 becomes large. As a result, the period until the overflow is shortened and the time until the overflow detection signal is generated is shortened. Therefore, the interval at which the sampling circuit 111 samples the integrated value of the perfect integrating circuit 110 also becomes short. In this way, the magnitude of the frequency deviation is converted into the overflow cycle in the overflow detector 113.

As described above, the switch circuit 106 is supplied with the overflow signal or the underflow signal from the up / down counter 104, the frequency division output from the 1/2 frequency divider circuit 105, and the overflow detection signal from the overflow detector 113, respectively. There is. As a result, when the switch detection circuit 106 receives the overflow detection signal, it controls the phase of the output of the 1/2 frequency dividing circuit 105 according to the output of the up / down counter 104. That is, in this embodiment, there are two systems, a circuit for performing the phase control itself and a circuit for determining the cycle of the phase control. By performing the phase control in a shorter cycle as the deviation of the sample timing with respect to the reference signal increases
The phase control signal for the jitter from the up / down counter 104 and the phase control signal for the frequency deviation from the overflow detector 113 are combined, and the jitter and the frequency deviation are simultaneously absorbed.

(Effects of the Invention) As described above, according to the present invention, the output jitter with respect to the reference signal and the frequency deviation on the transmission side can be absorbed at the same time, so that the frequency deviation on the transmission side can be tracked without increasing the output jitter. It is possible to provide a phase locked loop circuit that can significantly reduce noise due to output jitter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing signal waveforms of respective parts of the circuit of this embodiment.
FIG. 3 is a block diagram showing a conventional phase locked loop, and FIG. 4 is a time chart showing signal waveforms at various parts of the conventional phase locked loop. 101 ... Reference signal input terminal, 102,111 ... Sample circuit, 103
… Quantization circuit, 104… Up / down counter, 105… 1/2
Frequency divider circuit, 106 ... Switch circuit, 107 ... Programmable counter, 108 ... N frequency divider counter, 109 ... Phase synchronization signal output terminal, 110, 112 ... Complete integration circuit, 113 ... Overflow detector.

Claims (1)

[Claims] 1. A first means for sampling a reference signal extracted from a received signal on the basis of a phase synchronization signal and quantizing the sample output, and a first stage connected to the latter stage of the first means, Second means for integrating the signal quantized by the means, third means for dividing the phase synchronization signal by two, and an output signal of the third means for a clock signal independent of the phase synchronization signal. A fourth means for controlling the phase based on the above, a first integrator for integrating a sample output value of the phase synchronization signal which is an output signal of the first means, and an output of the first integrator are predetermined. A sampling circuit that samples every time the value of is out of the range, and a second circuit that integrates the output value of the sampling circuit
Second integrator and a detector that outputs an overflow detection signal each time the output of the second integrator overflows; the overflow detection signal output by the fifth means; According to the output signal from the means of
Means for inverting the phase of the output signal of the means and supplying it to the fourth means, with respect to the output signal from the third means obtained via the sixth means. Then, the phase synchronization circuit obtains the phase synchronization signal by controlling the phase by the fourth means.