JPH0748558B2 - Basic cell and array structure of basic cell - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to SOG (Sea Of Gates).
The present invention relates to a basic cell and an array structure of basic cells in a large scale integrated circuit (LSI).

[0002]

2. Description of the Related Art Conventionally, as a basic cell structure in an SOG type LSI, a structure shown in FIG. 12 is generally used. N
A pair of gate electrodes 2a and 2b having a bilaterally symmetrical structure with respect to the center line C is formed on the region 1, and two P-channel MOSFs are formed.
ET is configured. In addition, the center line C is also on the P region 3.
A gate electrode pair 4a, 4b having a bilaterally symmetrical structure is formed, and two N-channel MOSFETs are formed. The basic cell 5 is composed of the elements formed on the N region 1 and the P region 3.

An arrangement structure of basic cells in the SOG type LSI is shown in FIG. 13, which is formed by alternately arranging P-channel type transistor rows 7 and N-channel type transistor rows 8 on a master slice 6. There is. The basic cell 5 includes N-channel type MOSFETs and P-channel type MOSFETs in adjacent columns as shown by the hatched portion in FIG.
Are configured by combining.

[0004]

Since the above-mentioned conventional basic cell structure is symmetrical with respect to the center line C only in the left-right direction, when the basic cells are formed on the master slice 6, they are different in type. It is possible to form the basic cell in the direction in which the transistors are arranged, that is, in the left-right direction in FIG. However, it is impossible to form a basic cell in the direction in which the same type of transistors are arranged, that is, in the vertical direction in FIG. Therefore, some transistors in each column are not used, and the space on the semiconductor chip is wasted.

Further, when a logic cell such as a logic gate or a logic block is realized on a semiconductor chip, it is possible to realize the logic cell in terms of use area, but the logic cell is formed due to the shape limitation. There are cases where you cannot do it. This is because the logic cell cannot be configured in the vertical direction.

As a result, it becomes difficult to highly integrate the elements in the SOG type LSI, and the degree of freedom in wiring pattern design is restricted.

[0007]

The present invention has been made in order to solve such a problem, and a gate width direction is taken around a certain point along the direction surrounding this point. A basic cell is formed by including a gate electrode divided into four regions by two straight lines passing through at right angles to each other, and a drain region and a source region formed on both sides of a channel layer under each gate electrode.

A basic cell is constructed by forming a plurality of gate electrodes divided into four regions symmetrically with respect to a center line in the gate width direction that divides each region into two.

Of the gate electrodes divided into four regions, the channel layer under each of the opposing gate electrodes is P
A plurality of basic cells in which a channel and a channel layer under each of the other opposing gate electrodes are N-channels are arranged adjacent to each other.

Further, a basic cell in which all the channel layers under each gate electrode divided into four regions are formed as P-channels, and all the channel layers under each gate electrode divided in four regions are formed as N-channels. A plurality of basic cells that are alternately adjacent to each other.

[0011]

By arranging the gate width direction of the gate electrode along a direction surrounding a certain point as the center, it becomes possible to assemble basic cells vertically and horizontally on the master slice.

Further, by forming a plurality of gate electrodes symmetrically with respect to the center line in the gate width direction that divides each region into two, basic cells can be assembled not only in the vertical and horizontal directions but also in the diagonal direction on the master slice. become.

Further, by arranging a plurality of basic cells adjacent to each other, a channel layer under one gate electrode facing each other is formed as a P channel and a channel layer under the other gate electrode is formed as an N channel. , A basic cell in which the channel layers under each gate electrode are all P-channel and all N
By arranging a plurality of basic cells that are formed in the channel alternately adjacent to each other, it is possible to construct a circuit configuration that is completely equivalent in each direction.

[0014]

EXAMPLE An SOG type L according to a first example of the present invention will now be described.
The basic cell structure of SI is shown in FIG. FIG. 10A is a plan view of one basic cell 11a formed on the master slice, and FIG. 11B is Ib-Ib in FIG.
It is a line sectional view.

In the basic cell 11a, gate electrodes 12 to 15 whose gate width direction is taken along the direction surrounding the center point are provided.
Are formed. These gate electrodes 12 to 15 are divided into four regions by vertical lines and horizontal lines passing through the center points, and are formed in two polygonal lines in each divided region.
Of the gate electrodes 12 to 15 divided into four regions, the opposing gate electrodes 14a, 14b, and 15
a and b are formed on the P region 16. An oxide film 17 shown in FIG. 2B is formed on the substrate under each gate electrode 14, 15, and an N channel is formed in the channel layer under each gate electrode 14, 15 via this oxide film 17. It is formed. Also, the other opposing gate electrodes 12a, 12b
And 13a and 13a and 13b are formed on the N region 18. The P region 16 is formed on the substrate below each of the gate electrodes 12 and 13.
An oxide film is formed in the same manner as in the above case, and a P channel is formed in the channel layer below each of the gate electrodes 12 and 13 via this oxide film.

Further, an n ^{+ type} diffusion layer 19 in which n type impurities are diffused at a high concentration is formed in the P region 16 on both sides of the N channel layer under each of the gate electrodes 14 and 15, and the drain region is formed. And the source region is configured. Further, in the N region 18 on both sides of the P channel layer under each of the gate electrodes 12 and 13, a p ^{+ type} diffusion layer 20 in which p type impurities are diffused at a high concentration is formed. The drain region and the source region are configured similarly to the above. Two substrate contacts (well contacts) 21 are formed in each of the P region 16 and the N region 18 in the central portion and the peripheral portion. The P region 16 and the N region 18 are surrounded and separated by a field oxide film 22.

With the above structure, each N region 18 facing each other
In this region, two P-channel type MOSFETs composed of the gate electrodes 12a and 12b and two P-channel type MOSFETs composed of the gate electrodes 13a and 13b are formed. The gate electrode 14 is formed in each of the P regions 16 facing each other.
Two N-channel type MOSFE composed of a and b
Two N-channel MOSFETs each including T and the gate electrodes 15a and 15b are formed.

Therefore, according to the basic cell shown in FIG. 1, for example, two P-channel type MOSFETs and two N-channel type MOSFETs on one side of one basic cell are used.
Can be used to configure the two-input NOR gate shown in FIG. That is, the drain / source circuits of the two P-channel MOSFETs Q _12a and Q _12b composed of the gate electrodes 12a and _12b are connected in series, and the two N-channel MOSFET Q composed of the gate electrodes 14a and 14b are connected. _14a , Q _14b
The respective drain / source circuits of are connected in parallel to the FETs Q _12a and Q _12b . Then, the gate electrode _12a of the FET Q _{12a and} the gate electrode _14a of the FET Q 14a are connected to each other, and the gate electrode 12b and the FET Q of the FET Q _12b are connected.
_A 2-input NOR gate is formed by connecting the gate electrode 14b of 14b.

Also, two P-channel MOSFETs and two N-channel MOSs on one side of one basic cell are provided.
It is also possible to use a FET to form the two-input NAND gate shown in FIG. 2B.
That is, two P-channel type MOSFETs Q _12a and Q
The drain / source circuits of _12b are connected in parallel, and the drain / source circuits of the two N-channel MOSFETs Q _14a and Q _14b are connected in series to the parallel circuit of FETs Q _12a and Q _12b . Then, a gate electrode connected 14a of the gate electrode 12a and the FETQ _14a of FETQ _12a, FETQ _12b gate electrode 12b and FETQ of
_A 2-input NAND gate is formed by connecting the gate electrode 14b of 14b.

FIG. 3A shows a structural example of a basic cell obtained by modifying the basic cell of the first embodiment shown in FIG.
It should be noted that the same or corresponding parts as those in FIG. In this basic cell 11b, one broken line-shaped gate electrode 1 is provided in each divided region.
2a to 15a are formed, and the number of gate electrodes is reduced. According to such a basic cell 11b, it is possible to configure, for example, the inverter gate shown in FIG. 3B with one half of one basic cell. That is, one P-channel type MO composed of the gate electrode 12a
1 composed of SFET Q _12a and gate electrode 14a
Each N-channel MOSFET Q _14a and each drain
An inverter gate is formed by connecting source circuits in series and connecting the respective gate electrodes 12a and 14a.

FIG. 4A shows a structural example of another basic cell obtained by modifying the basic cell of the first embodiment shown in FIG. It should be noted that the same or corresponding parts as those in FIG. This basic cell 11c
In each of the divided regions, three broken line gate electrodes 12a, b, c to 15a, b, c are formed.
The number of gate electrodes is increasing. Such a basic cell 11
As shown in FIG.
It is possible to configure the 3-input NOR gate shown in (b). That is, the three P-channel MOSFETs Q _12a , Q _12a , Q _12a , Q
_12b, connects each drain-source circuit of the Q _12C in series, the gate electrode 14a, b, composed of c 3 N-
Channel type MOSFETQ _14a, Q _14b, connecting the respective drain-source circuit of the _{Q 14c FETQ 12a, Q 12 b} , in parallel to the Q _12C. Then, by connecting the gate electrodes 12a and 14a, the gate electrodes 12b and 14b, and the gate electrodes 12c and 14c, respectively,
A 3-input NOR gate is constructed.

According to the above basic cell 11c, 1
3 input NA shown in FIG. 4 (c) in one half of the basic cell
It is also possible to configure an ND gate. That is, the drains of the three P-channel MOSFETs Q _12a , Q _12b , and Q _12C composed of the gate electrodes 12a, _12b , and _12c are formed.
The source circuits are connected in parallel, and the gate electrodes 14a, b, c
3 N-channel MOSFETs
Q _14a, Q _14b, each of the drain-source circuit of Q _14c F
ETQ _12a , Q _12b , and Q _12C are connected in series to a parallel circuit. Then, each gate electrode 12a and 14a,
3-input NOR by connecting the gate electrodes 12b and 14b and the gate electrodes 12c and 14c, respectively
The gate is constructed.

Although the above example of the configuration of the basic cell 11c has been described with respect to a 3-input NOR gate and a NAND gate, it is also possible to configure a 2-input NOR gate and a NAND gate.

Further, in the basic cell of the first embodiment shown in FIG. 1, the number of gate electrodes formed in each divided region may be four or more. In general, if the number of gate electrodes in one basic cell is large, F that can be used when forming a logic block
Since the number of ETs increases, the SOG LSI is highly integrated, and the circuit design becomes easy. For example, as shown in FIG. 4 (a), if there are three FETs per divided region,
The half of one side of the basic cell can form the three-input NOR gate and the three-input NAND gate shown in FIGS. That is, when the logic gate is formed in units of basic cells, the FETs formed in each divided region
If the number is large, the number of FETs that can be connected in series or in parallel increases, and higher integration can be achieved, which is advantageous compared with the case where only one FET or two FETs are formed per divided region. Become.

In the above description of each basic cell,
The case where the gate widths (lengths of the gate electrodes) of the transistors formed in the divided regions are different has been described, but the gate widths may be the same.

The above basic cells 11a, 11b, 11c
Are arranged on the master slice as indicated by reference numeral 11 in FIG. In the figure, the shaded portion 23 indicates the N region 18 in which the P-channel MOSFET is formed, and the blank portion 24 indicates the P region 16 in which the N-channel MOSFET is formed. That is, one basic cell 11a or 11b or 11c is configured by the dotted line portion 11 in the figure, and the basic cell array structure is a structure in which a plurality of basic cells 11 are arranged adjacent to each other. .

The basic cells 11a, 11b, and
In 11c, the four divided regions were composed of mutually different channels between the adjacent regions. However, all four divided regions may be configured by the same channel. In this case, each of these basic cells 11a, 11b, 11c
Are arranged on the master slice as shown in FIG. That is, the basic cells 11P in which all of the four-division regions are formed in the P channel type and the basic cells 11N in which all of the four-division regions are formed in the N channel type are alternately arranged adjacent to each other. In this way, when the four divided regions are formed in the same channel type, if two FETs are formed in each divided region, it is possible to use up to eight FETs in one basic cell. Therefore, by using one N-channel type basic cell 11N and one P-channel type basic cell 11P adjacent thereto, an 8-input NAN
It is possible to equivalently configure the D gate and the 8-input NOR gate in the vertical and horizontal directions of the master slice.

According to the first embodiment as described above, the gate cells of the gate electrode pairs 12 to 15 are arranged in the gate width direction in the basic cells 11a, 11b,
By taking along the direction surrounding the center point of c, it becomes possible to assemble the basic cells 11 vertically and horizontally symmetrically on the master slice. Moreover, by arranging a plurality of the basic cells 11 adjacent to each other, it becomes possible for logic cells such as NAND gates and flip-flops to form circuits that are completely equivalent in the vertical and horizontal directions of the master slice. Become. Therefore, according to this embodiment, each transistor on the master slice can be effectively used, and the degree of integration of elements in the SOG type LSI is improved. Further, the degree of freedom in wiring pattern design is increased, and an SOG type LSI corresponding to a required function can be developed in a short period of time.

Further, it is possible to form the substrate contact (well contact) 21 in the vicinity of the diffusion layer 19 (diffusion layer 20), and there is an advantage that latch-up hardly occurs in the realized MOSFET. Further, since the diffusion layers outside each of the gate electrodes 12 to 15 have a large area and can have a larger number of contacts, the source resistance is reduced by using these diffusion layers in the source region, and the operating speed of the MOSFET is reduced. Will be faster.

FIGS. 7 and 8 show the structures of basic cells according to the second and third embodiments of the present invention.
The same or corresponding parts as those in (a) are designated by the same reference numerals and the description thereof will be omitted.

These embodiments differ from the first embodiment only in the shape of the gate electrode, and the other structures are substantially the same as the first embodiment. That is, in the second embodiment of FIG. 7, the gate width direction of the gate electrodes 31 to 34 is taken along the direction surrounding the center point of the basic cell 35, but the shape is circular (each divided region). The inside is arcuate). On the other hand, in the first embodiment, it is formed in a polygonal shape (a polygonal line shape in each divided area). Further, in the basic cell 45 according to the third embodiment of FIG. 8, the gate electrodes 41 to 44 are formed in a quadrangular shape (a straight shape in each divided region). In addition, the gate electrodes 31 to 34 and 41 to 4 in each example.
Reference numeral 4 has a shape divided into four regions by vertical and horizontal lines passing through the center point, which is the same as in the above-described first embodiment. Also in each of these embodiments, it goes without saying that the number of gate electrodes can be an arbitrary number. The arrangement structure of the basic cells 35 and 45 in each embodiment is shown in the same manner as in FIG. 5 or FIG.

Also in these second and third embodiments, the same effect as in the first embodiment can be obtained. That is, the basic cells 35 and 45 can be assembled vertically and horizontally symmetrically on the master slice, and the logical cells can be configured to be completely equivalent vertically and horizontally.

FIG. 9 is a diagram showing the structure of a basic cell according to the fourth embodiment of the present invention. The same or corresponding parts as in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

This fourth embodiment is a modification of the above-mentioned third embodiment in which the gate electrode is formed in a linear shape.
Each of the linear gate electrodes divided into regions is divided into two regions.
A plurality of symmetrically formed center lines in the gate width direction are formed. That is, the gate electrode 43a and the gate electrode 4
3d, and the gate electrode 43b and the gate electrode 43c are formed symmetrically with respect to the center line AA. In the other three divided regions as well, similarly, a plurality of gate electrodes are formed symmetrically with respect to the center line in the gate width direction that divides each region into two. Therefore, the fourth embodiment is the third
The structure is such that a gate electrode is additionally formed in the embodiment.

According to the fourth embodiment as described above, it is possible to assemble the basic cells 46 on the master slice shown in FIG. 10 not only in the vertical and horizontal directions but also in the oblique directions. That is, the logic block 51 corresponds to the basic cell 46, and the gate electrodes 41 to 44 are formed in each divided region. The logic block 52 is obtained by moving the logic block 51 in an oblique direction of the master slice, and the divided region formed by the gate electrodes 44a to 44d can be shared by the logic blocks 51 and 52. This is because the gate electrodes formed in each divided region are formed symmetrically in the oblique direction. As a result, the logical blocks 51 and 52 that are diagonally adjacent to each other when arrayed can share the same divided area, and as a result, the same logical blocks 51 and 52 can be configured not only in the vertical and horizontal directions but also in the diagonal direction. It is possible to reduce the unused cell area. Further, it becomes possible to efficiently design the circuit.

On the other hand, when the logic block is formed in the diagonal direction by using the basic cell 45 according to the third embodiment, it is necessary to completely shift the basic cell by one. That is, the logical block 61 shown in FIG.
It corresponds to the basic cell 45 shown in FIG. To configure the same logical block as the logical block 61 in a diagonal direction,
Similarly to the above, when the block frame is moved by one division area, the respective logic blocks can be configured equivalently in terms of circuit configuration. However, the arrangement of the gate electrodes in each divided region in the block frame that is moved diagonally is different, and it is necessary to greatly change the wiring pattern shape. Therefore, the logic block 61 must be completely shifted by one basic cell to form the logic block 62.

[0037]

As described above, according to the present invention, a gate width direction of a gate electrode is taken along a direction surrounding a certain point as a center, so that it is vertically and horizontally symmetrical on a master slice. It becomes possible to form a basic cell.
Therefore, each transistor on the master slice can be effectively used, and the space on the semiconductor chip is not wasted.

Further, by forming a plurality of gate electrodes symmetrically with respect to the center line in the gate width direction that divides each region into two, it is possible to assemble basic cells not only in the vertical and horizontal directions but also in the diagonal direction on the master slice. become. Therefore, each transistor on the master slice can be used more effectively, and the circuit design becomes easy.

Further, by arranging the basic cells adjacent to each other such that the channel layer under one of the facing gate electrodes is a P channel and the channel layer under the other gate electrode is an N channel, By arranging a plurality of basic cells in which the channel layers under the gate electrode are all P-channel and all N-channel are alternately arranged adjacent to each other, a completely equivalent circuit configuration is formed in each direction. It will be possible. Therefore, when the logic cell is realized on the semiconductor chip, if the logic cell can be realized on the utilization area, the logic cell can be formed without limitation in shape.

As a result, high integration of elements in the SOG type LSI is achieved, and the degree of freedom in wiring pattern design is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a basic cell according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a gate constituted by one half of the basic cell of the first embodiment in which two FETs are formed in each divided region.

FIG. 3 is a diagram showing a structure of a basic cell in which one FET is formed in each divided region by modifying the first embodiment, and a gate constituted by one half of the basic cell.

FIG. 4 is a diagram showing a structure of a basic cell in which three FETs are formed in each divided region by modifying the first embodiment, and a gate formed by one half of the basic cell.

FIG. 5 is a plan view showing an example of an array structure of basic cells according to the first embodiment and its modification.

FIG. 6 is a plan view showing an example of an array structure of basic cells in which each divided region has the same channel.

FIG. 7 is a plan view showing a structure of a basic cell according to a second embodiment of the present invention.

FIG. 8 is a plan view showing the structure of a basic cell according to a third embodiment of the present invention.

FIG. 9 is a plan view showing the structure of a basic cell according to a fourth embodiment of the present invention.

FIG. 10 is a plan view showing an example of an array structure of basic cells according to a fourth embodiment.

FIG. 11 is a plan view showing an example of an array structure of basic cells according to a third embodiment.

FIG. 12 is a plan view showing a structure of a conventional basic cell.

FIG. 13 is a plan view showing a conventional basic cell array structure.

[Explanation of symbols]

11a ... Basic cell 12-15 ... Gate electrode 16 ... P region 17 ... Oxide 18 ... N region 19 ... N ^{+ type} diffusion layer 20 ... P ^{+ type} diffusion layer 21 ... Substrate contact (well contact) 22 ... Field oxide film

Claims (5)

[Claims] 1. A gate electrode having a gate width direction centered on a certain point along a direction surrounding the point, and divided into four regions by two straight lines passing through this point and intersecting each other at right angles, and each of these gates. A basic cell comprising a drain region and a source region formed on both sides of a channel layer below an electrode. 2. The basic cell according to claim 1, wherein a plurality of gate electrodes divided into four regions are formed symmetrically with respect to a center line in the gate width direction that divides each region into two. 3. Of the gate electrodes divided into four regions, a channel layer under each one of the facing gate electrodes is formed as a P channel, and a channel layer under each of the other opposite gate electrodes is formed as an N channel. An array structure of basic cells, wherein a plurality of basic cells according to claim 1 or 2 are formed adjacent to each other. 4. The basic cell according to claim 1, wherein all the channel layers under each gate electrode divided into 4 regions are formed as P-channels, and all the channel layers under each gate electrode divided into 4 regions are all formed. The basic cell array structure according to claim 1, wherein a plurality of the basic cells according to claim 1 formed in an N channel are alternately and adjacently arranged. 5. The basic cell according to claim 2, wherein all the channel layers under each gate electrode divided into 4 regions are formed as P-channels, and all the channel layers under each gate electrode divided into 4 regions are all formed. The basic cell array structure according to claim 2, wherein a plurality of the basic cells according to claim 2 formed in an N channel are alternately and adjacently arranged.