JPH0748485B2 - Etching method - Google Patents

Description

The present invention relates to a method for etching an insulating film of a semiconductor device, for example, a method for selectively etching a low temperature silicon oxide film for interlayer insulation.

The present invention is applied to, for example, formation of contact holes in integrated circuit devices.

[Prior Art] A silicon oxide film (abbreviated as a low temperature oxide film or a low temperature silicon oxide film) deposited at a relatively low temperature by a CVD technique is well known. Since the low-temperature silicon oxide film is generally doped with phosphorus or boron, it is also called a doped oxide film, and includes a phosphorus-doped PSG film, a boron-doped BSG film, a BPSG film doped with both.

A contact hole is opened in the above-mentioned doped oxide film generally used for interlayer insulation by a photolithography technique.

[Problems to be Solved by the Invention] Since the doped oxide film is relatively thick, an anisotropic dry etching technique is used to accurately form fine contact holes.

Since the side wall of the contact hole opened by the anisotropic dry etching is formed vertically, it is known that the electrode wiring to be deposited later is likely to be broken due to step breakage.

Further, it is also known that the surface resistance of the base electrode region is roughened by dry etching, resulting in an increase in contact resistance.

In order to improve the above drawbacks, a technique is known in which a contact hole is anisotropically dry-etched and then wet-etched. According to this two-step technique, the etching accuracy can be maintained to some extent and the above-mentioned drawbacks can be improved.

5 to 7 are process diagrams showing the above-mentioned conventional technique.

First, the resist mask 1 is exposed and then selectively etched to form an opening (FIG. 5).

Next, anisotropic dry etching is performed using the resist 1 as a mask to open the BPSG film 2 partway (FIG. 6).

At this time, the side wall polymer 4 formed by the anisotropic dry etching may adhere.

When the next wet etching is performed with the sidewall polymer attached, the intermediate portion of the sidewall polymer 4 may remain as shown in FIG. 7.

Therefore, when the middle portion of the side wall 5 remains due to poor etching, there is a drawback that the step breakage of the embedded electrode wiring is not improved despite the wet etching, which is rather worse.

However, as the degree of integration increases, the number of contact holes formed in the doped oxide film (interlayer insulating film) on the chip is increasing remarkably, and the opening area allowed for each contact hole is shrinking more and more. is there. It is also well known that the reduction of the opening area increases the number of step breaks in the electrode wiring to be deposited later.

The present invention aims to remedy the above problems. Therefore, a specific object of the present invention is to develop an etching method for an insulating film, which can reduce step difference and can be miniaturized.

[Means and Actions for Solving Problems] The basic configuration of the present invention is that a resist mask provided on an insulating film is opened by photolithography and the exposed insulating film is anisotropically dry-etched. Then, the side wall polymer adhering to the side surface of the insulating film facing the opening is removed by oxygen ashing, and the insulating film after the oxygen ashing is wet-etched before removing the resist mask. The etching method is as follows.

The main constituent features of the present invention will be described below.

The insulating film is, for example, a doped oxide film doped with phosphorus or boron, and is generally formed by a low temperature CVD method.

The anisotropic dry etching technique is a technique for selectively dry etching in the vertical direction, and includes a reactive sputter etching method, a reactive ion etching method, and the like.

The technique for removing the sidewall polymer is known as oxygen ashing. Here, the sidewall polymer attached to the sidewall of the insulating film facing the contact hole is removed by oxygen plasma gas in the anisotropic dry etching process. Means technology. Although the surface of the resist mask is etched and thinned by this oxygen ashing, the thickness of the adhered side wall polymer is small, and the resist mask is removed during the removal of the side wall polymer to expose the flat surface of the insulating film. There is nothing to do.

The wet etching technique is a technique of dissolving the low temperature oxide film with an etching solution.

A specific feature of the present invention is that the exposed surface of the insulating film that has been anisotropically dry-etched is oxygen-ashed before the wet-etching step so that wet-etching that is performed later can be performed well. .

[Embodiment] FIGS. 1 to 4 are process diagrams showing a preferable embodiment of the present invention.

In FIGS. 1 to 4, the resist 1 is a positive resist and the film thickness is about 1.1 μm. The low temperature silicon oxide film 2 is BPSG deposited by the low temperature CVD method, its phosphorus concentration is ₂ to 8 P ₂ O ₅ wt%, and its boron concentration is 0 to
5B ₂ O ₃ wt%. The BPSG film thickness is 0.5 μm.

In step a in FIG. 1, the mask is opened by a normal photolithography technique.

In step b of FIG. 2, the etching apparatus is a batch type reactive ion etching apparatus (DEM-451 type). The etching gas is CF ₄ + H ₂ , and the flow rate ratio of CF ₄ and H ₂ is CF
₄ / H ₂ = 1 to 10. The pressure is 3 to 10 atmospheres, and the applied high frequency power is 100 to 300W. By the reactive ion etching, the upper part of the contact hole 6 is dug into a part of the BPSG film 2.

It is known that in the anisotropic dry etching process, the sidewall polymer 4 is attached to the sidewall surface of the dug contact hole.

In step C of FIG. 3, the side wall polymer is ashed by oxygen ashing.

This step is commonly referred to as the ash removal process and is performed using a cylindrical asher. The gas used is oxygen gas, the pressure is 0.6 to 1.0 torr, and the applied high frequency power is 100 to 1 KW.

In step d of FIG. 4, the partially etched contact hole 6 is wet etched. The etching solution is a general HF-NH ₄ F aqueous solution. As a result, as shown in step d, it is possible to form a contact hole having a smoother step.

[Second Embodiment] An embodiment in which the anisotropic dry etching conditions are changed as follows will be described below. The etching equipment is a branch leaf type RIE equipment, etching gas; C ₂ F ₆ + CHF ₃ , gas flow ratio;
C ₂ F ₆ / CHF ₃ = 1 to 5, pressure 0.1 to 0.5 torr, high frequency power 10
It is 0 to 400W.

[Effect] As can be understood from the above description, the selective etching method for an insulating film such as a doped oxide film according to the present invention can form a fine contact hole that is hard to cut a step,
There are great advantages in large scale integrated circuits.

Further, according to the present invention, the roughness of the bottom surface of the contact hole which is anisotropically etched is reduced in the above wet etching process, so that there is an advantage that the contact resistance is further reduced.

Still another advantage of the present invention is that the addition of the descum step C deteriorates the adhesion between the resist 1 and the BPSG film 2. As a result, in the next wet etching step, wet etching progresses further at the interface between the resist film 1 and the BPSG film, and a taper (chamfer) is formed on the upper side wall of the contact hole as shown in step d of FIG. I can do things. Therefore, the step coverage (coverability of the step) in the next electrode wiring process is significantly improved.

Therefore, according to the etching method of the present invention, it is possible to achieve both miniaturization of contact holes and prevention of step breakage.

[Brief description of drawings]

FIG. 1, FIG. 2, FIG. 3, and FIG. 4 are process diagrams of one embodiment of the present invention. FIGS. 5, 6, and 7 are process diagrams showing the prior art. 1 ... Resist mask 2 ... Low temperature silicon oxide film

Claims (2)

[Claims] 1. A resist mask provided on an insulating film is opened by a photolithography technique, the exposed insulating film is anisotropically dry-etched to open the side surface of the insulating film facing the opening. An etching method characterized in that the adhered side wall polymer is removed by oxygen ashing, and the insulating film after the oxygen ashing is wet-etched before the removal of the resist mask. 2. The etching method according to claim 1, wherein the insulating film is a low temperature silicon oxide film selected from the group consisting of a BPSG film, a PSG film and a BSG film.