JPH0746888B2 - Control device for voltage fluctuation compensator - Google Patents

Control device for voltage fluctuation compensator

Info

Publication number
JPH0746888B2
JPH0746888B2 JP62117996A JP11799687A JPH0746888B2 JP H0746888 B2 JPH0746888 B2 JP H0746888B2 JP 62117996 A JP62117996 A JP 62117996A JP 11799687 A JP11799687 A JP 11799687A JP H0746888 B2 JPH0746888 B2 JP H0746888B2
Authority
JP
Japan
Prior art keywords
voltage
controller
comparator
output
voltage fluctuation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62117996A
Other languages
Japanese (ja)
Other versions
JPS63283429A (en
Inventor
英機 山村
里志 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP62117996A priority Critical patent/JPH0746888B2/en
Publication of JPS63283429A publication Critical patent/JPS63283429A/en
Publication of JPH0746888B2 publication Critical patent/JPH0746888B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/30Reactive power compensation

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  • Supply And Distribution Of Alternating Current (AREA)
  • Control Of Electrical Variables (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、定電圧制御方式の電圧変動補償装置の制御装
置に関するものである。
The present invention relates to a control device for a voltage fluctuation compensating device of a constant voltage control system.

[従来技術と問題点] 例えば、アーク炉のような変動負荷のある母線の電圧変
動を定電圧補償するため第2図に示すような制御装置が
採られる。図は一相分について示す。電源母線1にアー
ク炉のような変動負荷11が接続される。これに対して、
母線1にリアクトル、又は図に示すような高インピーダ
ンス変圧器12と逆並列接続サイリスタスイッチ10が直列
に接続され、これと並列にコンデンサ、リアクトルより
なるフィルタ13が配置され、これにより、サイリスタ無
効電力補償回路(TQC)が構成され、前記サイリスタス
イッチ10の制御極への位相制御点弧パルスの付与によっ
て高インピーダンス変圧器12への通電制御を行って、無
効電力を発生し、前記変動負荷11による電圧変動を補償
するようにしている。このように電圧変動を補償するた
め、母線1の電圧変動を検出するΔV検出回路が接続さ
れる。4はΔV検出回路を示し、PT2の2次側に電圧検
出器41が接続され、その出力側は、ローパスフィルタ42
を介し、及び直接に比較器43を介し、出力した差電圧は
PI調節器44を介して、その出力ΔVは加算器7に入力す
る。変動負荷11によって生じる電流は、CT3より定常値
設定器5(例えば50%)を介して加算器7に入力する。
パルス発生回路8には、前記加算器7よりの出力の同期
検出器6よりのタイミング信号が入力し、ここでサイリ
スタ10の点弧位相制御パルスが作られ、パルスアンプ9
を介してサイリスタ10の点弧制御を行い、母線の定電圧
制御を行うことになる。
[Prior Art and Problems] For example, a control device as shown in FIG. 2 is adopted in order to perform constant voltage compensation for a voltage fluctuation of a bus bar having a fluctuating load such as an arc furnace. The figure shows one phase. A variable load 11 such as an arc furnace is connected to the power bus 1. On the contrary,
A reactor, or a high-impedance transformer 12 and an antiparallel connection thyristor switch 10 as shown in the figure are connected in series to the bus bar 1, and a filter 13 composed of a capacitor and a reactor is arranged in parallel with the reactor 13. Compensation circuit (TQC) is configured to control the energization of the high impedance transformer 12 by applying a phase control ignition pulse to the control pole of the thyristor switch 10 to generate reactive power, which is generated by the variable load 11. The voltage fluctuation is compensated. In this way, in order to compensate the voltage fluctuation, a ΔV detection circuit for detecting the voltage fluctuation of the bus bar 1 is connected. Reference numeral 4 denotes a ΔV detection circuit, a voltage detector 41 is connected to the secondary side of PT2, and its output side has a low-pass filter 42.
, And directly through the comparator 43, the difference voltage output is
The output ΔV is input to the adder 7 via the PI controller 44. The current generated by the fluctuating load 11 is input from the CT3 to the adder 7 via the steady value setting device 5 (for example, 50%).
The timing signal from the synchronous detector 6 which is the output from the adder 7 is input to the pulse generation circuit 8, where the firing phase control pulse of the thyristor 10 is generated, and the pulse amplifier 9
The firing control of the thyristor 10 is performed via the control circuit to control the constant voltage of the busbar.

このΔV検出回路4はクローズドループになっているの
で絶えず主制御による制御エラーを修正していることに
なる。
Since this ΔV detection circuit 4 is in a closed loop, it means that the control error due to the main control is constantly corrected.

今母線電圧の1%の電圧補償を考える。定常偏差:ε,
ループゲイン:GL,ループ時定数:τとする。
Now consider voltage compensation of 1% of the bus voltage. Stationary deviation: ε,
Loop gain: G L , loop time constant: τ L.

但し、ΔVin:電圧入力変化分、ΔVo:サイリスタ制御信
号変化分による無効電力変化分、Ko:ΔV検出回路のゲ
イン、To:同回路の時定数。
However, ΔVin: change in voltage input, ΔVo: change in reactive power due to change in thyristor control signal, Ko: gain of ΔV detection circuit, To: time constant of the same circuit.

ここで、具体的な設備を考える。Here, consider concrete equipment.

条件ε=5%,Vin=10V×1%=0.1V,ΔVo=10V,τ
50mS,GL=20(倍)とする。
Condition ε = 5%, Vin = 10V × 1% = 0.1V, ΔVo = 10V, τ L =
50mS, G L = 20 (times).

(1)式から (2)式から To=τ・GL=0.05×20=1(S) 以上から、第2図調節計44は高ゲインとなり、初期設定
の調整、アンプの温度ドリフト等が顕著に影響するの
で、高級な部品の使用が必要となるばかりか、安定動作
の制御装置は期待できない。例えば第2図のPI調節計44
に使用の演算増幅器(以下OPアンプと略)の零オフセッ
ト(VOF)を約2mVとすると、PI調節計44の出力ΔVは、 ΔV=VOF×K1=0.002v×2000=4V これに対し通常のOPアンプのリニア領域は±10Vである
ので、 ε=4/10=40(%)エラーとなり、バイアス調整が必要
となる。
From equation (1) From equation (2), To = τ L · G L = 0.05 × 20 = 1 (S) From the above, the controller 44 in FIG. 2 has a high gain, and the adjustment of the initial setting, the temperature drift of the amplifier, etc. significantly affect. Therefore, not only the use of high-grade parts is required, but also a stable operation control device cannot be expected. For example, PI controller 44 in Fig. 2
Assuming that the zero offset (V OF ) of the operational amplifier (hereinafter abbreviated as OP amplifier) used for is about 2 mV, the output ΔV of PI controller 44 is ΔV = V OF × K 1 = 0.002v × 2000 = 4V On the other hand, the linear region of a normal OP amplifier is ± 10V, so ε = 4/10 = 40 (%) error occurs, and bias adjustment is required.

これは運転初期に問題となり、現場で微調整するが、数
mVの調整はなかなか困難である。
This becomes a problem in the early stage of operation, and fine adjustment is performed on site, but
Adjustment of mV is quite difficult.

[問題を解決するための手段] 本発明は電圧系統等の数%の電圧変動を抑制する場合、
従来方式であるとPI調節計のオープンゲインが1000倍以
上となり、特に運転初期のオフセット調整が困難となる
のを解決する目的でなされたものである。定電圧制御方
式の電圧変動補償装置において、電圧変動変化分をPI制
御系の前段で検出し、増幅することにより、PI制御がマ
イナーループ構成でできるように構成したものである。
[Means for Solving the Problem] In the present invention, when suppressing voltage fluctuation of several% in a voltage system,
With the conventional method, the open gain of the PI controller becomes 1000 times or more, and it was made for the purpose of solving the difficulty in offset adjustment especially at the initial stage of operation. In the voltage fluctuation compensator of the constant voltage control system, the PI fluctuation can be detected in the preceding stage of the PI control system and amplified, so that PI control can be performed in a minor loop configuration.

第1図に本発明の制御系を示す。第2図と同一部分は同
一符号で示す。図において点線で囲む部分がΔV検出回
路である。
FIG. 1 shows the control system of the present invention. The same parts as those in FIG. In the figure, the portion surrounded by the dotted line is the ΔV detection circuit.

母線1にPT2が結合され、その出力側はV検出器41に接
続され、その出力ΔVinは第1の比較器43に入力する。
一方比較器43には規定電圧設定器45によりVSが入力し、
比較器43の出力は係数器46を介して比較器43′に入力
し、比較器43′の出力側はPI調節計47に接続され、PI調
節計47の出力側は分圧器48及び加算器7に接続される。
PT2 is coupled to the bus 1, its output side is connected to the V detector 41, and its output ΔVin is input to the first comparator 43.
On the other hand, V S is input to the comparator 43 by the specified voltage setting device 45,
The output of the comparator 43 is input to the comparator 43 ′ via the coefficient unit 46, the output side of the comparator 43 ′ is connected to the PI controller 47, and the output side of the PI controller 47 is the voltage divider 48 and the adder. Connected to 7.

分圧器48の出力側は完全積分器49に接続され、完全積分
器49を介して、その出力はVrefとして第2の比較器43′
に入力する。
The output side of the voltage divider 48 is connected to a perfect integrator 49, whose output is V ref via the second comparator 43 '.
To enter.

一方、PI調節計47の出力ΔVは加算器7において定常値
設定器(50%)50よりのV50と加算され、サイリスタパ
ルス発生回路8に入力する。なお、サイリスタパルス発
生回路8には、PT2に接続されている同期検出器6より
同期信号が入力する。
On the other hand, the output ΔV of the PI controller 47 is added to V 50 from the steady value setting device (50%) 50 in the adder 7 and input to the thyristor pulse generation circuit 8. The thyristor pulse generating circuit 8 receives a sync signal from the sync detector 6 connected to PT2.

上記構成においては、第2図の従来のΔV検出回路と相
違して、基本的には、まず規定電圧VSにより変化分を先
に検出して、この信号を係数倍したものをPI調節計47,
分圧器48,完全積分器49,比較器43′よりなるマイナール
ープ制御することにより調節計47のゲインを低減し、安
定な電圧フィードバック制御構成となすものである。
In the above configuration, unlike the conventional ΔV detection circuit of FIG. 2, basically, the change amount is first detected by the specified voltage V S , and this signal is multiplied by a coefficient to obtain a PI controller. 47,
The gain of the controller 47 is reduced by performing minor loop control including the voltage divider 48, the perfect integrator 49, and the comparator 43 ', and a stable voltage feedback control configuration is formed.

具体的は設備を考える。但し設備はさきに説明した設備
と同等仕様とし、GL=20(倍)、ε=5%、τ=50ms
とする。
Specifically, consider the equipment. However, the equipment has the same specifications as the equipment described above, G L = 20 (times), ε = 5%, τ L = 50 ms
And

又、規定電圧VSを100%値とし、係数器46の係数(−K
2)=20(倍)とする。
The specified voltage V S is set to 100% and the coefficient (-K
2 ) = 20 (times).

第2図K1の第1図K2,K3の関係は、 K1=K2・K3であるから、K1=2000(倍)から、K3=100
(倍)でよい。又、T3=To=1(S)とすると、 前記(1)式より (2)式よりτ=T3/GL=50ms 以上から、K3=100(倍)であるので、運転初期設定及
び高級部品使用の必要はない。オフセットの影響は従来
の1/20になると考えてよい。
The second first relationship Fig K 2, K 3 of FIG K 1, since a K 1 = K 2 · K 3, from K 1 = 2000 (times), K 3 = 100
(Double) is fine. Further, if T 3 = T o = 1 (S), then from the above equation (1) From equation (2), since τ L = T 3 / G L = 50 ms or more, and K 3 = 100 (times), there is no need to perform initial setting of operation and use of high-grade parts. It can be considered that the influence of the offset will be 1/20 of the conventional one.

又、分圧器48及び完全積分器49はVrefを形成しており時
定数τは、 τ=T4/K3 …(3) 但しn=1/K3(nは分圧比) 同様に制御系の零オフセットを考察する。
Further, the voltage divider 48 and the perfect integrator 49 form V ref , and the time constant τ 4 is τ 4 = T 4 / K 3 (3) where n = 1 / K 3 (n is a voltage division ratio) Consider the zero offset of the control system.

K2=20(倍)であるので、係数器46の零オフセットΔVK
は、 ΔVK=2mV×20(倍)=40mV 次段PI調節計47の出力ΔV′は、PI調節計47のOPアンプ
の零オフセット電圧をΔVKOF=2mVとすれば、 ΔV=K3(ΔVK+ΔVKOF) =100×(40mV+2mV)=4.2V 分圧器48,完全積分器49でVrefを作ってフィードバック
をかけることにより、完全積分器49の出力は4.2Vとな
り、PI調節器47の出力は ΔV=ΔV′+Vref=4.2+4.2=0(V) となる。即ち、制御系のオフセットはマイナーループで
除去出来る。
Since K 2 = 20 (times), the zero offset ΔV K of the coefficient unit 46
Is ΔV K = 2 mV × 20 (times) = 40 mV The output ΔV ′ of the next stage PI controller 47 is ΔV = K 3 (if the zero offset voltage of the OP amplifier of PI controller 47 is ΔV KOF = 2 mV). ΔV K + ΔV KOF ) = 100 × (40mV + 2mV) = 4.2V By making V ref with the voltage divider 48 and the perfect integrator 49 and applying the feedback, the output of the perfect integrator 49 becomes 4.2V, and the PI controller 47 outputs The output is ΔV = ΔV ′ + V ref = 4.2 + 4.2 = 0 (V). That is, the offset of the control system can be removed by the minor loop.

[発明の効果] (1)本発明ではPI制御系の前段で電圧変化分を検出、
増幅することにより、PI制御がマイナーループ構成でよ
く、電圧変化分を精度よく制御することができる。
[Effects of the Invention] (1) In the present invention, the voltage change is detected in the preceding stage of the PI control system,
By amplifying, the PI control may have a minor loop configuration, and the voltage change amount can be accurately controlled.

(2)PI制御系のゲイン見掛上低減でき、安定な制御構
成となる。
(2) The gain of the PI control system can be apparently reduced, resulting in a stable control configuration.

(3)OPアンプの零オフセットが無視でき、調整不用且
つ安定な制御回路が期待出来る。
(3) The zero offset of the OP amplifier can be ignored, and a stable control circuit that does not require adjustment can be expected.

【図面の簡単な説明】[Brief description of drawings]

第1図は、本発明の電圧変動抑制装置の制御回路を示
す。 第2図は、電圧変動装置の従来の制御回路を示す。 41……電圧検出器、42……ローパスフィルタ、43,43′
……比較器、44,47……PI調節計、45……規定電圧、46
……係数器、48……分圧器、49……完全積分器、50…
…定常値設定器(50%)。
FIG. 1 shows a control circuit of the voltage fluctuation suppressing device of the present invention. FIG. 2 shows a conventional control circuit of the voltage fluctuation device. 41 …… Voltage detector, 42 …… Low pass filter, 43,43 ′
…… Comparator, 44,47 …… PI controller, 45 …… Specified voltage, 46
…… Coefficient unit, 48 …… Voltage divider, 49 …… Complete integrator, 50…
… Steady value setter (50%).

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】変動負荷を接続した母線の電圧変動をΔV
検出回路で検出して無効電力補償回路のサイリスタを制
御する電圧変動補償装置の制御装置において、前記ΔV
検出回路が、母線にPTを介して接続されたV検出器と、
このV検出器の出力と規定電圧設定器の規定電圧が入力
され、両者を比較して電圧変動変化分を出力する第1比
較器と、該比較器の出力を入力して係数倍する−係数器
と、該−係数器の係数倍出力を入力とする第2比較器
と、該比較器の出力を入力とするPI調節計と、該PI調節
計の出力側にサイリスタ制御信号線及び前記PI調節計と
分圧器と完全積分器と前記第2比較器よりなるマイナー
ループを具備したことを特徴とする電圧変動補償装置の
制御装置。
1. A voltage fluctuation of a bus bar to which a variable load is connected is ΔV.
In the control device of the voltage fluctuation compensating device for detecting the thyristor of the reactive power compensating circuit by detecting by the detecting circuit,
The detection circuit is a V detector connected to the bus through PT,
The output of this V detector and the specified voltage of the specified voltage setting device are input, and a first comparator that compares the two and outputs the voltage fluctuation change amount, and the output of the comparator are input and multiplied by a coefficient-coefficient , A second comparator that receives the coefficient-multiplied output of the coefficient multiplier, a PI controller that receives the output of the comparator, and a thyristor control signal line and the PI controller on the output side of the PI controller. A controller for a voltage fluctuation compensating device, comprising a minor loop including a controller, a voltage divider, a perfect integrator, and the second comparator.
JP62117996A 1987-05-14 1987-05-14 Control device for voltage fluctuation compensator Expired - Fee Related JPH0746888B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62117996A JPH0746888B2 (en) 1987-05-14 1987-05-14 Control device for voltage fluctuation compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62117996A JPH0746888B2 (en) 1987-05-14 1987-05-14 Control device for voltage fluctuation compensator

Publications (2)

Publication Number Publication Date
JPS63283429A JPS63283429A (en) 1988-11-21
JPH0746888B2 true JPH0746888B2 (en) 1995-05-17

Family

ID=14725457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62117996A Expired - Fee Related JPH0746888B2 (en) 1987-05-14 1987-05-14 Control device for voltage fluctuation compensator

Country Status (1)

Country Link
JP (1) JPH0746888B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101171730B1 (en) * 2012-06-05 2012-08-06 주식회사 화인 Apparatus for inputting voltage of electrophoresis style dehydrator

Also Published As

Publication number Publication date
JPS63283429A (en) 1988-11-21

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