JPH0746447A - Contour compensation circuit - Google Patents

Abstract

PURPOSE:To attain natural contour correction by obtaining an optional contour correction signal without changing a boost frequency with a small circuit scale. CONSTITUTION:A 1st filter circuit 41 generates a contour correction signal. A 2nd filter circuit 42 generates a signal with an optional width narrower than that of the contour correction signal generated by the filter circuit 41. A coring circuit 43 clips a very small level of a signal obtained by the filter circuit 42 or below to a zero level. A gate pulse generating circuit 44 generates a gate pulse being at a high level at a portion other than a zero of the signal obtained by the coring circuit 43. A gate circuit 45 controls the contour correction signal generated by the filter circuit 41 with a gate pulse generated by the gate pulse generating circuit 44 to generate the contour correction signal with a narrower width.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contour compensation circuit for improving the sharpness of a video signal.

[0002]

2. Description of the Related Art An example of the configuration of a conventional contour compensation circuit is shown in FIG.
Shown in.

In FIG. 6, reference numerals 21 and 23 denote first coefficient circuits which invert the polarity of the video signal and reduce the level to 1/2, and 22 a second coefficient circuit which outputs without changing the polarity and level of the video signal. A circuit, 24 is a first delay circuit that delays the signal obtained from the first coefficient circuit 21 by 2τ (τ = 1 / (4f), f: boost frequency), and 25 is a first delay circuit.
Signal obtained by the delay circuit 24 and the second coefficient circuit 2
A first adder circuit for adding the original signals obtained from 2;
6 is a second delay circuit that delays the signal obtained by the first adding circuit 25 by 2τ, and 27 is a second delay circuit that adds the signal obtained by the second delay circuit 26 and the signal obtained by the first coefficient circuit 23. 2 adder circuit.

FIG. 7 shows a in the contour compensation circuit of FIG.
The signal waveforms at points b, c, d, e, and f are shown.
The operation of the conventional contour compensation circuit will be described below with reference to FIG.

FIG. 7A shows an input signal waveform to the contour compensating circuit of FIG. 6. The input signal has its polarity inverted by the coefficient circuit 21 and its level is 1 as shown in FIG. 7B. / 2, and the delay circuit 2 as shown in FIG.
4 delayed by 2τ. The output signal of the delay circuit 24 and the output signal of the coefficient circuit 22 are added by the adder circuit 25 to form a signal waveform as shown in (d) of FIG. 7, and further, by the delay circuit 26 as shown in (e) of FIG. It is delayed by 2τ. Then, the output signal of the delay circuit 26 and the output signal of the coefficient circuit 23 are added by the adding circuit 27, and
The contour correction signal as shown in (f) is obtained.

In the contour compensating circuit of FIG. 6, since there is a relationship of f = 1 / (2t) between the boost frequency f and the width t of the contour correction signal, a low frequency portion which should have a visual enhancement effect should be detected. The contour correction signal generated when emphasizing has a wide width, and an unnatural edging occurs in the contour portion where the luminance difference of the video signal is large, which causes a problem that the sharpness of the image deteriorates.

As a method for solving such a problem,
Various contour compensation circuits have been considered (for example, Japanese Patent Publication No. 5).
-6392 publication).

FIG. 8 shows an example of the configuration of the contour compensation circuit. In FIG. 8, 21 to 27 are 21 to 2 in FIG.
It is the same as 7. 28 is a first non-linear conversion circuit for multiplying the signal obtained from the second addition circuit 27 by 1/2.
Is a subtraction circuit for subtracting the signal obtained by the first delay circuit 24 from the signal obtained by the first coefficient circuit 21, 30 is an absolute value circuit for taking the absolute value of the signal obtained by the subtraction circuit 29, and 31 is an absolute value The signal obtained from the circuit 30 is 1/2 of the delay amount 2τ of the first and second delay circuits 24 and 26.
Is a third delay circuit for delaying by τ corresponding to the second delay circuit 32 is a second delay circuit for multiplying the signal obtained from the third delay circuit 31 by a power of 1/2.
Is a non-linear conversion circuit, and 33 is a multiplication circuit that takes the product of the signal obtained from the first non-linear conversion circuit 28 and the signal obtained from the second non-linear conversion circuit 32.

FIG. 9 shows a, in the contour compensation circuit of FIG.
The signal waveforms at points b, c, d, e, and f are shown.
The operation of the contour compensation circuit of FIG. 8 will be described below with reference to FIG.

FIG. 9A shows an input signal waveform to the contour compensation circuit of FIG. 8. This input signal undergoes the same operation as that of the contour compensation circuit of FIG. The signal waveform is output and is multiplied by 1/2 by the non-linear conversion circuit 28.

On the other hand, the subtraction circuit 29 subtracts the output signal of the delay circuit 24 from the output signal of the coefficient circuit 21 to obtain the signal shown in FIG. 9B, and the absolute value circuit 30.
Then, the signal becomes as shown in FIG. 9D, which is delayed by τ by the delay circuit 31 as shown in FIG. 9E and is half-powered by the non-linear conversion circuit 32.

By multiplying the output signals of the non-linear conversion circuits 28 and 32 by the multiplication circuit 33, the contour correction signal shown in FIG. 9 (f) is obtained.

As shown in (f) of FIG. 9, in the contour compensation circuit of FIG. 8, a contour having a width half that of the contour correction signal (see (f) of FIG. 7) obtained by the contour compensation circuit of FIG. A correction signal is obtained, and more natural contour correction can be performed.

[0014]

However, the configuration of the contour compensation circuit of FIG. 8 requires a non-linear conversion circuit, an absolute value circuit, a multiplication circuit, and the like, so that the circuit scale becomes large. Further, there is a problem that the width of the contour correction signal cannot be set arbitrarily.

It is an object of the present invention to solve the above-mentioned conventional problems and to provide a contour compensation circuit capable of more natural contour correction.

[0016]

In order to achieve such an object, the contour compensating circuit of the present invention is generated by a first filter circuit for generating a contour correction signal of a video signal and a first filter circuit. A second filter circuit for generating a contour correction signal having an arbitrary width narrower than the contour correction signal, a coring circuit for clipping a signal obtained from the second filter circuit below a minute level to a zero value, and a core. A gate pulse generation circuit that generates a gate pulse that becomes a high level in a portion other than the zero value of the signal obtained by the ring circuit, and a signal obtained by the first filter circuit is controlled by the gate pulse to correct a narrower contour It is configured to include a gate circuit that generates a signal.

That is, the first contour compensation circuit of the present invention is
A delay circuit that outputs a video signal as a plurality of signals having different delay amounts, a first selector that receives a plurality of output signals of the delay circuit and selects an output signal having a delay amount T1, and an output signal of the first selector. A first coefficient circuit that inverts the polarity and reduces the level to 1/2, a second selector that receives a plurality of output signals of the delay circuit and selects an output signal having a delay amount T2, and a second selector Of a second coefficient circuit that inverts the polarity of the output signal of the above and reduces the level thereof by half, and a signal obtained by the first coefficient circuit and the delay circuit T (T1 <T <T2 and T− T1 = T2-
T) a first adder circuit for adding a signal delayed by the second coefficient circuit and a third selector for selecting an output signal of a delay amount T3 to which a plurality of output signals of the delay circuit are input And a third coefficient circuit that inverts the polarity of the output signal of the third selector and halves its level, and a plurality of output signals of the delay circuit are input and the delay amount T
And a fourth coefficient circuit for inverting the polarity of the output signal of the fourth selector and halving the level of the output signal of the fourth selector, and a third coefficient circuit. A predetermined amount T (T1 <T3 by the signal and the delay circuit
<T <T4 <T2 and T−T3 = T4−T) and a second addition circuit for adding the signal delayed by the fourth coefficient circuit and the signal obtained by the second addition circuit. A coring circuit that clips a minute level or less to a zero value, a gate pulse generation circuit that generates a high-level gate pulse at a portion other than the zero value of the signal obtained by the coring circuit, and a gate pulse generation circuit And a timing adjustment circuit for adjusting the timing of the gate pulse and an AND of the signal obtained by the first addition circuit and the signal obtained by the timing adjustment circuit
It has a configuration including a circuit.

The second contour compensating circuit of the present invention is the first contour compensating circuit.
Can be further simplified than the contour compensating circuit of, and the third coefficient circuit is a coefficient circuit that outputs without changing the polarity and level,
By replacing the second adder circuit with a subtractor circuit and omitting the fourth selector and the fourth coefficient circuit, it is possible to realize with a smaller circuit configuration.

[0019]

With this configuration, in the contour compensation circuit of the present invention, the thick contour correction signal generated by the first filter circuit and the narrow width signal generated by the second filter circuit are set to a minute level by the coring circuit. The following is clipped to a zero value, and a portion other than the zero value is set to a high level by the gate pulse generation circuit, and is cut off by the gate pulse generated to generate a narrow-width contour correction signal.

In the first contour compensation circuit of the present invention, the video signal is delayed by the delay amount T1 selected by the first selector to invert the polarity and the level is halved, and the second selector. A signal whose delay is delayed by the delay amount T2 and whose polarity is inverted and the level is halved, and a predetermined amount T (T1 <T <T2 and T-T1 = T2-
The signals delayed by T) are added by the first adder circuit and output. On the other hand, the video signal is delayed by the delay amount T3 selected by the third selector to invert the polarity and the level is halved, and the signal is delayed by the delay amount T4 selected by the fourth selector. A signal whose polarity is inverted and whose level is halved and a predetermined amount T (T1 <T3 <T <
The signals delayed by T4 <T2 and T−T3 = T4−T) are added by the second adding circuit, and the coring circuit clips a signal below a minute level to a zero value, and the gate pulse generating circuit makes a zero value. A gate pulse having a high level is generated in other parts, and a signal whose timing is adjusted by the timing adjusting circuit is output. An AND circuit outputs the logical product of the signal obtained by the first addition circuit and the signal obtained by the timing adjustment circuit to output a contour correction signal having a narrow width.

In the second contour compensating circuit of the present invention, the video signal is delayed by the predetermined amount T and delayed by the delay amount T3 (T1 <T3 <T <T2) selected by the third selector. Also, except that the gate pulse is generated from the signal obtained by subtracting the output signal without changing the level, it operates in the same manner as the first contour compensation circuit and outputs the narrow contour correction signal.

That is, the contour compensating circuit of the present invention can be configured by a small-scale circuit, and the thick contour correction signal of the low frequency video signal is cut off by the gate pulse generated from the contour correction signal thinner than that, thereby increasing the boost frequency. The contour correction is performed without changing the image quality, the contour portion that looks unnatural is improved, and the sharpness of the image is improved.

[0023]

1 is a block diagram showing the concept of a contour compensation circuit according to a first embodiment of the present invention.

In FIG. 1, 41 is a first filter circuit for generating a contour correction signal, and 42 is a second filter circuit for generating a signal having an arbitrary width narrower than the contour correction signal generated by the filter circuit 41. , 43 are filter circuits 4
2, a coring circuit that clips a level less than the minute level of the signal obtained by 2 to a zero value, 44 a gate pulse generation circuit that generates a high level gate pulse at a portion other than the zero value of the signal obtained by the coring circuit 43, Reference numeral 45 denotes a gate circuit that controls the contour correction signal generated by the filter circuit 41 by the gate pulse generated by the gate pulse generation circuit 44 to generate a narrow contour correction signal. The contour correction circuit shown in FIG. 1 will be described in detail below.

FIG. 2 is a block diagram showing a specific configuration of the contour compensation circuit in the second embodiment of the present invention.

In FIG. 2, reference numeral 1 is a delay circuit that outputs a video signal as a plurality of signals having different delay amounts, and reference numeral 2 is a first circuit that receives a plurality of output signals of the delay circuit 1 and selects an output signal having a delay amount T1. The selector 3 is a first coefficient circuit that inverts the polarity of the output signal of the first selector 2 and reduces its level to 1/2. Reference numeral 4 is a fifth coefficient circuit which outputs the video signal delayed by the delay amount T by the delay circuit 1 without changing the polarity and the level. Reference numeral 5 denotes a second selector which receives a plurality of output signals of the delay circuit 1 and selects an output signal having a delay amount T2. Reference numeral 6 inverts the polarity of the output signal of the second selector 5 and reduces its level to 1/2. 2 is a second coefficient circuit. 7 is a signal obtained by the first coefficient circuit 3 and a predetermined amount T obtained by the fifth coefficient circuit 4.
The first adder circuit adds a signal delayed by (T1 <T <T2 and T-T1 = T2-T) and a signal obtained by the second coefficient circuit 6. A third circuit 8 receives a plurality of output signals of the delay circuit 1 and selects an output signal having a delay amount T3.
The selector 9 is a third coefficient circuit which inverts the polarity of the output signal of the third selector 8 and reduces its level to 1/2. Reference numeral 10 is a sixth coefficient circuit for outputting the video signal delayed by the delay amount T by the delay circuit 1 without changing the polarity and level. Reference numeral 11 is a fourth input signal to which a plurality of output signals of the delay circuit 1 are input and which selects an output signal of the delay amount T4.
And a selector 12 for inverting the polarity of the output signal of the fourth selector 11 and halving its level.
Is a coefficient circuit of. Reference numeral 13 denotes a signal obtained by the third coefficient circuit 9 and a predetermined amount T obtained by the sixth coefficient circuit 10.
(T1 <T3 <T <T4 <T2 and T-T3 = T4-
T) a second adder circuit for adding the signal delayed by the fourth coefficient circuit 12 and a clip circuit 14 for clipping below a minute level of the signal obtained by the second adder circuit 13 to a zero value (core). Coring circuit for ring processing), 1
Reference numeral 5 is a gate pulse generation circuit that generates a gate pulse that becomes a high level in a portion other than the zero value of the signal obtained by the coring circuit 14, and 16 is a timing that adjusts the timing of the gate pulse generated by the gate pulse generation circuit 15. It is an adjustment circuit. An AND circuit 17 takes the logical product of the signal obtained by the first addition circuit 7 and the signal obtained by the timing adjustment circuit 16.

FIG. 3 shows a in the contour compensation circuit of FIG.
The signal waveforms at points b, c, and d are shown. The operation of the contour compensation circuit of this embodiment will be described below with reference to FIG.

Since the contour compensating circuit of this embodiment is configured as described above, the delay amounts T1 and T2 are respectively set to T-T1 = by the first selector 2 and the second selector 5.
When selected to be T2-T, the signal waveform output from the first adder circuit 7 is as shown in FIG. On the other hand, the third selector 8 and the fourth selector 11
The delay amounts T3 and T4 are respectively T-T3 = T
When 4-T and T1 <T3 <T <T4 <T2 are selected, the signal waveform output from the second adder circuit 13 is shown in (a) of FIG. 3 as shown in (b) of FIG. A signal waveform narrower than the signal waveform shown is obtained. After the coring processing is performed on the output signal of the second addition circuit 13 by the coring circuit 14, the gate pulse generation circuit 15 generates the gate pulse shown in (c) of FIG. 3 from the output signal of the coring circuit 14. It The output signal of the first addition circuit 7 is supplied to the gate pulse generation circuit 1 by the AND circuit 17.
The output signal of No. 5 is cut off by the signal whose timing is adjusted by the timing adjusting circuit 16,
As shown in (d) of, a thinner contour correction signal is obtained.

In the contour correction signal thus generated, the delay amounts T3 and T4 are arbitrarily selected by the third selector 8 and the fourth selector 11,
It can be of any thickness. Further, since the same effect as the coring treatment is performed, the S / N improving effect can be obtained.

FIG. 4 is a block diagram showing a specific configuration of the contour compensating circuit according to the third embodiment of the present invention.

In FIG. 4, elements other than 18 and 19 are the same as those shown in FIG. Reference numeral 18 denotes a third coefficient circuit which outputs the output signal of the third selector 8 without changing the polarity and level. 19 is a delay circuit 1 for a predetermined amount T (T
The subtraction circuit subtracts the signal obtained by the third coefficient circuit 18 from the signal delayed by 1 <T3 <T <T2 and T-T1 = T2-T).

FIG. 5 shows a in the contour compensation circuit of FIG.
The signal waveforms at points b, c, d, e, and f are shown.
The operation of the contour compensation circuit of this embodiment will be described below with reference to FIG.

Since the contour compensating circuit of this embodiment is configured as described above, the delay amounts T1 and T2 are set by the first selector 2 and the second selector 5 with the input signal waveform shown in FIG. , Respectively, so that T-T1 = T2-T, the signal waveform output from the adder circuit 7 becomes as shown in FIG. On the other hand, when the delay amount T3 is selected by the third selector 8 so that T1 <T3 <T, the signal waveform output from the subtraction circuit 19 is as shown in FIG. A waveform with a narrower width than the waveform shown in FIG. After the coring circuit 14 performs coring processing on the output signal of the subtraction circuit 19, the gate pulse generation circuit 15 generates the gate pulse shown in FIG. 5D from the output signal of the coring circuit 14. The timing of this gate pulse is adjusted by the timing adjusting circuit 16 so that the center of the gate pulse and the center of the contour correction signal output by the adding circuit 7 are aligned,
A waveform as shown in FIG. 5E is obtained. Adder circuit 7
The output signal of 1 is cut out by the AND circuit 17 by the gate pulse obtained by the timing adjustment circuit 16, and a thinner contour correction signal is obtained as shown in FIG.

The contour correction signal thus generated can be made to have an arbitrary thinness by arbitrarily selecting the delay amount T3 by the third selector 8. Further, since the same effect as the coring treatment is performed, the S / N improving effect can be obtained.

If the delay of the delay circuit 1 is performed by using the 1H line memory in the contour compensating circuits of FIGS. 2 and 4, vertical contour correction can be performed in the same manner.

[0036]

As described above, the contour compensating circuit of the present invention having the above-mentioned configuration can more naturally perform contour correction without changing the boost frequency.

Since the non-linear conversion circuit, the absolute value circuit and the multiplication circuit are not used in the contour compensating circuit of the present invention, the contour compensating circuit can be constructed with a small circuit scale, and since the gate pulse of any fineness can be generated, the contour compensating circuit of arbitrary fineness A contour correction signal can be obtained. At the same time, the contour correction signal has the same effect as the coring process, and the S / N improving effect is also obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the concept of a contour compensation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a contour compensation circuit according to a second embodiment of the present invention.

FIG. 3 is a signal waveform diagram showing the operation of the second embodiment.

FIG. 4 is a block diagram showing a specific configuration of a contour compensation circuit according to a third embodiment of the present invention.

FIG. 5 is a signal waveform diagram showing the operation of the third embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional contour compensation circuit.

FIG. 7 is a signal waveform diagram showing the operation of the conventional example shown in FIG.

FIG. 8 is a block diagram showing another example of a conventional contour compensation circuit.

9 is a signal waveform diagram showing the operation of the conventional example shown in FIG.

[Explanation of symbols]

 1 Delay circuit 2,5,8,11 Selector 3,4,6,9,10,12,18 Coefficient circuit 7,13 Adder circuit 14,43 Coring circuit 15,44 Gate pulse generation circuit 16 Timing adjustment circuit 17 AND Circuit 19 Subtraction circuit 41, 42 Filter circuit 45 Gate circuit

Claims (3)

[Claims] 1. A first for generating a contour correction signal of a video signal
Filter circuit, a second filter circuit for generating a contour correction signal of an arbitrary width narrower than the contour correction signal generated by the first filter circuit, and a signal obtained by the second filter circuit. A coring circuit that clips a minute level or less to a zero value; a gate pulse generation circuit that generates a gate pulse that becomes a high level in a portion other than the zero value of the signal obtained by the coring circuit; and the first filter circuit. And a gate circuit for generating a narrower contour correction signal by controlling the signal obtained by (1) with the gate pulse. 2. A delay circuit that outputs a video signal as a plurality of signals having different delay amounts, a first selector that receives a plurality of output signals of the delay circuit and selects an output signal having a delay amount T1, and the first selector. A first coefficient circuit that inverts the polarity of the output signal of the first selector and reduces its level to 1/2; and a second coefficient circuit that receives the plurality of output signals of the delay circuit and selects the output signal of the delay amount T2 And a second coefficient circuit that inverts the polarity of the output signal of the second selector and reduces its level to 1/2, a signal obtained by the first coefficient circuit, and the delay circuit. Quantitative T (T1 <T <T2 and T-T1 = T2-
T) a first adder circuit for adding a signal delayed by the second coefficient circuit and a third adder circuit for inputting a plurality of output signals of the delay circuit and selecting an output signal of a delay amount T3 And a third coefficient circuit that inverts the polarity of the output signal of the third selector and reduces its level to 1/2, and outputs a plurality of output signals of the delay circuit and outputs a delay amount T4. A fourth selector that selects a signal; a fourth coefficient circuit that inverts the polarity of the output signal of the fourth selector and reduces its level to 1/2; and a signal obtained by the third coefficient circuit And a predetermined amount T (T1 <T3 <T <T4 <T2 and T-
T3 = T4−T) A second addition circuit for adding the signal delayed by the fourth coefficient circuit and a signal obtained by the second addition circuit to a zero value below the minute level of the signal. A coring circuit that clips, a gate pulse generation circuit that generates a high-level gate pulse at a portion other than the zero value of the signal obtained by the coring circuit, and a timing of the gate pulse generated by the gate pulse generation circuit 2. A contour compensation circuit according to claim 1, further comprising: a timing adjustment circuit that adjusts the signal, and an AND circuit that takes a logical product of the signal obtained by the first addition circuit and the signal obtained by the timing adjustment circuit. circuit. 3. A delay circuit that outputs a video signal as a plurality of signals having different delay amounts, a first selector that receives a plurality of output signals of the delay circuit and selects an output signal having a delay amount T1, and the first selector. A first coefficient circuit that inverts the polarity of the output signal of the first selector and reduces its level to 1/2; and a second coefficient circuit that receives the plurality of output signals of the delay circuit and selects the output signal of the delay amount T2 And a second coefficient circuit that inverts the polarity of the output signal of the second selector and reduces its level to 1/2, a signal obtained by the first coefficient circuit, and the delay circuit. Quantitative T (T1 <T <T2 and T-T1 = T2-
An adder circuit for adding a signal delayed by T) and a signal obtained by the second coefficient circuit, and a third selector for receiving a plurality of output signals of the delay circuit and selecting an output signal of a delay amount T3. A subtraction circuit for subtracting a signal obtained by the third selector from a signal delayed by a predetermined amount T (T1 <T3 <T) by the delay circuit; A coring circuit that clips to a value, a gate pulse generation circuit that generates a gate pulse that becomes a high level in a portion other than the zero value of the signal obtained by the coring circuit, and a gate pulse that is generated by the gate pulse generation circuit Timing adjusting circuit for adjusting the timing of the signal, the signal obtained by the first adding circuit, and the signal obtained by the timing adjusting circuit Contour compensation circuit according to claim 1, characterized in that an AND circuit taking the logical product of No..