JPH0746096A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce higher harmonic components included in a line and further to miniaturize the current drive capacity of an inverter in a clock generation circuit by suppressing clock signals outputted to a clock line with a large load capacity by receiving oscillation output at a low amplitude level. CONSTITUTION:The oscillation output signals 101 of an oscillator 4 are outputted as sine wave signals and are inputted to the clock generation circuit 1 provided with the inverter 11 and resistors 12 and 13. The signals 101 are inverted and outputted by the inverter 11. At the time, the inverter 11 is biased to Vcc/2 by the resistors 12 and 13 and the current driving power of the inverter 11 is set so as to let an output level be at a low level lower than amplitude between a power supply voltage Vcc and a ground potential. In the meantime, since an internal circuit 3 which is the supply object of the clock signal is formed by a CMOS logic circuit, the potential of the low level is supplied to the internal circuit 3. In such a manner, a reference potential 103 from a reference potential generation circuit 5 is made identical to Vcc/2 imparted to the inverter 11 and is supplied to the circuit 3 as the clock signal 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit used as a clock signal supply circuit.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit of this type, a predetermined clock signal is generated from a signal output from an oscillator including a crystal oscillator or the like via a clock signal generation circuit, and is supplied to other circuits. It is generally supplied.

FIG. 5 is a circuit diagram showing a conventional semiconductor integrated circuit for generating and outputting a clock signal. As shown in FIG. 5, it corresponds to the internal circuit 3 to which the clock signal is supplied. The oscillator 4 and the clock driver circuit 7 including the inverters 71, 72 and 73 are configured. Further, FIG. 6 shows the oscillation output signal 1 of the oscillator 4.
10 is a timing chart showing signal waveforms of 01 and clock signal 106. FIG.

In FIG. 5, the oscillation output signal 1 of the oscillator 4 is shown.
01 is output as a sine wave signal as shown in FIG. 6, and is input to the clock driver circuit 7 including inverters 72, 72 and 73. In the clock driver circuit 7, the oscillating output signal 101 is shaped into a square wave by the inverters 71 and 72, and then the inverter 73 having a large current drive capability is used to generate a large load capacitance as shown in FIG. Clock signal 1
It is output as 06. Therefore, the clock signal 106
Is always supplied to the plurality of internal circuits 3 as a pulse wave having a constant amplitude, frequency and duty ratio via the clock line.

[0005]

In the above-described conventional semiconductor integrated circuit, when the clock signal output from the semiconductor integrated circuit is expressed by the Fourier analysis as the waveform in the time domain by the spectrum in the frequency domain, FIG. As shown in, the sine wave of the frequency f of the clock signal and the frequencies 3f, 5f that are odd multiples of the frequency f,
It is expressed as the sum of the harmonic components 7f, 9f, .... In the spectrum of FIG. 7, the frequency is 1
The harmonic components of 1f and above are omitted.

As described above, in the case of a clock signal whose amplitude, frequency, and duty ratio are always constant, energy is concentrated in a very narrow band, and a clock line having a large load capacity is used for current driving capability. Since it is driven by using a large inverter, noise including electromagnetic radiation is likely to occur, and in particular, in recent years, the operating frequency of the clock signal has been gradually increasing to 16 MHz and 32 MHz, which is an odd multiple of that. The frequency is in a state of being superimposed on the frequency band of conventional FM broadcasting and the frequency band of television broadcasting, which causes noise interference to the audio or image of these broadcasts and causes malfunctions on VTRs and stereos. There is a drawback that it becomes a factor.

When the inverter 73 having a large current drive capacity and a large load capacity is switching, a large transient current flows in the power supply ground potential, causing a voltage drop due to the parasitic resistance existing in the power supply ground wire, which causes other voltage drop. There is a drawback that it adversely affects various circuits.

[0008]

A semiconductor integrated circuit according to a first aspect of the present invention inputs an original signal having a predetermined frequency, is applied with a specific bias voltage, and has an amplitude level lower than a power supply voltage level. , A clock generation circuit that outputs a clock original signal having a frequency equal to the frequency of the above, a reference potential generation circuit that outputs a reference potential equal to the bias voltage, a clock original signal output from the clock generation circuit, and the reference potential. And a voltage shaping circuit for inputting and comparing both potential levels and amplifying the potential difference between them to output as a clock signal.

In the semiconductor integrated circuit of the second invention, an original signal of a predetermined frequency is input, a specific bias voltage is added, and a frequency equal to the frequency of the original signal having an amplitude level lower than the power supply voltage level. A clock generating circuit for outputting the first clock original signal, and a frequency of the original signal which is inputted with the original signal, is applied with a bias voltage equal to the specific bias voltage, and has an amplitude level lower than a power supply voltage level. A second clock generating circuit that outputs a second clock original signal having a frequency equal to the input signal, and the first clock original signal and the second clock original signal are input to compare the potential levels of the two signals. And a clock shaping circuit that amplifies the potential difference of 1 and outputs as a clock signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, an oscillator 4, a clock generation circuit 1 including an inverter 11 and resistors 12 and 13, and a reference corresponding to a plurality of internal circuits 3 to which a clock signal is supplied. The potential generating circuit 5 and the clock shaping circuit 2 including one comparator 21 are provided. 2 shows the oscillation output signal 101 of the oscillator 4, the output signal 102 of the clock generation circuit 1, the reference potential output 103 output from the reference potential generation circuit 5, and the clock signal 10 output from the clock shaping circuit 2.
4 is a timing chart showing a signal waveform of No. 4 of FIG.

In FIG. 1, the oscillation output signal 1 of the oscillator 4
01 is output as a sine wave signal as shown in FIG. 2, and is input to the clock generation circuit 1 including the inverter 11 and the resistors 12 and 13. In the clock generation circuit 1, the oscillation output signal 101 is inverted and output by the inverter 11. In this case, inverter 11 is biased to V _CC / 2 by resistors 12 and 13,
The current drive capability of the inverter 11 is set in advance by design so that the output level becomes a low level equal to or lower than the amplitude between the power supply voltage V _CC and the ground potential. As a result, the output signal 102 of the clock generation circuit 1 is, as shown in FIG. 2, a signal at a low potential level centered on the potential of V _CC / 2, and is output to the clock line as a signal with less harmonic components. It is output and input to the positive phase side of the comparators 21 forming the plurality of clock shaping circuits 2 via the clock line.

On the other hand, the internal circuit 3 to which the clock signal is supplied is formed of a CMOS logic circuit. Therefore, the amplitude of the supplied clock signal is the power supply voltage V.
It must be supplied as a potential level equal to the amplitude between _CC and ground potential. Therefore, the reference potential generating circuit 5
The reference potential 103 output from the clock generation circuit 1 is
At a potential of V _CC / 2 that is the same as the bias potential applied to the inverter 11 by the resistors 12 and 13, and is input to the opposite phase side of the comparators 21 included in the plurality of clock shaping circuits 2. It In the comparator 21 of each clock shaping circuit 2, the output signal 102 of the clock generation circuit 1 and the reference potential 103 are compared in potential level, and the potential level difference between these signals is the power supply voltage V _CC.
Is amplified to a potential level equal to the amplitude between the
As shown in FIG. 2, the clock signal 104 is output and supplied to the internal circuit 3. As is apparent from FIG. 2, when the potential level of the output signal 102 of the clock generation circuit 1 is higher than the reference potential 103 of the reference potential generation circuit 5, the clock signal 104 is output from the clock shaping circuit 2. The level of the output clock signal 104 becomes V _CC , and when the potential level of the output signal 102 of the clock generation circuit 1 is lower than the reference potential 103 of the reference potential generation circuit 5, the clock output from the clock shaping circuit 2 The level of the signal 104 is formed as a pulse signal having a ground potential.

In the present embodiment, the clock line from which the output signal 101 of the clock generation circuit 1 is output is set at a low level to suppress the noise level. In order to reduce the length of the corresponding signal wiring as much as possible, it is desirable that the clock generation circuit 1 be arranged near the oscillator 4 and the clock shaping circuit 2 be arranged near the internal circuit 3.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 3, in the present embodiment, an oscillator 4, an inverter 11, a clock generation circuit 1 including resistors 12 and 13, and an inverter are provided corresponding to a plurality of internal circuits 3 to which clock signals are supplied. 61 and 62, resistor 6
A second clock generation circuit 6 including 3 and 64, and a plurality of clock shaping circuits 2 each including a comparator 21 are provided. In this embodiment, a second clock generation circuit 6 is provided instead of the reference potential generation circuit 5 in the first embodiment described above. Further, FIG. 4 shows an oscillation output signal 101 of the oscillator 4 and an output signal 1 of the clock generation circuit 1.
02, the output signal 105 of the second clock generation circuit 6 and the clock signal 104 output from the clock shaping circuit 2.
3 is a timing diagram showing the signal waveform of FIG.

In FIG. 3, the oscillation output signal 1 of the oscillator 4
01 is output as a sine wave signal as shown in FIG. 4, and is input to the clock generation circuit 1 including the inverter 11 and the resistors 12 and 13. In the clock generation circuit 1, as in the case of the first embodiment, the oscillation output signal 10
1 is inverted and output by the inverter 11. In this case, the inverter 11 is V
_It is biased to _CC / 2, and the current drivability of the inverter 11 is set in advance by design so that the output level becomes a low level equal to or lower than the amplitude between the power supply voltage V _CC and the ground potential. As a result, the output signal 102 of the clock generation circuit 1 is, as shown in FIG. 4, a signal at a low potential level centered on the potential of V _CC / 2, and is output to the clock line as a signal with less harmonic components. It is output and input to the positive phase side of the comparators 21 forming the plurality of clock shaping circuits 2 via the clock line.

On the other hand, in the second clock generation circuit 6, the oscillation output signal 101 is output by being normally rotated by the inverters 61 and 62. In this case, inverter 62 is biased to V _CC / 2 by resistors 63 and 64, and the current drive capability of inverter 62 is
As in the case of the clock generation circuit 1, by designing beforehand,
The output level is set to a low level equal to or lower than the amplitude between the power supply voltage V _CC and the ground potential. As a result, the output signal 105 of the second clock generation circuit 6 is at a low potential level centered on the potential of V _CC / 2 having a phase opposite to that of the output signal 102, as shown in FIG. The signal is output as a signal with few components, and is input to the opposite phase side of the comparators 21 forming the plurality of clock shaping circuits 2 via the clock lines.

On the other hand, as in the case of the first embodiment, the internal circuit 3 to which the clock signal is supplied is formed of a CMOS logic circuit, and therefore the amplitude of the clock signal supplied is the power supply voltage V. It must be supplied as a potential level equal to the amplitude between _{CC and} ground potential. Therefore, the output signal 102 of the clock generation circuit 1 and the output signal 105 of the second clock generation circuit 6 are level-compared by the comparator 21 forming the clock shaping circuit 2, and the potential of the output signal 102 is output. If the potential of the output signal 102 is higher than that of the output signal 105, the amplified signal is amplified and output as the power supply voltage V _{CC. If} the potential of the output signal 102 is lower than the potential of the output signal 105, the amplified potential is amplified to the ground potential. Is output as. That is, it is amplified to a potential level equal to the amplitude between the power supply voltage V _CC and the ground potential, and is output as the clock signal 104 and supplied to the internal circuit 3 as shown in FIG.

In the case of the above-described first embodiment, the reference voltage generating circuit 5 outputs from the clock shaping circuit 2 when the reference voltage fluctuates due to the influence of "variation" in manufacturing and noise. There is a possibility that the duty ratio of the clock signal 104 does not become a constant pallet wave, but in the present embodiment, the output signal 102 of the clock generation circuit 1 is generated.
And the phase difference between the output signal 105 of the second clock generation circuit 6 and the source input signal are both the oscillation output signal 101 of the oscillator 4.
Therefore, there is an advantage that the clock signal 104 is not changed from 180 degrees, and the clock signal 104 is output from the clock shaping circuit 2 as a pulse signal having a constant duty ratio.

According to the present invention, by suppressing the potential level of the clock line having a large load capacitance to a low amplitude, the level of the harmonic component contained in the clock line can be reduced by 90% or more according to the simulation. is there.

[0021]

As described above, the present invention suppresses the clock signal output to the clock line having a large load capacitance to a low amplitude level by receiving the oscillation output,
It is possible to significantly reduce the harmonic components included in the clock line, and to suppress the current driving capability of the inverter included in the clock generation circuit that drives the clock line to a small level, which is a conventional transient. The current level is also greatly reduced, and the adverse effect on other circuits can be eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms in the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing operation waveforms in the second embodiment.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a diagram showing operation waveforms in a conventional example.

FIG. 7 is a diagram showing a spectrum of a conventional clock signal.

[Explanation of symbols]

 1 Clock generation circuit 2 Clock shaping circuit 3 Internal circuit 4 Oscillator 5 Reference potential generation circuit 6 Second clock generation circuit 7 Clock driver circuit 11, 21, 61, 62, 71-73 Inverter 12, 13, 63, 64 Resistance

Claims (2)

[Claims] 1. A clock generator for inputting an original signal of a predetermined frequency, adding a specific bias voltage, and outputting a clock original signal having a frequency equal to the frequency of the original signal having an amplitude level lower than a power supply voltage level. A circuit, a reference potential generation circuit that outputs a reference potential equal to the bias voltage, a clock original signal output from the clock generation circuit, and the reference potential, and both potential levels are compared. A semiconductor integrated circuit, comprising: a clock shaping circuit that amplifies a potential difference and outputs it as a clock signal. 2. A first signal having a frequency equal to the frequency of the original signal input with a predetermined frequency, having a specific bias voltage added thereto, and having an amplitude level lower than the power supply voltage level.
And a frequency equal to the frequency of the original signal having a lower amplitude level than the power supply voltage level, to which the original signal is input, a bias voltage equal to the specific bias voltage is added. Second
Second clock generation circuit for outputting the clock original signal of, and the first clock original signal and the second clock original signal are input, the potential levels of both signals are compared, and the potential difference between them is amplified. A semiconductor integrated circuit, comprising: a clock shaping circuit that outputs a clock signal.