JPH0745827A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device in which a shallow channel doping profile can be obtained, no damage is caused on a surface of a silicon of a substrate near a gate sidewall spacer, and a leakage current is low and which has no punchthrough. CONSTITUTION:The method for manufacturing a semiconductor device comprises the steps of sequentially laminating a gate insulating oxide film 3, a silicon film 4 and a CVD oxide film 5 on a silicon substrate 1, opening a gate electrode of the film 5, implanting impurity ions 8 of low energy and implanting impurity ions 9 of high energy from the opening 7, embedding conductor for a gate electrode 10 in the opening, then removing the film 5, and forming a gate sidewall spacer 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to an integrated circuit using a MOS type field effect transistor (MOSFET) having a channel length of submicron.

[0002]

2. Description of the Related Art The following two manufacturing methods are known for a conventional MOS field effect transistor (MOSFET). First, as shown in FIG. 6A, p-type impurity ions 34 are irradiated from above the silicon substrate 31 on which the field oxide film 32 and the screening oxide film 33 are formed to perform channel ion implantation. Then, as shown in FIG. 6B, after removing the screening oxide film 33,
A gate oxide film 35 is formed, a gate electrode 36 is formed on the gate oxide film 35, and n-type impurity ions 37 are irradiated from above to perform the first ion implantation for forming the source / drain.

Next, as shown in FIG. 6C, a silicon oxide film 38 is formed on the entire surface by the CVD method. Next in FIG.
As shown in (d), the silicon oxide film 38 is etched leaving only the side wall of the gate electrode to form a gate side wall spacer 38 ′.
7'is irradiated and the second ion implantation for source / drain formation is performed to complete the source / drain 39 of LDD (Lightly Doped Drain) structure.

The second is a method for overcoming the short channel deterioration. First, as shown in FIG. 7A, first, a silicon oxide film 42 and a silicon nitride film 4 are formed on the surface of a semiconductor substrate 41.
3 is sequentially deposited, a resist film is formed on the surface of the silicon nitride film 43, the silicon nitride film 43 in the portion where the field oxide film 44 is to be formed is removed by etching using a lithographic technique, and field oxidation is performed. A field oxide film 44 is formed.

Next, as shown in FIG. 7B, a resist film is formed on the surface of the silicon nitride film 43, and the silicon nitride film 43 is patterned by using a photolithography technique to pattern the gate electrode forming portion. And open. Next, as shown in FIG. 7C, the semiconductor substrate 41
N becomes the punch through stopper by implanting ions into the surface of
^{The +} -type ion implantation layer 45 is formed under the surface of the semiconductor substrate 41 at 0.
It is formed at a position of 3 μm.

Next, as shown in FIG. 7D, the silicon oxide film 42 in the opening of the silicon nitride film 43 is removed by etching, and a gate oxide film 46 is formed in this portion.
Next, as shown in FIG. 7E, a polysilicon film is deposited and etched back to form a gate electrode 47 made of polysilicon in the opening of the silicon nitride film 43. Then finally, as shown in FIG. 7 (f), by removing the silicon nitride film 43 by ion implantation under the following conditions in this part, p ⁺
Forming a source 48 and a drain 49 of the mold
-218165).

[0007]

A submicron field effect transistor (MOSF) formed on a silicon substrate.
ET) shows a significant deterioration in electrical characteristics due to a decrease in threshold voltage and a decrease in electron mobility when the channel length becomes almost the same as the layer width of the source and drain regions. This phenomenon is known as short channel deterioration, and it is a serious limitation when further miniaturizing the device.

MOSFETs have been developed in the sub-half micron region having a gate length of 0.3 μm. At this time, a very thin oxide film having a thickness of 10 nm or less is required at the same time. In addition, controlling the channel doping profile requires controlling dopant diffusion to form a shallow channel profile. The above-described conventional method for manufacturing the first MOSFET has the following problems.

I) It is difficult to achieve a shallow channel doping profile. The reason for this is as follows. FIG. 8A shows the relationship of the impurity concentration with respect to the depth direction (x) of the silicon substrate immediately after the channel impurity is doped into the silicon substrate through the screening oxide film 33. Thereafter, during the step of growing the gate oxide film, the diffusion of impurities by the gate oxide film is blocked and the impurities are diffused in the depth direction of the silicon substrate.
As shown in (b), the impurity concentration near the substrate surface decreases.

Ii) The silicon surface of the substrate near the gate sidewall spacer is easily scratched, and the scratch increases the leakage current of the transistor. In sub-micron and half-micron MOSFETs, LDD (Li
The ghtly Doped Drain structure is becoming widely used. The formation of the gate sidewall spacer is
The CVD oxide film is deposited as described above, and this etching back is performed. This etch back damages the silicon surface of the underlying substrate after etching the CVD oxide film.

The above-mentioned second conventional manufacturing method has not yet overcome the unexpected problem of punch-through. The present invention has been made to solve the above-mentioned problems, and can achieve a shallow channel doping profile, without causing scratches on the silicon surface of the substrate in the vicinity of the gate sidewall spacer, and having low leakage current and punch-through. An object of the present invention is to provide a method of manufacturing a semiconductor device which does not exist.

[0012]

According to the present invention, a)
A polysilicon or amorphous silicon film and a first CVD oxide film are sequentially formed on a silicon substrate on which an oxide film for transistor isolation and an oxide film for gate insulation are formed in advance.
b) etching the first CVD oxide film in the region where the gate electrode is to be formed to form an opening, and c) low energy impurity ions and higher energy impurity ions in the substrate through the opening. Implanting to form a channel region, d) embedding a conductor in this opening to form a gate electrode, and e) removing the first CVD oxide film,
Low concentration ion implantation is performed on both sides of the silicon substrate using the gate electrode as a mask to form low concentration impurity source / drain regions, and f) a second CVD oxide film is laminated on this region and etched back. Forming a gate side wall spacer by: g) etching the polysilicon or the amorphous silicon film using the gate electrode and the gate side wall spacer as a mask to form a gate electrode extension, and h) forming a gate electrode in the silicon substrate. And a gate sidewall spacer is used as a mask to perform high-concentration ion implantation on both sides of the gate sidewall spacer to complete the source / drain regions, thereby manufacturing a semiconductor device. Will be provided.

According to the present invention, a) A polysilicon or amorphous silicon film and a first CVD oxide film are sequentially formed on a silicon substrate on which a transistor isolation oxide film and a gate insulating oxide film have been formed in advance. The above-mentioned polysilicon or amorphous silicon film protects the oxide film for gate insulation in a later step, screens ions at the time of ion implantation, and serves as an etching stopper during the etch back to form the gate sidewall spacer. This is for buffering the stress caused by the wall spacer. This film thickness is usually 2
It is 0 to 60 nm.

The first CVD oxide film serves as a mask for setting a region for forming a gate electrode and for doping a channel in a substrate in a self-aligned manner with respect to a region for forming a gate electrode. The thickness of this first CVD oxide film is usually 300 to 500 nm. In the present invention, b) the first CVD oxide film in the region where the gate electrode is formed is etched to form the opening.

This etching is carried out using the underlying polysilicon or amorphous silicon film as an etching stopper. This opening is for channel doping and for forming a gate electrode, and its width corresponds to the width of the gate electrode, and is usually 0.3 to 5.0 μm. In the present invention, c) low-energy impurity ions and higher-energy impurity ions are implanted into the substrate through the opening to form a channel region.

The low energy impurity ions are MO
It is those for forming the channel for setting the threshold voltage of the SFET, to inject impurities into shallow regions of the silicon substrate through the polysilicon or amorphous silicon film and the gate insulating oxide film is good, for example, ¹¹ When implanting B ⁺ , the energy is usually 10 to 30 keV.
The injection amount is 0 × 10 ^{12 to} 5.0 × 10 ¹² at / cm ² .

Forming a channel for setting a threshold voltage in a shallow region of a silicon substrate is particularly important for forming the buried channel type PMOSFET shown in FIG. However, 19 and 19 'are sources and drains, 20 and 20' are LDDs, 21 is a channel for setting a threshold voltage, 22 is a buried channel for preventing punch-through, and Xc is the depth of the channel dope layer. Particularly in a submicron buried channel PMOSFET having a short channel length, it is very difficult to lower the threshold voltage (Vth). The threshold voltage exponentially increases with the channel length (Leff) as shown in the following equation. ΔVth∝exp (−hLeff) where h∝1 / Xc, where Xc is the channel thickness. Therefore, the shallower the channel, the better the short channel behavior of the transistor. According to the conventional method, it is difficult to obtain a shallow channel profile due to blocking and re-diffusion of doping impurities during thermal growth of the gate oxide film, and the channel depth Xc is about 0.1 μm. In the present application, 0.05 μm X is avoided by avoiding the blocking of impurities.
c is obtained, and as shown in FIG.
Can be lowered and short channel deterioration can be prevented.

The high-energy impurity ions are for forming a buried channel for preventing punch-through deterioration, and it is preferable to inject the impurity so as to be adjacent immediately below the LDD junction of the silicon substrate, for example, ¹¹ B ^+. In the case of injecting 1., the energy is usually 100 to 150 keV.
The injection amount is 0 × 10 ^{12 to} 5.0 × 10 ¹² at / cm ² . By implanting the impurity ions of low and high energy, the channel can be formed so that the relationship of the impurity concentration with respect to the channel depth (x) has a distribution as shown in FIG. 2, for example.

In the present invention, a conductor is embedded in this opening to form a gate electrode. As the conductor, for example, polysilicon, tungsten, a stacked body of polysilicon and tungsten, or the like is used. This conductor is on the polysilicon or amorphous silicon film on the bottom of the opening,
A gate electrode is formed by depositing to a thickness corresponding to the depth of the opening.

Since this gate electrode is buried in the channel-doped opening, it is arranged in a self-aligned manner with respect to the channel. In the present invention, e) the first
After removing the CVD oxide film of, the low-concentration impurity source / drain regions (lightly doped) are formed by implanting low-concentration ions on both sides of the silicon substrate using the gate electrode as a mask.
drain) is formed.

In the above-mentioned ion implantation, when ³¹ P ⁺ is used, the energy is usually 20 to 40 keV, and the implantation amount is usually 1.0 × 10 ^{13 to} 5.0 × 10 ¹³ at / cm ² . In the present invention, (f) a gate side wall spacer is formed by laminating a second CVD oxide film on this and etching back. The second CVD oxide film is
It should be larger than the thickness of the gate electrode, usually 100 to 3
It is 00 nm.

The above-mentioned etch back is performed by using the lower polysilicon or amorphous silicon film as an etching stopper and does not directly damage the oxide film for gate insulation near the lower gate sidewall spacer and the surface of the substrate silicon. Can be improved. Junction leakage current also increases due to the occurrence of stress-induced crystal defects from the sidewall edges. This junction leakage current depends on the amount of crystal defects generated. The present application places a thin polysilicon or amorphous silicon film between the substrate silicon surface and the CVD oxide sidewalls, which acts as a buffer film to prevent stresses that induce leakage power.

FIG. 5 compares the junction leakage current of a device with a conventional sidewall and a device with a buffer layer (polysilicon / oxide). This leakage current is
1 due to the stress induced by the sidewall
Increase by 0 times or more. The width of the gate sidewall spacer corresponds to the film thickness of the second CVD oxide film and is usually 10
It is 0 to 250 nm.

In the present invention, (g) the polysilicon or amorphous silicon film is etched using the gate electrode and the gate sidewall spacer as a mask to form a gate electrode extension. This etching is performed using the oxide film for gate insulation as an etching stopper.

As described above, the gate electrode extension portion acts as a buffer material for reducing the stress damage of the gate sidewall spacer to the substrate, and reduces the junction leakage current. In the present invention, (h) a source / drain region is formed by performing high-concentration ion implantation on both sides of a silicon substrate using a gate electrode, a gate sidewall spacer, and a gate electrode extension as a mask to form a semiconductor device. Complete.

[0026]

Since the ion implantation of the channel is performed after the oxide film for gate insulation is formed, a shallow channel doping profile can be formed without diffusion of channel impurities due to heat. The polysilicon or amorphous silicon film serves as an etching stopper during the etch back of the formation of the gate sidewall spacer, acts as a screening film during the ion implantation of the channel, and protects the underlying oxide film for gate insulation. The generated stress on the substrate surface is buffered and the leakage current is reduced.

[0027]

Embodiments of the present invention will be described with reference to the drawings.
As shown in FIG. 1A, a transistor isolation region (field oxide film) 2 and an active region are formed in a P-type silicon substrate 1 by a known MOS process technique. A 12 nm gate oxide film 3 is grown on the active region by a thermal oxidation method.

On top of this, a polysilicon layer 4 having a film thickness of 50 nm is formed.
Deposit. On top of this, the first film with a thickness of 300-500 nm
The CVD oxide film 5 is laminated. Then, a photoresist film 6 having an opening in the gate electrode formation region is laminated. Using the photoresist film 6 as a mask, the first CVD oxide film 5 is etched to form an opening 7 in the gate electrode formation region as shown in FIG. 1b).

Transistor channel region doping
The profile is set by ion implantation of impurity atoms through the opening 7. Normal channel doping is 2
Ion implantation is required twice. That is, MOSFET
Low energy boron implantation 8 for setting a threshold voltage and high energy boron implantation 9 for preventing punch-through deterioration.

This low energy boron implant typically includes 20 keV of ¹¹ B ⁺ at about 1 × 10 ^{12 to} 5 × 10 ¹² at.
It is performed by injecting an amount of / cm ² . This high energy ion implantation is at a dose of about 2 × 10 ¹² atoms / cm ² with 120 kev of ¹¹ B ⁺ . This high energy ion implantation 9
Depth is selected so as to have a peak concentration just below the LDD (n ⁻ ) junction as shown in FIG. This reduces the junction breakdown voltage but prevents the drain depletion layer region from spreading to the channel.

As shown in FIG. 1C, a gate electrode 10 is formed by burying polysilicon in the opening by selective epitaxy. The properties of this layer depend on growth conditions, such as temperature. For example, polysilicon has a deposition temperature of 800 ° C. and a growth rate GR> 100Å by using a reaction of SiCl ₄ + H _2.
Deposited per minute.

A low resistance refractory metal can also be used as the gate electrode 10. For example, tungsten (W)
Can be selectively grown on polysilicon using the following conditions. Gas: WF ₆ + SiH ₄ , supply ratio 10/8, growth temperature: 270
C. The thickness of this layer should be approximately equal to the trench depth.

As shown in FIG. 1D, after removing the CVD oxide film 5 in an HF solution, lightly doped drain (LDD) ion implantation 11 is performed to set a source N ^- 12 and a drain N ^- 12 'region. To do. Ion implantation 11 is typically performed using ³¹ P ⁺ ions for N ^- channel transistors. The implantation amount is about 3 × 10 ¹³ at / cm ² and the ion implantation energy is about 30 kev.

As shown in FIG. 1E, the gate sidewall spacer 14 is formed. The width of this sidewall is typically 100-250 nm, which depends on the thickness of the deposited second CVD oxide film 14. For example, to obtain a sidewall width of about 200 nm, a second CVD oxide film having a film thickness of 200 nm is deposited and anisotropic etchback is performed by RIE (reactive ion etching method).

The etching selectivity between the oxide film and the polysilicon is sufficient to completely etch the second CVD oxide film without etching the polysilicon film 4. Due to this fact, the etching of the thin oxide film 3 below is prevented, and the silicon surface is not damaged. In particular,
The conditions for this gate sidewall CVD etching are as follows.

RIE gas: CHF ₃ (52 Sccm) + CF ₄ (20 Sccm) +
Ar (96 Sccm) pressure: 200 mTorr RF power: 700 watts Etching ratio SiO ₂ / polysilicon = 8 After forming this gate sidewall spacer 14, the lower polysilicon film 4 is etched to form the gate electrode extension 1
3 is formed.

This thin polysilicon 4 can be etched under the following conditions. RIE gas: HBr (30 Sccm) + Cl ₂ (15 Sccm) +
He-O ₂ (4 Sccm) pressure: 120 mTorr RF power: 150 watts Etch ratio polysilicon / SiO ₂ = 40 The gate sidewall spacer 14 and the gate electrode extension 13 are formed when a large amount of source and drain ions are doped 15. Acts as a mask. In this ion doping, the amount of arsenic ions is 40 keV and the amount is 5 × 10 ¹⁵ / cm ² .

By this ion implantation, the source 16 and drain 16 'regions are formed. On the other hand, the ion implantation for heavily doping the source / drain can be performed before the thin polysilicon 4 is removed. In such a case, the thin polysilicon 4 acts as a screen layer to prevent the passage of ions.

As shown in FIG. 1F, the wiring layer 18 for contact and metal connection is set by a known method to complete this semiconductor device. However, 17 is an insulating layer.
The relationship between the impurity concentration and the channel depth of the obtained semiconductor device was as shown in FIG.

[0040]

According to the present invention, a shallow channel doping profile can be achieved, a substrate around the gate sidewall spacers is not scratched, leakage current is low, and punch-through is prevented. Can be provided.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a semiconductor device manufactured according to an embodiment of the present invention.

FIG. 2 is a diagram similarly showing a relationship of impurity concentration with respect to channel depth.

FIG. 3 is an explanatory diagram of a PMOSFET of this semiconductor.

FIG. 4 is a graph showing a relationship between a channel depth, a gate length and a threshold voltage according to the present invention.

FIG. 5 is a graph of leakage current according to the present invention.

FIG. 6 is a diagram illustrating a conventional manufacturing process of a semiconductor device.

FIG. 7 is an explanatory diagram of a manufacturing process of a conventional semiconductor device.

FIG. 8 is an explanatory diagram of an impurity concentration of a conventional semiconductor channel.

[Explanation of symbols]

1 Silicon substrate 2 Transistor isolation region 3 Gate oxide film 4 Polysilicon film 5 First CVD oxide film 6 Photoresist film 7 Opening 8 Low energy boron (ion) implantation 9 High energy boron (ion) implantation 10 Gate electrode 11 LDD Ion Implantation 12 Source N ^- 12 'Drain N ^- 13 Extended Gate Electrode 14 Second CVD Oxide Film (Gate Sidewall Spacer) 15 Source and Drain Ion Doping 16 Source 16' Drain 17 Insulation Layer 18 Wiring Layer

Claims (1)

[Claims] 1. A) a polysilicon substrate or an amorphous silicon film and a first CVD oxide film are sequentially formed on a silicon substrate on which a transistor isolation oxide film and a gate insulating oxide film are formed in advance, and b) a gate electrode is formed. The first CVD oxide film in the region to be formed is etched to form an opening, and c) low energy impurity ions and higher energy impurity ions are implanted into the substrate through the opening to form a channel region. And d) embedding a conductor in this opening to form a gate electrode, and e) removing the first CVD oxide film, and then using the gate electrode as a mask in the silicon substrate to form a low voltage on both sides thereof. Concentration ion implantation is performed to form low-concentration impurity source / drain regions, and f) a second CVD oxide film is stacked on this region and etched back to form a gate sidewall. A gate spacer is formed, and g) the polysilicon or amorphous silicon film is etched by using the gate electrode and the gate sidewall spacer as a mask to form a gate electrode extension, and h) the gate electrode and the gate sidewall are formed in the silicon substrate. A method of manufacturing a semiconductor device, characterized in that high-concentration ion implantation is performed on both sides of the spacer using the mask as a mask to complete the source / drain regions, and a semiconductor device is manufactured.