JPH0745780Y2 - Signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of the device C Conventional technology (Figs. 6 and 7) D Problems to be solved by the device (Figs. 6 and 7)
E) Means for solving problems (Figs. 1, 2 and 4) F Action (Figs. 1, 2 and 4) G Example (Figs. 1 to 5) ) H Effect of the invention A Industrial field of application The present invention relates to a signal generating circuit, and is suitable for application to, for example, a signal generating circuit of a bowtie signal.

B Outline of the Invention The present invention can obtain a highly accurate reference signal with a simple configuration by providing a plurality of waveform data in the signal generation circuit according to the phase at which the reading is started.

C Conventional Technology Conventionally, when transmitting a video signal, a bow tie (bom ti)
e) The signal is used to adjust the phase of the video signal (Japanese Patent Application No. 1-18792).

That is, in the signal generation circuit of the bow tie signal, the frequency of 500
Sine wave signals of [KHz] and 502 [KHz] are output, and the sine wave signals are created based on the waveform data stored in the read-only memory circuit.

For example, as shown in FIG. 6, 999
If it is divided into sampling waveform data and stored in a read-only memory circuit, and this is read out sequentially every 37 samplings with a clock signal of frequency 13.5 [MHz],
Waveform data of a continuous sine wave can be obtained at a frequency of 500 [KHz].

Therefore, in synchronization with a predetermined reference signal, for example, the waveform data is read from the 10th sampling and sequentially read 47, 84, 12
1, ..., 935, After reading the 972nd sampling, if you repeat from the 10th sampling again, the frequency
Waveform data of a sine wave that is continuous at 500 [KHz] and starts at the 10th sampling phase is obtained.

Therefore, the bowtie signal for adjusting the luminance signal is obtained by outputting the waveform data of the sine wave through the digital-analog conversion circuit.

On the other hand, as shown in FIG. 7, in the bow-tie signal for adjusting the chroma signal, the sine wave signal of one cycle is decomposed into waveform data of 995 samplings and stored in the read-only memory circuit.

By doing this, a clock signal with a frequency of 13.5 [MHz], which is equal to the clock signal for adjusting the luminance signal, is read out every 37 samplings in sequence, and a frequency of approximately 502 [KHz]
It is possible to obtain continuous sine wave waveform data.

Therefore, in the bow tie signal for adjusting the chroma signal, the waveform data is read from the 10th sampling, for example, in synchronization with a predetermined reference signal and sequentially read 47, 84, 121 ,.
After reading the 5th and 972th sampling, the 15th sampling returns, 52, 89, ..., Sampling order is followed by waveform data for every 37th sampling. At a frequency of about 502 [KHz]. Waveform data of a sine wave that is continuous and starts at the 10th sampling phase is obtained.

Thus, the frequencies 500 [KHz] and 50 created in this way
The sine wave signal of 2 [KHz] is given to the luminance signal processing circuit and the chroma signal processing circuit, respectively, and the beat of the output is obtained, so that the phase of the luminance signal and the chroma signal is high with reference to the predetermined reference signal. It can be adjusted to a predetermined phase with accuracy.

D Problem to be solved by the invention By the way, when the sine wave waveform data of a predetermined phase is read out in this way, the read-out of the address data for sequential reading is started depending on which sampling waveform data is read out. It is necessary to update from the address data of every 37 samplings.

Therefore, there is a problem that the configuration of the address data creation circuit becomes complicated accordingly.

In particular, in the case of the bow tie signal for adjusting the chroma signal, when the reading is started again after reading for one cycle, it is unavoidable that the address data at the start of reading changes each time (in this case, in the first cycle). , The waveform data is read from the 10th sampling, while it is 15 from the 2nd cycle.
The waveform data is read from the sampling point), and the configuration of the address data creation circuit becomes more complicated.

Therefore, there is a problem that the configuration of the entire signal generating circuit becomes complicated accordingly.

The present invention has been made in consideration of the above points, and is intended to propose a signal generation circuit that can obtain a signal of a predetermined phase with a simple configuration.

E Means for Solving the Problem In order to solve the problem, in the present invention, the waveform data of the reference signal is sequentially stored in the order of the address, and the end identification data is stored at the address following the end of the series of waveform data. The memory circuit (9 (20)) in which (00H (marker)) is recorded and the output data output from the memory circuit (9 (20)) are sequentially input, and the output data (D _BC (D _BY ))
From the end detection data (00H (marker)) and outputs a detection signal, and a phase designation means for selecting the phase of the reference signal read from the memory circuit (9 (20)). (6 (16)) and phase designation means (6 (1
According to the selection result of (6)), a read start address generating means (7) for generating a read start address for reading the waveform data.
(17)), when a read start is instructed, a read address is generated from the read start address, and when the detection signal (S _ST ) is input and the end identification data (00H (marker)) is detected, the end A read address generating means (8 (19)) for returning the read address to a predetermined address determined corresponding to the address where the identification data (00H (marker)) is recorded and continuously generating the read address is provided.

F action The end identification data (00H (marker)) is recorded in the address following the end of the series of waveform data, and this end identification data (00H (marker)) is detected from the output data output from the memory circuit (9 (20)). The end identification data (00H
(Marker)) is returned to a predetermined address determined based on the recorded address and the read address is continuously generated, so that a reference signal having a predetermined phase corresponding to the read start address can be easily created. it can.

G Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a signal generation circuit for a bow tie signal as a whole, which is adapted to give a horizontal synchronization signal S _H and a vertical synchronization signal S _V which are intra-station synchronization signals to a reference signal generation circuit 3.

The reference signal generation circuit 3 creates a clock signal CK having a frequency of 13.5 [MHz] which is synchronized with the horizontal synchronization signal S _H and the vertical synchronization signal S _V, and is synchronized with the vertical synchronization signal S _V during a predetermined horizontal scanning period. A clear signal CL whose signal level rises at the timing of starting scanning is created.

Further, the reference signal generating circuit 3 outputs the clock signal CK and the clear signal CL to the bow tie signal generating circuit 4 for adjusting the chroma signal and the bow tie signal generating circuit 5 for adjusting the luminance signal, whereby the clock signal CK and the clear signal CL are output. A bow tie signal for adjusting the luminance signal and adjusting the chroma signal, which is held in a predetermined phase with respect to the intra-station synchronization signal, is created based on the CK and the clear signal CL.

That is, in the bow-tie signal generating circuit 4 for adjusting the chroma signal, the rotary switch 6 outputs 8-bit data according to the rotational position of the operator.

On the other hand, the memory circuit 7 is a read-only memory (RO
M), which receives the 8-bit data obtained from the rotary switch 6 as address data, and the read start address data D _STC determined by the manipulated variable of the rotary switch 6 is transferred to the memory circuit 9 via the address data generation circuit 8. It is designed to output to.

The address data generation circuit 8 takes in the read start address data D _STC at the timing when the clear signal CL rises, and thereby outputs the read start address data D _STC to the memory circuit 9 via the address data generation circuit 8. ing.

Further, the address data generation circuit 8 takes in the read start address data D _STC and then successively updates the read start address data D _STC by 1 in synchronization with the clock signal CK. Is output to the memory circuit 9.

As a result, the address data generation circuit 8 causes the clock signal
In the cycle of CK, the value is sequentially 1 from the read start address data D _STC
The address data D _RC, which increases in increments of 1, is output to the memory circuit 9.

Further, the address data generation circuit 8 includes a marker detection circuit 10
When the marker detection signal S _ST is output from, the address data D _RC is initialized, and then the value is updated by 1 again in sequence.

Therefore, in the memory circuit 9, when the marker detection signal S _ST is output after the address data which is sequentially incremented by 1 from the predetermined value determined by the operation amount of the rotary switch 6, is input, the address returns to 0 and again. Address data D _RC that increases by 1 is input, and this repetitive operation is repeated in a predetermined cycle in synchronization with the vertical synchronizing signal S _V.

Further, as shown in FIGS. 2 and 3, the memory circuit 9 is
It is composed of a read-only memory (ROM) with a capacity of 1 [KB], and decomposes a sine wave signal of one cycle into waveform data of 994 samplings, and the waveform data is successively recorded every 37 samplings in a recording area where addresses are continuous. It is designed to be recorded.

That is, the 0th sampling waveform data is stored in the 0th address recording area, and the 37th sampling waveform data is stored in the 1st address recording area.

Further, the waveform data of the 74th, 111th, ..., Sampling points are sequentially stored in the recording area values of the addresses 2, 3, ..., And the waveform data of the 962nd sampling is followed by the waveform data of the 5th sampling. It is designed to be stored.

After the waveform data, the 42nd sampling waveform data is stored, the 89th, 116th, ..., Sampling waveform data is sequentially stored, and the 967th sampling waveform data is followed by the 10th sampling waveform data. Waveform data is stored.

Similarly, the waveform data is stored in sequence,
The waveform data of the 994th sampling is stored in the recording area of 4 addresses, and the reference data for the marker having the value 00H is stored in the recording area of the last 995 addresses.

Thus, in the memory circuit 9, 37 kinds of waveform data having different phases starting from the 0th sampling, the 5th sampling, the 10th sampling, ... Are successively stored.

Accordingly, the read start address data D _{STC is} read from the memory circuit 9.
The waveform data can be obtained every 37 samples in synchronization with the clock signal CK from a predetermined address determined by.

At this time, in the waveform data, the sine wave signal of one cycle is
Since it is decomposed into 994 sampling waveform data and stored every 37 samples, if sequentially read out in synchronization with the clock signal CK of frequency 13.5 [MHz], a sine wave of frequency 502 [KHz] will be generated. Waveform data can be obtained.

On the other hand, the marker detection circuit 10 outputs the marker detection signal when the reference data for the marker is output from the memory circuit 9.
It is designed to output S _ST .

Therefore, in the memory circuit 9, when the recording area of the last 995 addresses from the predetermined address determined by the read start address data D _STC is reached, the waveform data is returned to 0 address and output.

As a result, in synchronization with the vertical synchronizing signal S _V from the memory circuit 9, at a frequency 502 [KHz] which is started at the timing of scanning start in a predetermined horizontal scanning period and in a predetermined sampling phase determined by the operation amount of the rotary switch 6. The waveform data of the sine wave can be obtained.

In this embodiment, the waveform data is output through a digital analog conversion circuit (not shown), which allows clock signal adjustment at a frequency of 502 [KHz] in synchronization with the internal synchronization signal at a predetermined phase. Is designed to get the bowtie signal of.

Thus, in the address data generation circuit 8, the address data is sequentially updated by 1 from the predetermined address determined by the read start address data D _STC , and the marker detection signal S _ST is updated.
When the signal rises, the bowtie signal having a desired phase can be obtained with a simple configuration in which the address is returned to 0 and the update operation is repeated, and the configuration of the entire bowtie signal generation circuit 1 can be simplified accordingly.

Incidentally, in the bow tie signal generating circuit 4 for adjusting the chroma signal, the rotary switch 6 constitutes the phase designating means for selecting the phase of the bow tie signal which is the reference signal, whereas the memory circuit 7 is the result of the selection of the phase designating means. Accordingly, the read start address generating means for outputting the read start address of the waveform data stored in memory circuit 9 is constituted.

Further, the address data generation circuit 8 constitutes a read address generation means for sequentially outputting the read address of the waveform data to the memory circuit 9 based on the read start address, while the memory circuit 9 starts the read of the reference signal. A memory circuit configured to continuously store waveform data of a plurality of waveforms corresponding to phases.

On the other hand, the bowtie signal generation circuit 5 for adjusting the luminance signal
In, the rotary switch 16 and the memory circuit 17 are configured similarly to the rotary switch 6 and the memory circuit 7,
The read start address data D _STY determined by the manipulated variable of the rotary switch 16 is used to switch the switching circuit 18 and the address data generation circuit 19
To the memory circuit 20 via.

Thus, in the memory circuit 20, when the clear signal CL rises, the waveform data is sequentially output from a predetermined address according to the operation amount of the rotary switch 16.

On the other hand, the switching circuit 18 uses the update data output from the address data update circuit 22 when the clear signal CL rises.
The read start address data D _STY is output to the address data generation circuit 19 instead of D _ENY .

The address data generation circuit 19 outputs the read start address data output from the switching circuit 18 when the clear signal CL rises.
D _STY capture, which causes the relevant address data generation circuit
Read start address data D _STY via memory circuit 20
It is designed to output to.

Further, the address data generating circuit 19 successively updates the read start address data D _STY by 1 in synchronization with the clock signal CK and updates the updated data by the memory circuit.
20 to output the clock signal CK.
In this cycle, the address data D _RY that sequentially increases by 1 from the read start address data D _STY is output.

Further, the address data generation circuit 19 includes a marker detection circuit 24
When the detection signal S _ST is output from, the update data D _ENY is _fetched and the address data D _RC that sequentially increases by 1 from the update data D _ENY is output instead of the read start address data D _STY . .

Thus, in the bow tie signal generating circuit 5 for adjusting the chroma signal, when the detection signal S _ST is output, the updating operation is repeated from the 0 address, while in the bow tie signal generating circuit 5 for adjusting the luminance signal, the update data is updated. The update operation is repeated from D _ENY .

On the other hand, as shown in FIG. 4 and FIG.
Reference numeral 20 is a read-only memory (ROM) with a capacity of 1 [KB], and decomposes a sine wave signal of one cycle into waveform data of 999 samplings, and records the waveform data sequentially at every 37th sampling. The area is continuously recorded.

At this time, in the bow tie signal for chroma signal adjustment,
Since the frequency must be 502 [KHz], select 994 as the sampling number and read it with the clock signal CK of frequency 13.5 [MHz], so that the waveform data is circulated to the original waveform data in 37 cycles. Can be configured.

On the other hand, in the bow tie signal for adjusting the luminance signal, the frequency is 500 [KHz], so the waveform data of 999 sampling is converted to the clock signal CK of frequency 13.5 [MHz].
Read every 37 samples with.

However, when the 999-sampling waveform data is read every 37 samplings, the original waveform data is returned in one cycle.

Therefore, in the bow-tie signal generating circuit 5 for adjusting the luminance signal, the memory circuit 20 stores the waveform data of 1 cycle starting from the 0th sampling, the waveform data of 1 cycle starting from the 1st sampling, and the 1 cycle starting from the 2nd sampling. Waveform data, ..., One cycle of waveform data starting from the 36th sampling is sequentially stored.

Further, the reference data for the marker having a value of 00H is stored following the final waveform data of each cycle, whereby the 0th sampling, the 1st sampling,
It is designed to be able to detect breaks in 37 types of waveform data with different phases starting from.

On the other hand, the address data update circuit 22 is configured by an adder circuit, and the update data D _ENY obtained by subtracting the value 27 from the address data output from the address data generation circuit 19 is sent to the switching circuit 18. Output.

On the other hand, the marker detection circuit 24 uses the marker detection circuit 10
Similarly, when the reference data for the marker is output from the memory circuit 20, the marker detection signal S _ST is output.

Therefore, in the memory circuit 20, one waveform data of 37 types of waveform data is sequentially read from the predetermined address determined by the read start address data D _STY according to the read start address data D _STY , and the marker is set. Once detected,
The update data D _{ENY obtained} by subtracting the value 27 from the address data is _fetched by the address data update circuit 22,
The waveform data of the phase is continuously read.

As a result, in synchronization with the vertical synchronizing signal S _V , at the timing of scanning start in a predetermined horizontal scanning period and at the same time as the rotary switch.
It is possible to obtain sinusoidal waveform data D _BY having a frequency of 500 [KHz] that starts at a predetermined sampling phase determined by the operation amount of 16.

Therefore, by outputting the waveform data through a digital analog conversion circuit (not shown), the frequency of 500
At [KHz], it is possible to obtain a bow-tie signal for adjusting the luminance signal, which is synchronized with the in-station synchronization signal at a predetermined phase.

Thus, in the address data generation circuit 19, the address data is updated one by one from the predetermined address determined by the read start address data D _STY , and the marker detection signal S _ST
When the signal rises, the bowtie signal having a desired phase can be obtained with a simple configuration of returning to the address of the update data D _ENY and repeating the update operation, and the entire configuration of the bowtie signal generation circuit 1 is simplified accordingly. be able to.

Further, the bow-tie signals for adjusting the chroma signal and the brightness signal having different frequencies can be created with high accuracy with reference to one clock signal CK, and the entire configuration can be simplified accordingly.

Further, by storing the waveform data of a plurality of waveforms according to the read start phase in the memory circuit in this way, the bow-tie signal for adjusting the chroma signal and the brightness signal can be generated by simply switching the read start address. The phase can be adjusted independently with high accuracy, and the phase adjustment accuracy of the video signal can be increased accordingly.

By the way, in the bow tie signal generating circuit 5 for adjusting the luminance signal, the rotary switch 16 constitutes the phase designating means for selecting the phase of the bow tie signal which is the reference signal, while the memory circuit 17 shows the result of the selection of the phase designating means. Accordingly, the read start address generating means for outputting the read start address of the waveform data stored in the memory circuit 20 is constituted.

Further, the address data generating circuit 19 constitutes a read address generating means for sequentially outputting the read address of the waveform data to the memory circuit 9 based on the read start address, while the memory circuit 20 starts reading the reference signal. A memory circuit configured to store waveform data of a plurality of waveforms according to phases is configured.

According to the above configuration, waveform data of a plurality of waveforms corresponding to the start phase of the bowtie signal is stored in the memory circuits 9 and 20,
By sequentially reading according to the operation amount of the rotary switches 6 and 16, it is possible to obtain a bow-tie signal having a desired phase with a simple configuration.

In the above embodiment, the rotary switch 6 and
Although the case where the phase designating means is constituted by 16 and the read start address generating means is constituted by the memory circuits 7 and 17 has been described, the present invention is not limited to this, and various means can be applied, for example, phase switching or If it is not necessary to make adjustments, the configuration can be made even simpler.

Further, in the above embodiment, the case where the bow tie signal generating circuit 1 creates the bow tie signal for the luminance signal adjustment and the chroma signal adjustment has been described, but the present invention is not limited to this, and the present invention is not limited to this. The bow tie signal generating circuit for adjusting the chroma signal may be configured separately.

Furthermore, in the above-described embodiment, the case of generating a sine wave is described, but the present invention is not limited to this, and can be widely applied to the case of creating various reference signals such as a triangular wave and a sawtooth wave.

Further, in the above-mentioned embodiments, the case where the present invention is applied to the bowtie signal generating circuit has been described, but the present invention is not limited to this and can be widely applied to signal generating circuits which generate various reference signals.

H Effect of the Invention The waveform data of the reference signal and the end identification data indicating the end of the waveform data are recorded in the memory circuit, and when the end identification data is detected from the output data sequentially read based on the read address, By returning to a predetermined address based on the address where the end identification data is recorded and continuously generating a read address,
It is possible to repeatedly read the waveform data according to the reading start phase. As a result, it is possible to realize a signal generation circuit that has a simple configuration and is capable of obtaining a reference signal having a desired phase.

[Brief description of drawings]

FIG. 1 is a block diagram showing a bowtie signal generating circuit according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing waveform data for adjusting a chroma signal, and FIG. 3 is a chart showing the waveform data. FIG. 5 is a schematic diagram showing waveform data for adjusting a luminance signal, FIG. 5 is a table showing the waveform data, and FIGS. 6 and 7 are schematic diagrams showing conventional waveform data. 1, 4, 5 ... Bowtie signal generating circuit, 3 ... Reference signal generating circuit, 6, 16 ... Rotor switch, 7, 9, 17, 20
...... Memory circuit, 8, 19 ...... Address data generation circuit,
9, 20 ... Memory circuit, 10, 24 ... Marker detection circuit.

Claims (1)

[Scope of utility model registration request] 1. A memory circuit in which waveform data of a reference signal is sequentially stored in an address order, and end identification data is recorded at an address following the end of the series of waveform data, and the memory circuit outputs the data. Termination detection means for sequentially inputting output data, detecting the termination identification data from the output data and outputting a detection signal, phase designation means for selecting the phase of the reference signal read from the memory circuit, and the phase designation A read start address generating means for generating a read start address for reading the waveform data according to the selection result of the means, and a read address is generated from the read start address when the read start is instructed, and the detection signal is inputted. And the end identification data is detected, a predetermined value is determined corresponding to the address where the end identification data is recorded. Read address generating means for returning the read address to the read address and continuously generating the read address.