JPS6035115Y2 - rhythm sound source - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a rhythm sound source that uses a random address generator to generate a rhythm sound having a non-monotonous tone and close to that of a natural musical instrument.

An example of a method for digitally creating a cymbal noise sound source as a conventional rhythm sound source is shown in FIG. 1a.

In other words, the outputs of the 3rd and 177th stages of the 17-stage shift register 1 driven by the clock generator 5 are exclusively ORed.
Through the circuit (EX-OR) 2, it outputs "1" when the levels are different, and "0" when the levels are the same, and returns it to the first stage through the OR circuit 3, and then pseudo-randomly outputs 2"-i times from the 17 stage output. Get a pulse.

In addition, the NOR circuit 4 which inputs the output of each stage of the shift register 1 inputs its output to the first stage via the OR circuit 3, thereby eliminating the state of "0°" for all stages and setting the initial condition as "1" for all stages. '.

By using the random address generation circuit 10 having such a configuration and changing the state of the shift register 1 shown in Table 1, which will be described later, it is possible to obtain a pulse output having a random pulse width and pulse interval as shown in the figure, for example. .

This pulse output is passed through a low pass filter (LPF) 6 and sent to an acoustic system to obtain a noise source.

However, the signal shown in the figure has only two amplitude values, ``1'' and ``0'', so although it contains random frequencies, the tone is monotonous, making it tasteless and different from that of a natural musical instrument. .

The purpose of the present invention is to provide a rhythm sound source that uses a random address generator to generate rhythm sounds that have non-monotonous tones and are similar to those of natural musical instruments.

In order to achieve the above object, the rhythm sound source of the present invention includes a plurality of address signal generation circuits including at least one random address signal generation circuit that generates random addresses, and a plurality of address signal generation circuits that store a predetermined waveform. The present invention is characterized in that it includes a waveform storage circuit that is controlled to selectively input an address signal from the address signal and output a predetermined waveform with an amplitude value corresponding to the address signal.

The present invention will be described in detail below with reference to examples.

FIG. 2 is a schematic explanatory diagram of an embodiment of the present invention.

In the same figure, a plurality of address signal generation circuits 11ttl
12t..., at least one random address signal generation circuit 10 is provided, and the control circuit 12 selectively derives the address signal output from each.

This selectively derived address signal is input into the waveform storage circuit 13, and the amplitude value corresponding to the address signal is read out.

This waveform storage circuit 13 stores an arbitrary waveform such as a sine wave.
The amplitude value corresponding to the address signal is stored in binary code and is outputted to the audio system via the D/A converter 14.

The control signal of the control circuit 12 may be manual or preset.

Therefore, a plurality of address signal generation circuits 1h, 11°...
. . . By selecting a signal from the random address signal generation circuit 10, a rhythm sound whose tone color changes can be obtained.

FIG. 3 is a detailed explanatory diagram of the embodiment of FIG. 2.

In the same figure, a 17-stage shift register l, EX-OR
Circuit 2. OR circuit 3. NOR circuit 4. Clock generator 5
The random address generation circuit 10° consisting of the following is shown in FIG.

As an example of this random address signal is shown in Table 1 below, the horizontal column indicates each stage jjs, ~S1 of the shift register.
I took a 7, and Tokiya was on the vertical swing.

-t8, and all "
1.

The state of this shift register 1 is the above-mentioned S3 and S17.
By inputting to the first stage, a pseudo-random pulse indicating a state change of (217-1) is obtained.

However, the random address signal generation circuit 10 is not limited to this configuration and may have another configuration as long as it outputs a random address signal.

Random address signals from any output stage of the shift register 1 of this random address signal generation circuit 10, for example, the 14th to 17th stages, and the clock CLK i of the clock generator 5
Inverters 3 i and A surrounded by dotted lines serve as control circuits (12 in FIG. 2) that select and output the address signal regularly output from the counter 21 and the address signal driven by the counter 21.
A combination of a logic circuit 22 consisting of a plurality of sets of ND circuits 32, 33 and OR circuits 34, and a shift register 23 driven by a slow clock CLK 2 from a clock generator 5 via a clock divider 24 is used. .

That is, when all of the shift registers 23 are at low level, regular signals from the address counter are sent from the inverter 31 and the AND circuit 32 to the waveform memory circuit (RO) through the OR circuit 34.
M) Output to 13.

By gradually shifting the high level (H) from the LBS to the MSB of the shift register 23 by the clock CLK 2, the output signal of the shift register 1 of the random address signal generation circuit 10 is transferred to the waveform storage circuit (ROM) through the AND circuit 33. )13.

In this way, the regular address signal of the address counter 21 is superimposed on the irregular random address signal from the random address signal generating circuit 10, making it possible to generate more complex timbre changes than in conventional circuits.

The output data from the waveform storage circuit 13 is sent to the D/A converter 14.
The signal is D/A converted and sent to the audio system via an integrator 15 consisting of a capacitor C1 and a resistor R1 and a low pass filter (LPF) 16.

In the embodiment, a waveform storage circuit 13 consisting of a ROM that stores in binary code is used, but instead, the waveform is inputted via a decoder to a waveform analog value storage circuit consisting of a voltage dividing circuit and an electronic switch, and processed in an analog manner. Direct LPF l 4
You can send it to 3.

As explained above, according to the present invention, the random address signal of the binary code output from the random address signal generation circuit as described above and the regular address signal from the address signal generation circuit are combined and the waveform is stored. into the circuit,
It is possible to obtain timbre changes with many amplitude values corresponding to the address signal, and it is possible to break the monotony of the conventional timbre of only two amplitude values and realize a rhythm sound source having a particularly tasteful timbre.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional example, FIG. 2 is a schematic explanatory diagram of an embodiment of the present invention, and FIG. 3 is a detailed explanatory diagram of the embodiment of FIG. is an exclusive OR circuit, 3
is an OR circuit, 4 is a NOR circuit, 5 is a clock generator, 6
, 16 is a low-pass filter, 10 is a random address signal generation circuit, 11□, 11□ is an address signal generation circuit,
12 is a control circuit, 13 is a waveform storage circuit, 14 is a D/A converter, 15 is an integrator, 21 is an address counter, 22 is a logic circuit, 23 is a shift register, and 24 is a clock frequency divider.

Claims (1)

[Scope of utility model registration request] A plurality of address signal generation circuits including at least one random address signal generation circuit that generates random addresses, and address signals from the plurality of address signal generation circuits that store predetermined waveforms and are selectively inputted to correspond to the address signals. 1. A rhythm sound source comprising a waveform storage circuit controlled to output a predetermined waveform with an amplitude value.