JPH0745636A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a field-effect transistor which has such a planar gate that can suppress a long gate effect and is suitable for integration and a high gate breakdown voltage and high output. CONSTITUTION:A thin channel layer 13 containing an impurity at a high concentration is formed on a semiconductor substrate 11 and a cap layer containing a doping layer 15 is formed on the channel layer 13. The thickness and impurity concentration of the doping layer 15 are controlled so that the doping layer 15 itself can be depleted by a surface depletion layer resulting from the interface level of the surface of the substrate 11 and the surface depletion layer cannot spread to the channel layer 13. In addition, the thickness of the cap layer is made within the range of 450-1,200Angstrom .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET), and more particularly to the structure of a field effect transistor suitable for integration and having a high output and a high gain.

[0002]

2. Description of the Related Art A Schottky barrier field effect transistor (MESFET) using a compound semiconductor has attracted attention for its high speed and low power consumption. It is applied to etc. To increase the output and efficiency of the MESFET, the resistance between the source electrode and the gate electrode, that is,
The source resistance (Rs = ΔV _GS / ΔI _DS ) is reduced to increase the transconductance (gm) and the on-resistance (Rm).
It is important to reduce the _ON ) and increase the gate breakdown voltage (V _bd ) between the gate electrode and the drain electrode.

There is a MESFET proposed by the inventor of the present application as one that achieves an increase in transconductance in a planar structure (Japanese Patent Laid-Open No. 4-22553).
No. 3). This MESFET is a so-called pulse-doped ME in which a cap layer is provided on a thinned channel layer.
In the SFET, a doping layer for suppressing the spread of the surface depletion layer is provided in the cap layer. With such a structure, the long gate effect can be suppressed, and thereby the transconductance can be increased.

[0004]

However, in the above-mentioned prior art, sufficient consideration has not been given to increasing the gate breakdown voltage. As a result, the gate breakdown voltage may become insufficient in an attempt to increase the transconductance.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a field effect transistor having both a sufficiently large transconductance and a high gate breakdown voltage.

[0006]

The FET of the present invention has been made in order to achieve such an object, and is formed by a thin channel layer having a high impurity concentration and formed on this channel layer. And a cap layer having a doping layer doped with impurities, and the thickness and the impurity concentration of the doping layer are determined by the surface depletion layer due to the interface state of the semiconductor substrate surface. The surface layer is depleted and has a predetermined thickness and a predetermined impurity concentration such that the surface depletion layer does not spread to the channel layer, and the cap layer has a layer thickness of 450 Å or more,
It is 1200 angstroms or less.

[0007]

[Function] The spreading of the surface depletion layer from the substrate surface to the deep part is blocked by this doping layer, the channel layer is not affected by the surface depletion layer, and only the depletion layer under the gate electrode affects the channel layer. become. Therefore, the so-called long gate effect does not occur. for that reason,
A large transconductance can be maintained even on the shallow side of the gate bias. The doping layer itself is depleted by the surface depletion layer, and the insulation between the gate and drain does not deteriorate.

Further, the thickness of the cap layer is preferably thin from the viewpoint of increasing the transconductance, and conversely, is thick from the viewpoint of increasing the gate breakdown voltage. If the thickness of the cap layer is 450 angstroms or more, a gate breakdown voltage of 10 V or more can be obtained, and
A transconductance of 100 mS / mm or more, which is 200 angstroms or less, can be obtained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a MESFET according to an embodiment of the present invention.
3 is a cross-sectional view showing the structure of the MESFET, and the manufacturing method of this MESFET is shown in the FET cross-sectional views in the respective manufacturing steps of FIG. This manufacturing method will be described below.

First, the semi-insulating GaAs semiconductor substrate 11
A non-doped GaAs buffer layer 12 is formed on it (see FIG. 2A). To form this buffer layer 12,
A crystal growth technique such as MBE (Molecular Beam Epitaxy) or OMVPE (Organic Metal Vapor Phase Epitaxial) is used to improve the carrier confinement property of the channel layer 13 described later. Each supply ratio is controlled so that the conductivity type is p-type. This GaAs
The carrier density of the buffer layer 12 is, for example, 2.5 × 10 5.
It is set to ¹⁵ [cm ^-3 ].

Next, the carrier density is 4 × 10 ¹⁸ [cm ^-3 ].
And the Si-doped GaAs channel layer 13 thinned to a thickness of 200 angstroms is used as the buffer layer 12.
Formed on. Subsequently, a non-doped GaAs layer 14 having a conductivity type of n type and a carrier density of 1 × 10 ¹⁵ [cm ⁻³ ] or less is formed on the channel layer 13 with a thickness of 150 Å (see FIG. 2B). ). A crystal growth technique such as the MBE method or the OMVPE method is also used for forming each of the layers 13 and 14.

Next, a doping layer 15 which is a Si-doped GaAs layer having a carrier density of 4 × 10 ¹⁸ [cm ⁻³ ] and a thickness of 50 Å is formed on the non-doped layer 14. The conductivity type is n on the doping layer 15.
A non-doped layer 16 having a carrier density of 1 × 10 ¹⁵ [cm ⁻³ ] or less is formed to a thickness of 500 Å (see FIG. 7C). The crystal growth technique similar to the above is also used for forming each of these layers 15 and 16. The non-doped layer 14, the doping layer 15, and the non-doped layer 16 formed on the channel layer 13 constitute the cap layer 50. Further, the thickness and the impurity concentration of the doping layer 15 in the cap layer 50 are such that the surface depletion layer resulting from the interface state on the substrate surface, that is, the surface of the cap layer 50 depletes the doping layer 15 itself, and The surface depletion layer does not extend to the channel layer 13.

Next, the gate electrode 17 is formed on the epitaxial wafer having such a laminated structure by using the vapor deposition technique, the lithography technique, the etching technique and the like. After that, an oxide or the like is formed on the side wall of the gate electrode 17, and Si ions are selectively ion-implanted on the substrate surface using the oxide or the like as a mask. By this ion implantation,
The n ⁺ type Si ion implantation layers 18 and 19 are formed (see FIG. 3D). At this time, the ion implantation layer 1 on the drain side
8 is formed at a position away from the gate electrode 17.

Finally, the same vapor deposition technique or lithography technique is used to form the drain electrode 20 and the source electrode 21 in ohmic contact with the ion implantation layers 18 and 19. By forming this electrode, the ME having the structure shown in FIG.
The SFET will be completed.

The ME according to this embodiment having such a structure
In the SFET, the gate electrode 17 is formed on the flat cap layer 50, and the MESFE having the planar structure is formed.
T is formed. Therefore, there is no drawback of the FET having the recess structure in the gate electrode portion, that is, the manufacturing yield is lowered due to poor uniformity and reproducibility due to recess etching.

Next, the MESF according to this embodiment will be described.
The operation of ET will be described below with reference to FIGS. 3 to 5 while comparing with a normal pulse-doped MESFET in which the cap layer 50 does not have a doping layer.

Here, the MESFET according to the present embodiment is shown in (a) of each of these drawings, and the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Also,
A known pulse-doped MESF is shown in FIG.
ET is shown. This pulse-doped MESFET
A thin channel layer 32 is formed on the GaAs semiconductor substrate 31 like the channel layer 13 according to the present embodiment, and a low impurity concentration cap layer 33 is formed on the channel layer 32. Ion implantation layers 34 and 35 similar to the ion implantation layers 18 and 19 in this embodiment are formed on both ends of the cap layer 33.
A gate electrode 36, a drain electrode 37, and a source electrode 38 are formed at the same relative positions as the respective electrodes in this embodiment, as in the case of this embodiment. 4 and 5, the reference numerals are omitted for ease of viewing the drawings, but the same reference numerals as those in FIG. 3 are attached to the respective portions.

In FIG. 3, the same negative gate voltage Vg is applied to the source electrodes 21 and 38 of the gate electrodes 17 and 36 of these MESFETs, and the depletion layer immediately below the gate completely closes the channel. It represents the state. That is, in the FET according to the present embodiment shown in FIG. 9A, the depletion layer shown by the oblique line immediately below the gate electrode 17 completely closes the channel layer 13, and the conventional FET shown in FIG.
Also in FIG. 7, the depletion layer shown by the oblique line immediately below the gate electrode 36 completely closes the channel layer 32. Here, in each FET, a surface depletion layer due to the interface state of the surface is formed between the gate electrodes 17 and 36 and the n ⁺ type Si ion implantation layers 18 and 34 on the drain electrode side, It is integrated with the depletion layer below the gate electrode value.

FIG. 4 shows the case where the gate voltage Vg is swung to the shallow side in each FET in the state shown in FIG.
That is, it represents the state of each depletion layer when the negative value having a large absolute value is changed to the negative value having a small absolute value.
The depletion layers immediately below the gates become shallower as the negative charges accumulated in the gate electrodes 17 and 36 decrease, and the channels of the current channel layers 13 and 32 open. When an appropriate voltage is applied to the drain electrodes 20 and 37 in this state, a current according to the applied voltage starts to flow between each drain and source.

FIG. 5 shows the state of each depletion layer when the gate voltage Vg is further shifted to the shallow side for each FET from the state of FIG. When the absolute value of the gate voltage Vg decreases and reaches a certain value, in the conventional MESFET shown in FIG. 5B, the depth of the depletion layer immediately below the gate electrode 36 and the channel layer 32 are spread. The depth of the surface depletion layer on the side of the drain electrode 37 becomes substantially equal. As a result, the short effective gate length La shown in FIG. 4B is changed to the long effective gate length Lb shown in FIG. 5B.
become. This is the so-called long gate effect. Due to this long gate effect, the conventional pulse-doped MESFET
The value of the transconductance gm at 1 is reduced, and the high frequency characteristic is deteriorated.

On the other hand, in the MESFET according to the present embodiment shown in FIG. 5A, the growth of the surface depletion layer from the substrate surface to the deep portion is blocked by the doping layer 15. Therefore, the channel layer 13 on the drain electrode 20 side is not affected by the surface depletion layer, and only the depletion layer immediately below the gate electrode 17 affects the channel layer 13. Therefore, the effective gate length Lc does not change, and the long gate effect does not appear unlike the conventional pulse-doped MESFET. Therefore, the value of the transconductance gm remains high until the current channel formed in the channel layer 13 is completely opened and the current is saturated. As a result, the high frequency characteristic is kept in a good state. At this time, since the doping layer 15 itself is completely depleted by the surface depletion layer, the insulation between the gate electrode 17 and the drain electrode 20 does not deteriorate. Therefore, the FE according to the present embodiment
At T, the drain breakdown voltage can be maintained high.

FIG. 6 is a graph schematically showing the gate voltage dependence characteristic of the transconductance gm when the gate bias is changed in this way. In the figure, the horizontal axis represents the gate voltage Vg [V] and the vertical axis represents the transconductance gm [ms / mm]. Further, the characteristic curve 41 shown by the solid line shows the characteristic of the MESFET according to the present embodiment, and the characteristic curve 42 shown by the dotted line shows the characteristic of the conventional pulse-doped MESFET. As can be seen from the figure, in the conventional MESFET, the value of the transconductance gm decreases on the side where the gate bias is shallow, that is, on the side where the gate voltage is close to 0 [V]. This is because the long gate effect occurs on the shallow side of the gate bias as described above. On the other hand, in the MESFET according to the present embodiment, the transconductance gm does not decrease even if the gate bias becomes shallow, and is maintained at a constant high value.

By the way, this type of FET is required to have a high gate breakdown voltage V _bd , particularly a gate breakdown voltage V _bd of 10 V or more. Experiments by the inventors have revealed that the higher the gate breakdown voltage V _bd , the higher the layer thickness of the cap layer 50 including the non-doped layer 14, the doping layer 15, and the non-doped layer 16. FIG. 7 is a graph showing the experimental results, in which the thickness of the cap layer 50 is plotted on the horizontal axis and the gate breakdown voltage V _bd is plotted on the vertical axis. As can be seen from this result, in order to obtain the gate breakdown voltage V _bd of 10 V or more, the cap layer 50 has a layer thickness of 450.
It turns out that it should be Angstrom or higher.

However, it has been found from the experiments by the inventors that the transconductance gm monotonically decreases as the thickness of the cap layer 50 increases. FIG. 8 is a graph showing the experimental results, in which the horizontal axis represents the thickness of the cap layer and the vertical axis represents the transconductance gm.
From this graph, when the thickness of the cap layer exceeds 1200 Å, the transconductance gm is 10
High output MESFET with 0mS / mm or less
As a result, sufficient gain cannot be obtained. Therefore, a high output MESFET having a high gain and a high gate breakdown voltage V _bd
In order to obtain the above, the layer thickness of the cap layer 50 is 450 to 1200.
Angstrom is preferable. By the way, in the above-mentioned embodiment, the layer thickness of the cap layer 50 is 700 angstrom, the transconductance gm of 210 mS / mm and the gate breakdown voltage V _{bd of} 12 V are obtained.

[0025]

As described above, according to the present invention, the spreading of the surface depletion layer from the substrate surface to the deep portion is blocked by the doping layer, the channel layer is not affected by the surface depletion layer, and the gate electrode is not affected. Only the lower depletion layer will affect the channel layer. Therefore, the conventional F
Unlike the ET, the long gate effect does not occur on the shallow side of the gate bias, and high transconductance can be maintained. Further, at this time, the doping layer itself is depleted by the surface depletion layer, and the insulation between the gate and the drain does not deteriorate. Therefore, according to the present invention, it is possible to provide a high output and high gain FET having excellent high frequency characteristics while maintaining the drain breakdown voltage high. Further, by setting the layer thickness of the cap layer in the range of 450 to 1200 angstroms, it is possible to obtain a high output MESFET having a well-balanced gain and a high gate breakdown voltage.

Further, a gate electrode is formed on the flat cap layer to form a planar structure FET. Therefore, it is possible to obtain an FET having uniform characteristics suitable for high integration without the drawbacks of the recess structure.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a MESFET according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the FET in each manufacturing process of the MESFET shown in FIG.

FIG. 3 is a FET cross-sectional view showing a state in which a channel is completely closed by a depletion layer in the FET according to the present embodiment and the conventional FET.

FIG. 4 is a FET cross-sectional view showing a depletion layer state when the gate bias is swung to the shallow side in the FET according to the present embodiment and the conventional FET.

5 is a FET cross-sectional view showing a depletion layer state in the case where the gate bias is swung further shallower than in the case of FIG. 4 in the FET according to the present embodiment and the conventional FET.

FIG. 6 is a graph showing the dependence of each drain conductance gm of the FET according to the present example and the conventional FET on the gate voltage Vg.

FIG. 7 is a graph showing the relationship between the layer thickness of the cap layer and the gate breakdown voltage V _bd of the FET according to this example.

FIG. 8 is a graph showing the relationship between the layer thickness of the cap layer and the transconductance gm of the FET according to this example.

[Explanation of symbols]

11 ... Semi-insulating semiconductor substrate (GaAs), 12 ... Non-doped buffer layer (GaAs), 13 ... Channel layer (S)
i-doped GaAs), 14 ... Non-doped layer (GaA)
s), 15 ... Doping layer (Si-doped GaAs), 1
6 ... Non-doped layer (GaAs), 17 ... Gate electrode, 1
8, 19 ... Si ion implantation layer, 20 ... Drain electrode, 2
1 ... Source electrode, 50 ... Cap layer.

Claims (1)

[Claims] 1. A field-effect transistor including a thinned channel layer having a high impurity concentration and a cap layer formed on the channel layer, wherein the cap layer is doped with impurities. The doping layer has a thickness, and an impurity concentration is such that the doping layer itself is depleted by a surface depletion layer caused by an interface state of a semiconductor substrate surface, and the surface depletion layer is formed in the channel layer. Has a predetermined thickness and a predetermined impurity concentration, and the cap layer has a layer thickness of 450 angstroms or more,
A field-effect transistor having a thickness of 1200 angstroms or less.