JPH0744524A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the power consumption in a clock generating circuit and to suppress undesired radiation noise while an oscillation stable time is reduced in the microcomputer incorporating the lock generating circuit. CONSTITUTION:The microcomputer 1a incorporates a clock generating circuit 10 with a high vibrator drive capability and a clock generating circuit 11 with a low drive force while suppressing the vibrator drive capability as clock generating circuits, and a changeover circuit 12 is operated so that the oscillation of the vibrator 2 is quickly started and made stable by the high drive force clock oscillation circuit 10 at the oscillation start and the oscillation of the vibrator 2 is maintained by the low drive force clock oscillation circuit 11 in the normal operation. Thus, the settling time at the start of oscillation is reduced and the current consumption in the oscillation circuit in the normal operation is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generating circuit, and more particularly to a microcomputer incorporating two types of clock generating circuits having different oscillator driving capabilities.

[0002]

2. Description of the Related Art Referring to FIG. 3, which is a block diagram showing a main part of a conventional microcomputer having a clock generating circuit, a microcomputer 1C has an external terminal X1.
The oscillator 2 is connected between the terminals X1 and X2, and the capacitive elements 3 and 4 are connected between the terminals X1 and X2 and the ground potential. External terminals X1 and X2
Is connected to the system clock generating circuit 14, and the system clock generating circuit 14 and the internal circuit 13 of the microcomputer 1C are connected by a clock signal line S3.

This conventional microcomputer 1C is
In the normal active state, the system clock generation circuit 14 oscillates at a predetermined frequency by the oscillator 2 connected to the terminals X1 and X2, and stops the oscillation when the standby mode which is the standby state is set. The output of the system clock generation circuit 14 is supplied to the internal circuit 13 of the microcomputer as the internal system clock S3.

[0004]

In the system clock generating circuit incorporated in the conventional microcomputer described above, when the oscillator starts oscillating by increasing the driving capability of the transistor used in the system clock generating circuit. The oscillation stabilization time of is shortened. Therefore,
Even if the transistor of the system clock oscillator circuit may have a low ability to drive the oscillator while the oscillation is stable, the oscillator with a high drive capability drives the oscillator. It has a drawback that the power consumed by the oscillation circuit increases and the power consumption of the microcomputer also increases.

Further, there is a drawback that a large unnecessary radiation noise is generated from the system clock.

The object of the present invention has been made in view of the above-mentioned drawbacks, and it is intended to shorten the oscillation stabilization time of the clock generation circuit and, at the same time, reduce the power consumption of the clock generation circuit and suppress unnecessary radiation noise. It is in.

[0007]

A feature of the present invention is that in a microcomputer having a clock generation circuit for controlling oscillation of one oscillator connected to the outside, the oscillator is oscillated with a high driving force. And a second clock oscillating circuit for oscillating the oscillator with a low driving force and first and second selection signals for activating or deactivating the first and second clock oscillating circuits. And a switching circuit that generates and outputs one of the output signals of the first and second clock oscillation circuits in response to these selection signals and supplies the selected output signal to the internal circuit of the microcomputer.

When the internal circuit is in the initial state, the first clock oscillator circuit is set to the active state and the second clock oscillator circuit is set to the stop state in response to the first selection signal. When the internal circuit is in the active state, the second clock oscillator circuit can be set to the active state and the first clock oscillator circuit can be set to the stop state in response to the second selection signal.

Further, the first and second selection signals are respectively supplied to the first and second clock generation circuits in response to a control signal supplied from the internal circuit set to the active state. It can also be supplied.

[0010]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. Referring to FIG. 1, a microcomputer 1a includes a clock generation circuit 10 having a transistor for driving an oscillator with high driving capability, a clock generation circuit 11 having a transistor for driving an oscillator with low driving capability, and these clock generation circuits. Generating selection signals S1 and S2 for bringing 10 and 11 into an active state or a stopped state, and generating clock oscillation circuits 10 and 11 in response to these selection signals.
And a switching circuit 12 which selects one of the output signals and supplies it to the internal circuit 13.

A vibrator 2 is provided between the external terminals X1 and X2.
However, the capacitance elements 3 and 4 are externally connected between the external terminals X1 and X2 and the ground potential, respectively. The external connection terminals X1 and X2 are connected to both the clock oscillation circuits 10 and 11, respectively. The output terminals of the clock generation circuits 10 and 11 are connected to the switching circuit 12, and the signal lines for transmitting the selection signals S1 and S2 are connected to both of the clock generation circuits 10 and 11 and the switching circuit 12, respectively. The output signal line of the switching circuit 12 is an internal circuit 13
And is configured to be supplied with the system clock S3.

That is, the microcomputer 1a of the present embodiment has two clock generating circuits 10 and 11 having different oscillator driving capabilities, and a switching circuit for selectively switching the oscillation of these clock generating circuits 10 and 11. 1
The addition of 2 is different from the conventional example.

Referring again to FIG. 1, in the microcomputer 1a, when the power is turned on or the standby mode is released, the switching circuit 12 has a high driving power.
A selection signal S1 that outputs 0 as an active state and a clock driving circuit 11 having a low driving force as a stop state is output. This selection signal S
The clock generation circuit 10 selected in response to 1 drives the vibrator 2 with a high driving force, so that the vibrator 2 is promptly driven.
Oscillation of the internal circuit 13
To the system clock S3 to activate the microcomputer 1a. At this time, the clock generation circuit 11 is in a stopped state in response to the selection signal S1.

Next, when the oscillation of the clock supplied from the clock generation circuit 3 to the switching circuit 12 becomes sufficiently stable,
The switching circuit 12 generates the selection signal S2 to activate the clock generation circuit 11 and deactivates the clock generation circuit 10. Since the clock generating circuit 11 in the active state has a small ability to drive the oscillator 2, the oscillator 2 is kept oscillating with low power consumption, and the system clock is supplied to the internal circuit 13 instead of the clock generating circuit 10. To continue.

Referring to FIG. 2 which is a block diagram of the second embodiment of the present invention, the microcomputer 1b of the present embodiment is configured to receive the supply of the switching circuit control signal S4 from the internal circuit 13. Is different from that of the first embodiment. The other constituent elements have the same structure as in the first embodiment, and the description thereof will be omitted.

Referring again to FIG. 2, when the power is turned on or the standby mode is released, the switching circuit 12 outputs the selection signal S1 in response to the switching circuit control signal S4 from the internal circuit 13 and responds to this signal. Then, the clock generation circuit 10 switches the clock oscillated with a high driving force to the switching circuit 12
To the internal circuit 13 as a system clock. At this time as well, the clock generation circuit 11 is in the stopped state. When the clock supplied from the clock generation circuit 10 is in a stable oscillation state, the internal circuit 13 outputs the switching circuit control signal S4 again, and in response to this signal, the switching circuit 1
2 supplies the selection signal S2 to the clock generation circuits 10 and 11. In response to this selection signal S2, the clock generation circuit 11 becomes active, oscillates the oscillator 2 with a low driving force, and supplies its output signal to the switching circuit 12. The switching circuit 12 continues to supply this signal to the internal circuit 13 as a system clock instead of the output signal of the clock generation circuit 11. At this time, clock generation circuit 10 is in a stopped state in response to selection signal S2.

[0018]

As described above, the clock generation circuit for embedding the microcomputer of the present invention comprises two types of clock generation circuits having different oscillator driving capabilities, and is supplied from the switching circuit or the internal circuit of the microcomputer. In response to the switching circuit control signal, the clock generator circuit is switched to oscillate the oscillator connected to the external terminal with a high driving force at the start of oscillation and with a low driving force after the oscillation is sufficiently stabilized. did. Therefore, the power consumption of the clock generation circuit in the active state is reduced, and unnecessary radiation noise from the oscillation circuit can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional microcomputer-embedded clock generation circuit.

[Explanation of symbols]

1a, 1b, 1c Microcomputer 2 Oscillator 3,4 Capacitive element 10 Clock generation circuit for oscillating oscillator with high driving force 11 Clock generation circuit for oscillating oscillator with low driving force 12 Switching circuit 13 Internal circuit 14 System clock Generation circuit S1, S2 selection signal S3 System clock S4 Switching circuit control signal

Claims (3)

[Claims] 1. A microcomputer having a clock generation circuit for controlling oscillation of one oscillator connected to the outside, comprising: a first clock oscillation circuit for oscillating the oscillator with a high driving force, and a low clock driving circuit for oscillating the oscillator. A second clock oscillating circuit for oscillating the oscillator and first and second selection signals for activating the first and second clock oscillating circuits are activated and responsive to these selection signals. And a switching circuit for selecting one of the output signals of the first and second clock oscillation circuits and supplying the selected output signal to an internal circuit of the microcomputer. 2. When the internal circuit is in an initial state, the first clock oscillation circuit is set to an active state and the second clock oscillation circuit is set to a stop state in response to the first selection signal, When the internal circuit is in the active state, the second clock oscillation circuit is set in the active state and the first clock oscillation circuit is set in the stopped state in response to the second selection signal. The microcomputer according to claim 1, wherein 3. The first and second selection signals are:
2. The microcomputer according to claim 1, wherein the microcomputer is supplied to each of the first and second clock generation circuits in response to a control signal supplied from the internal circuit set to the active state.