JPH04244779A - Power supply control circuit - Google Patents

Abstract

PURPOSE:To perform control so that the switching operation is reset automatically even if the switching operation of a switching circuit is interrupted abruptly due to the influence of noise by switching the connection of two capacitors between series connection and parallel connection. CONSTITUTION:When a power is turned ON, a half voltage of power supply voltage V appears at terminal D if capacitors C1, C2 are connected in series and a signal generating circuit, i.e., a frequency division circuit 3, starts frequency dividing operation to feed a clock signal to an internal circuit. When the frequency dividing operation of the circuit 3 is stopped, charging operation takes place so long as the capacitors C1, C2 are connected in series and a voltage V/2 appears at the terminal D thus resetting the frequency dividing circuit 3. When the capacitors C1, C2 are connected in parallel, they are discharged completely and the frequency dividing operation is stopped. But the capacitors C1, C2 are connected in series again by the output from a control circuit 1 and a voltage V/2 is applied on the frequency dividing circuit 3 which thereby resumes frequency dividing operation.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control circuit that controls a switching circuit so that even if the switching operation of the switching circuit suddenly stops due to the influence of noise or the like, the switching operation is automatically restored.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 4, the circuit configuration of an electronic watch aimed at reducing current consumption, for example, includes an oscillation circuit 20, a frequency dividing circuit 21, a level shifter 22, and a starting pulse generation circuit. 23 and two capacitors C1 and C2
and transistors T1 and T1 for alternately switching these two capacitors C1 and C2 between series connection and parallel connection.
It is equipped with a switching circuit 24 consisting of T2, T3, and T4. This is to ensure that a starting pulse is generated at terminal G of the starting pulse generation circuit 23 when the power is first turned on, and an "L" signal is output to terminal A for starting. That is, the switching circuit 24 is initialized by the "L" signal at the terminal A, and the capacitors C1 and C2 are connected in series and charged. From then on, the capacitors C1 and C2 are charged by pulses of a constant period from the frequency dividing circuit 21. By alternately connecting C2 in parallel and series, the power supply voltage can be reduced by 1/
The pressure is reduced to 2. This reduced voltage serves as a power source for the oscillation circuit 2 and the frequency dividing circuit 3, and low voltage driving is performed. Note that the display section and the like (not shown) require a relatively high voltage, and therefore are driven by applying the power supply voltage as is.

0003

However, in the conventional circuit configuration described above, when the capacitors C1 and C2 are connected in parallel (discharged state), if the oscillation or frequency division operation stops due to the influence of noise, etc., the capacitor C1 , C2 cannot be switched to series connection (charging state). In this case, the clock will remain stopped unless the power is turned on again.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to reliably switch two capacitors to series connection (charged state) even when switching operation suddenly stops, to enable the switching operation to be restored, and to maintain the reduced voltage. The purpose of this invention is to generate a clock signal using the power supply voltage to reduce power consumption.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the power supply control circuit of the present invention includes two capacitors for reducing the power supply voltage to 1/2, and a voltage reduced by each capacitor. A signal generation circuit that generates a clock signal as a power supply voltage, a switching circuit that alternately switches the connection state of each of the above capacitors between series and parallel based on the clock signal from the above signal generation circuit, and each of the above capacitors connected in parallel. and a control circuit that generates an output when the switching operation of the switching circuit stops and connects the capacitors in series.

[0006]

Embodiment In FIG. 1 showing a first embodiment of the present invention, an oscillation circuit 2, a frequency divider circuit 3 which is a signal generation circuit that generates a clock signal, a level shifter 4, a capacitor C1,
The configuration of C2 and transistors T1, T2, T3, and T4 that constitute the switching circuit 5 that alternately switches the capacitors C1 and C2 between the series state and the parallel state is the same as that in the case of FIG. 4, but the conventional starting pulse generation The control circuit 1 including three transistors P1, N1, and N2 is connected to the terminal D without connecting the circuit 23.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

First, when the power is turned on, the capacitor C
1 and C2 are connected in series, the power supply voltage V is applied to terminal D.
1/2 of the voltage is generated, and the frequency dividing circuit 3, which is a signal generating circuit, starts frequency division and supplies a clock signal to an internal circuit (not shown).

On the other hand, when the power is turned on, capacitors C1 and C2
are connected in parallel, no voltage is immediately applied to the frequency divider circuit 3. At this time, since the terminal D becomes "H", the transistor P1 of the control circuit 1 is turned off, the terminal E becomes a floating state, the transistor N1 is turned off, and the terminal F also becomes a floating state. The terminal F of the transistor N2 is in a floating state and “H”
Since the terminal F is currently in a floating state, the transistor N2 is turned on, the terminal E becomes "L", and the terminal B becomes "H". This is inverted by the level shifter 4, and the terminal A is turned on. An “L” signal is output. When an "L" signal is output at terminal A, transistors T2 and T4 are turned on, and capacitors C1 and C2 are connected in series. At this time, a voltage of V/2 is generated at terminal D, frequency division is started in frequency dividing circuit 3, and a clock signal is generated. In this way, even if the capacitors C1 and C2 are connected in parallel when the power is turned on, the control circuit 1 switches the capacitors C1 and C2 to be connected in series.

Next, the pulse signal supplied from the frequency dividing circuit 3 to the level shifter 4 is directly connected to the terminal A as shown in FIG.
is output to. When an "L" signal is generated at terminal A, transistors T2 and T4 are turned on, and capacitors C1 and C2 are connected in series. Further, when an "H" signal is generated at terminal A, transistors T1 and T3 are turned on, and capacitors C1 and C2 are connected in parallel. In this way, the capacitors C1 and C2 are alternately connected in series and in parallel by the pulse signal from the frequency dividing circuit 3, and are repeatedly charged and discharged. Capacitor C1 and C
In order to switch to series connection before the discharge of 2 ends,
The frequency dividing circuit 3 outputs a pulse signal with a sufficiently high frequency. Therefore, the signal level of terminal D is “H” and “L”
maintained at approximately an intermediate level.

It is assumed that the transistor P1 of the control circuit 1 is turned on when the signal level of the terminal D is from the above-mentioned approximately intermediate level to the "L" side. When the transistor P1 is turned on, the terminal E becomes "H" and the terminal B becomes "L". Note that at this time, the transistor N1 is in an on state and the terminal F is at "L", and the transistor N2 is in an off state.

The above is the normal operation after the power is turned on, and by this normal operation, the frequency divider circuit 3 continues to supply clock signals to internal circuits such as the drive circuit of the timepiece using the stepped-down voltage as the power supply voltage. In FIG. 2, a is when the power is turned on, b
indicates the start of the switching operation, c indicates the unstable operation period immediately after the start of the switching operation, d indicates the stable operation period, and e indicates the time when the switching operation is stopped.

Next, the operation when the frequency division of the frequency dividing circuit 3 is stopped during the above-mentioned normal operation will be explained. If the capacitors C1 and C2 are connected in series when the frequency division is stopped, charging is performed, so a voltage of V/2 is generated at the terminal D, and the frequency dividing operation of the frequency dividing circuit 3 is restored.

On the other hand, when the frequency division is stopped, the capacitor C
1 and C2 are connected in parallel, the battery is completely discharged and the terminal D becomes "H", no voltage is applied to the frequency dividing circuit 3, and the frequency dividing operation remains stopped.

By the way, when the terminal D becomes "H", the transistor P1 of the control circuit 1 is turned off, the terminal E is brought into a floating state, and the transistor N1 is turned off. As a result, the terminal F also becomes a floating state, the transistor N2 is turned on, the terminal E becomes "L", and the terminal B becomes "H". Here, it is assumed that the transistor N2 is turned on when the signal level of the terminal F is slightly on the "H" side from "L". by this,
The terminal A becomes "L", the capacitors C1 and C2 are connected in series again, a voltage of V/2 is applied to the frequency dividing circuit 3, and the frequency dividing operation is restarted.

By the above operation, capacitors C1 and C
Even if the switching operation of the switching circuit 5 stops when capacitors C1 and C2 are connected in parallel, the control circuit 1
By connecting the two in series, the switching operation can be reliably restored.

FIG. 3 shows another embodiment, in which a control circuit 1 comprising two transistors P2 and N3 and a resistor R is shown.
1 is connected to terminal D, and its circuit operation will be explained below.

First, when the power is turned on, capacitors C1 and C2
If they are connected in series, a voltage is generated at terminal D, the frequency dividing circuit 3 starts frequency division, and supplies a clock signal to an internal circuit (not shown).

On the other hand, when the power is turned on, capacitors C1 and C2
When are connected in parallel, no voltage is applied to the frequency divider circuit 3, but the transistor P2 of the control circuit 11 is turned off, and the signal level of the terminal E2 is weakly pulled to the "L" side via the resistor R. , the terminal B2 becomes "H", the transistor N3 is turned on, and the terminal E2 is further pulled to the "L" side. When terminal B2 becomes "H", terminal A becomes "L", and transistors T2 and T4 are activated as in the case of FIG.
turns on, capacitors C1 and C2 are connected in series, a voltage of V/2 is generated at terminal D, and frequency divider circuit 3
The frequency division operation is started at , and a clock signal is generated.

Subsequently, a high frequency pulse is outputted from the frequency dividing circuit 3 to the terminal A2, and the switching circuit 5 outputs the high frequency pulse to the terminal A2.
and C2 are alternately switched between series and parallel states. As a result, as in the case of FIG. 1, the signal level of the terminal D is maintained at an intermediate level between "H" and "L", and the transistor P2 of the control circuit 11 is turned on. The above is the normal operating state. At this time, the terminal E2 is "H", the terminal B2 is "L", and the transistor N3 is off.

Next, the operation when the frequency division of the frequency dividing circuit 3 is stopped during the above normal operation will be explained. Even if the frequency division is stopped, if the capacitors C1 and C2 are connected in series, charging is performed and a voltage of V/2 is generated at the terminal D, so that the frequency dividing operation of the frequency dividing circuit 3 is resumed.

On the other hand, when frequency division stops, capacitor C
If 1 and C2 are connected in parallel, they are completely discharged and the terminal D becomes "H", no voltage is applied to the frequency dividing circuit 3, and the frequency dividing operation remains stopped.

By the way, when the terminal D becomes "H", the transistor P2 of the control circuit 11 is turned off, and the terminal E becomes "H".
2 becomes "L", terminal B2 becomes "H", transistor N3 is turned on, and terminal E2 is further pulled to the "L" side. As a result, an "L" signal is generated at terminal A, capacitors C1 and C2 are connected in series again, a voltage of V/2 is applied to the frequency dividing circuit 3, and the frequency dividing operation is restarted.

By the above operation, capacitors C1 and C2
Even if the switching operation of the switching circuit 5 stops when the capacitors C1 and C2 are connected in parallel, the control circuit 11
can be connected in series and the switching operation can be reliably restored.

[0025]

According to the present invention, even if the connection switching operation of two capacitors suddenly stops, the two capacitors can be reliably connected in series and the switching operation can be resumed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

[Figure 2] Figure 1
Timing chart showing the signal status of each part of the circuit.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

[Figure 4] Circuit diagram showing a conventional example

[Explanation of symbols]

C1, C2 capacitor 1 Control circuit 3 Frequency divider circuit 5 Switching circuit

Claims (1)

[Claims] [Claim 1] 2 for reducing the power supply voltage to 1/2
a signal generation circuit that generates a clock signal using the voltage stepped down by each capacitor as a power supply voltage, and a connection state of each of the above capacitors is alternately connected in series and parallel based on the clock signal from the signal generation circuit. and a control circuit that generates an output when the switching operation of the switching circuit stops when the capacitors are connected in parallel, and connects the capacitors in series. circuit.