JPH0744266A - Device controller - Google Patents

Abstract

PURPOSE:To automatically decide the frequency of a clock according to the number of devices connected with a CPU. CONSTITUTION:A pulse generator 101 generates pulses delayed by each pulse width to devices 103-105 synchronously with an oscillator 108. The input of the pulse is short-circuited in each device, and outputted, and when the device is present at the output destination of the pulse, the output is inputted to a logical sum gate, and a logical sum signal is inputted to a counter 106 as an enable signal. The counter 106 counts synchronously with the oscillator 108 in the period of enable, and stores the result in the register of a clock diver 107. The clock driver 107 frequency-divides the signal of an oscillator 109 based on a value set at the register, and supplies the clock to each device. Thus, the clock can be automatically decided according to the number of devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device control device capable of determining the operating frequency of the devices, for example, by the number of devices connected to a bus line or the like.

[0002]

2. Description of the Related Art In a conventional device control device, for example, an information processing device, when the operating frequency of a device is determined by assuming the maximum number of devices (peripheral elements) to be connected, or when the number of devices increases due to expansion, etc. The operating frequency is determined by calculating the number and setting the operating frequency corresponding to the number of devices with a jumper switch or the like.

An example of a conventional frequency setting method will be described with reference to FIG. In FIG. 3, the user calculates the number N of devices connected to the devices 103 to 105. Then, the frequency specified or recommended by the system bus for the number of devices is determined, the register setting value for dividing the frequency of the crystal oscillator 109 to that frequency is checked, and the jumper switch 301
The clock driver 107 is set by. After performing these operations, the power was turned on and the device was started.

Further, conventionally, when changing an interface capable of controlling only data output to an interface capable of inputting / outputting, the interface is newly designed or an input port different from the existing output control interface is provided. It was provided with a data input section.

Furthermore, when connecting more external devices than the number of connectors provided in the apparatus, they are mechanically switched by a dedicated switching device or connected by a switching device which executes a dedicated control procedure for switching. Was there.

Further, in a system equipped with a plurality of devices having different connection forms and control methods, for example, FIG.
As shown in FIG. 9, when a plurality of devices 2105, 2106, 2107 having different connection forms and control methods are equipped, a control mechanism 2201 is connected to the device 2105,
The control mechanism 2202 was connected to the device 2106, and the control mechanism 2203 was connected to the device 2107. Therefore, the load of the signal line directly operated by the CPU increases as the number of devices equipped increases.

Further, for a plurality of devices having different connection forms and control methods, the CPU operates separately for each control mechanism.

[0008]

However, in the above conventional example, when the operating frequency is adjusted to the configuration of the maximum number of devices,
To envision devices to be added in the future, for example, even in a system that can operate at an operating frequency of 50 MHz, 25 MHz
However, there is a drawback in that the operation speed is lowered by operating at a low frequency.

Further, when the optimum operating frequency is adjusted according to the number of devices, it is necessary to calculate the number of devices for each expansion and change the operating frequency suitable for the number of devices with a switch or the like on the board. However, there is a drawback in that the probability of occurrence of troubles such as calculation errors and operation errors is increased, and the reliability of the device is lowered.

The present invention has been made in view of the above conventional example, and automatically sets the optimum operating frequency to the number of connected devices to improve the efficiency of the apparatus and to control the device with high reliability. A first object is to provide a device.

Further, when a new input / output interface is designed to control data input in a device having only an output interface, a large amount of cost is required and the existing output interface is wasted. .
When a new input section is provided, a port dedicated to input is required, and a new space is required for the board and port mounting section.

In view of the above-mentioned conventional example, a second object of the present invention is to add a data input section to an existing data output interface and control the data input timing to realize a bidirectional interface with one port. is there.

Further, in order to connect more external devices than the number of connectors provided, it is necessary to perform a manual switching in order to perform a mechanical switching, which requires extra labor for the operator. . When using a switcher that executes a dedicated control procedure, preparation such as setting the ID of a device to be connected in advance is required, and the switcher is also very expensive.

A third object of the present invention is to provide a device control apparatus in which the number of connectors can be easily increased in view of the above conventional example.

Further, in a system equipped with a plurality of devices having different connection forms and control methods, when the number of control mechanisms and devices connected to the signal line directly operated by the CPU increases, the load capacity of the signal line increases. , Stable operation becomes difficult. Furthermore, it has not been possible to simultaneously operate a plurality of devices having different connection forms and control methods.

In view of the above conventional example, a fourth object of the present invention is to provide a plurality of devices having different connection configurations and control methods,
It is to provide a device control device having a device control mechanism that stably and simultaneously operates.

[0017]

[Means for Solving the Problems] and

In order to achieve the above object, the device control apparatus of the present invention has the following configuration.

A device control device which operates in synchronism with a clock, wherein a generation means for generating a signal according to the number of connected devices, and the number of the devices based on the signal generated by the generation means It is provided with counting means for counting and means for determining the frequency of the clock input to the connected device according to the number of devices counted by the counting means.

Further, input / output means for inputting / outputting a signal, a plurality of connector means, selecting means for selecting a desired connector from the plurality of connector means, and the plurality of connectors based on the selection by the selecting means Connection means for connecting one of the means to the input / output means.

Further, a storage means for storing information of the connected device, a switching means for switching a control signal based on the information of the device stored in the storage means, and information of the device stored in the storage means. Based on the change, the changing means for changing the position, time and number of the signal line to be operated,
The control means controls the device described by the control signal switched by the switching means and the operation of the signal line changed by the changing means.

[0021]

[First Embodiment] FIG. 1 is a block diagram of an operating frequency determining circuit according to an embodiment of the present invention. The pulse generator 101 uses the signal CLK110 oscillated by the crystal oscillator 109 as a clock and shifts a rectangular pulse having a width of one cycle from the output line by shifting the clock by one cycle.
14-117. The latch 102 latches the pulse signal 117 generated from the pulse generator 101 and outputs a device reset signal DRST113. The devices 103 to 105 are connected devices. The counter 106 uses the output signal of the oscillator 108 as a clock, the output signal 118 of the OR gate 120 as an enable signal, and outputs the counted output as the register setting signal 119 of the clock driver 107. The clock driver 107 is a crystal oscillator 10
The output signal 9 is divided to generate a signal DCLK111 which is a clock input to each device. The reset signal / SRST112 is used for the pulse generator 101 and the latch 1
02 and is input. Detailed operation of the circuit configured as described above will be described later.

FIG. 2 is an example of a block diagram of the entire information processing apparatus which employs the operating frequency determining circuit according to the embodiment of the present invention. In FIG. 2, the circuit of FIG. 1 is assumed to be built in the CPU 201, but it is not limited to this. In the figure, a CPU 201 controls the entire device.
The memory control circuit 202 controls the memory 203 used as a program storage or work area. The DMA control circuit (Direct Memory Access Controller) 204 is
Data is transferred between the memory and the I / O without the control of the CPU 201. LAN interface 205
Interface between the LAN 214 such as Ethernet and the present apparatus. The I / O 206 is a ROM, SRAM,
These are I / Os such as RS232C. The disk interface 208 is with the hard disk 207, the printer interface 210 is with the printer 209, and the keyboard interface 211 is the keyboard 212 and the mouse 2.
The video interface 206 is an interface with the image display device 215. The devices are connected by the system bus 1.

In FIG. 2, the CPU 201 outputs the device reset signal / DRST and then outputs the RO in the I / O 206.
After performing a startup process such as a system check according to the program stored in M, the programs such as the OS stored in the hard disk 207 are loaded into the main memory 203.
Bring to. Thereafter, the application program operates according to the user's instruction from the keyboard 212 or the mouse 213.

Next, the operation of the frequency determining circuit of this embodiment will be described with reference to the timing chart of FIG. 4 and the flow chart of FIG. The apparatus of this embodiment is different from the conventional one in that the number of devices connected to the system bus is automatically detected and the frequency of the device corresponding to the number of devices is automatically determined.

Since the device does not operate during the reset period, in this embodiment, the period is used to determine the number of devices and the clock of the device before starting.

In FIG. 1, when the reset signal / SRST112 is negated at the timing t01 in FIG. 4, the pulse generator 101 causes the positive pulse shift signal 11
4 to 116 are output at timings t01 to t04.
Each of the devices 103 to 105 has two short-circuited terminals, one of which has a pulse generator 101.
By connecting the output signal from the OR gate and the other terminal to the input of the OR gate 120.
The output signal 118 of 20 will be output at a high level during a cycle period corresponding to the number of devices. By using this signal as the enable signal of the counter 106, the static eigenvalue 119 corresponding to the number of devices is obtained while being updated from timing t03 to timing t04.
The signal 119 is used as a register setting signal of the clock driver 107 so that the frequency division ratio of the clock driver 107 is determined according to the unique value 119 indicating the number of devices. The clock DCLK111 divided according to the value of the register of the driver 107 is supplied to each device. After the detection time of the number of devices is completed and DCLK111 is determined, the pulse signal 117 generated from the pulse generator 101 causes the latch 102 to negate the reset signal / DRST113 to each device at timing t05. When the reset period ends, the frequency of DCLK determined during that period is used as the system clock until the next reset.

The flow chart of FIG. 5 is based on the above description, and shows the setting operation of signals and the like and the output of signals in each unit as a flow chart.

As described above, by adopting the method of this embodiment, the number of devices is automatically detected during the device reset period, and the device frequency is automatically adjusted according to the value. Can be determined.

[0029]

[First Modification of First Embodiment] In the first embodiment, each device is provided with two terminals for device number determination, but the present invention is not limited to this. Since most signals of the system bus are not used during the reset period, the number of devices can be detected only by the signal of the system bus by using it for detecting the number of devices only during the reset period.

In the first embodiment, the system of FIG. 1 is used as it is, and the internal circuit of each device is constructed as shown in FIG. In FIG. 6, the address signal 602 and the data signal 603 of the device 601 are connected to the bus 1. The terminal 604 is a device reset signal / DRST11.
3 shows an input terminal of 3. Buffers 605 and 606 each represent an input / output buffer for address / data, and by adding a selector circuit 607, when / DRST113 is asserted, the address signal 602 becomes the data signal 603.
When the / DRST 113 is negated, the internal data 608 is output as the data signal 603 under the control of the output data control signal 609. That is, FIG.
1 is realized by using an unused address / data bus during the reset period as a short-circuited terminal of the devices 103 to 105 in FIG.

By preparing a set of address data unique to each device, the same effect as the above embodiment can be obtained.

[0032]

[Modification 2 of the first embodiment] In Modification 1, the address / data signal is used as a signal of the system bus used for detecting the number of devices during the reset period, but it is pulled up. If a signal is used, the same effect can be obtained when the number of signal lines required to determine the number of devices is only two.

FIG. 7 is a diagram best showing this embodiment. The blocks designated by the same reference numerals as those in FIG. 1 are the same as those in the first embodiment. In FIG. 7, the pulse continuous generator 7
01 outputs a continuous rectangular wave in synchronization with the clock 110. Also, the signals 703 and 704 are pulled up. The operation of the circuit of FIG. 7 will be described with reference to the timing chart of FIG.

/ SRST signal 112 becomes timing t11
When negated at, the pulse continuous generator 701 starts outputting a plurality of pulses at timing t12. Each of the devices 103 to 105 counts the number of input pulses unique to each device, and then, at timing t12 to t14,
One pulse is output as each of the ACK signals 705 to 707. A signal 70 obtained by pulling up these / ACK signals.
4 is used to obtain a logical sum signal 118, which is used as an enable signal for the counter 106. The counter 106 counts in synchronization with the clock signal 110 during the enable period, outputs the result as a signal 119, and outputs the signal to the driver 10
Write to register 7. The counter 106 is disabled at the time when the last / ACK signal is output from the connected devices, that is, at the timing t14, and a value corresponding to the number of devices is stored in the register of the clock driver 107. After that, the shift register 702 counts the number of pulses generated by the pulse continuous generator 701, and negates the reset signal / DRST113 to each device.

Next, the internal circuit of each device is shown in FIG. In FIG. 9, the / REQ signal 902 is pulled up by the resistor 904 and the / ACK signal 903 is pulled up by the resistor 904 in the device 901. Further, the device reset signal / DRST113 is input from the terminal 905. Buffers 906 and 907 represent input / output buffers for the pull-up signals 902 and 903, respectively. By using the logic gate 909 at a predetermined position of the output of the shift register 908, the number of pulses entering the / REQ signal 902 is counted by the number corresponding to the position of the gate 909 and a positive pulse is output. The output pulse of the gate 909 is directly output by the selector circuit 910 to the / ACK signal 903 when / DRST 113 is asserted.
When / DRST113 negates, internal / AC
The K signal 911 is output to the / ACK signal 903 under the control of the / ACK control signal 912.

With the above configuration, by preparing a shift register count value specific to each device, the counter 106 counts according to the number of devices, and the same effect as the above embodiment can be obtained.

[0037]

[Modification 3 of the first embodiment] Not limited to the method of automatically detecting the number of devices in the above-mentioned embodiment, a completely different method may be used as long as the same action is obtained. By providing the device with the pull-up terminals described below, the detection circuit can be shared by all devices.

FIG. 10 shows this embodiment. In FIG. 10, a resistor R10 having a constant value is provided for each of the devices 103 to 105.
One terminal pulled up by 01a to c is prepared and connected to the signal line 1002, and the resistance values R1001d and 1001 of the same value are also applied to the signal line 1002 on the substrate on which the device is mounted.
Pull up / down with e. Then, the signal line 10
The voltage level VS of 02 is output as a digital value 1004 by the A / D converter 1003. Assuming that the pull-up resistor power supply voltage is Vp and the number of devices is N, <when N = 0> VS = Vp / 2 <when N ≧ 1> Vs = Vp · (N + 1) / (RN-1
+ N + 1) where RN-1 represents R to the (N-1) th power.

The equation is established, and this equation is expressed in a graph as shown in FIG. As can be seen from this graph, VS and N have a one-to-one correspondence, and the number of devices can be calculated if the voltage level of VS is known.

Therefore, the clock driver 107 of the above-described embodiment is set so that the clock is output at a frequency suitable for the number of devices indicated by the digital value 1004 obtained by A / D converting the voltage level of VS. That is, output 1
A logic for converting 004 into an appropriate value to be set in the register of the clock driver 107 may be added to the circuit of FIG. With the above configuration, the same effect as that of the above-described embodiment can be obtained.

[0041]

[Second Embodiment] As a second embodiment of the present invention, an information processing apparatus in which an input interface is added to an output interface will be described with reference to the drawings.

FIG. 12 is a block diagram showing the configuration of the bidirectional interface of the present invention.

In FIG. 12, the CPU 1 controls each operation of the information processing apparatus having the bidirectional interface of this embodiment. The system controller 2 receives the control signal from the CPU 121 and controls the information storage medium and the expansion bus. The interface 123 controls only data output, and outputs data and inputs status information to an external device. The input / output port 124 is physically connected to an external device to exchange data and status. A CPU bus is provided between the CPU 121 and the system controller 122, and an expansion bus is provided between the system controller 122 and the interface 123 that controls data output. . Block 1 above
Depending on the configuration of 21 to 124, CPU bus, and expansion bus, C
Data output from the PU 121 to an external device is realized. The data input interface 125 is an interface newly provided in this embodiment for controlling data input.

Hereinafter, the CPU 121 when inputting data
The processing procedure by will be described in detail.

First, the CPU 121 issues a command as a normal data output to determine whether the external device connected to the input / output port 124 supports the bidirectional interface. The determination can be made by observing the status signal from the external device after issuing the command. When the bidirectional interface is supported, a data input command is issued and data from an external device is input from the input / output port 124. The input data is taken in by the CPU 121 via the newly provided input control interface 125 and CPU data bus.

At this time, the same I as in the conventional data output is used.
If data is input using the O address, it may collide with the data from the system controller 122 and input incorrect data. Therefore, the system controller 122 sends a ready signal to the CPU 121, which indicates the end of data transfer, to the data input interface 1.
25, and only when data is input from the input / output port 124, this Ready signal is sent as shown in the timing chart of FIG. 12B, and the * Ready signal is returned to the CPU 121. In the case other than the data input from the input / output port 124, the Ready signal is immediately sent to the CPU 121.
Return to.

The signal A is a group of signals input from the extended control bus for the input control interface 125 to determine whether or not the current data transfer is data input.

As described above, data can be input from the input / output port 124, and a bidirectional interface can be realized together with the existing output control interface.

[0049]

[Modification 1 of Second Embodiment] A modification of the apparatus of the second embodiment is shown in FIG. The same numbers are given to the same components as those in FIG. CPU data bus and system controller 12
A tristate buffer 126 is added between the two. The procedure for inputting data is almost the same as in the case of the second embodiment. The difference from the second embodiment is that when data is input using the same IO address as when outputting data, * Ready is newly provided in the above embodiment.
While the collision with the data output from the system controller 122 is avoided by the signal, in this modification, the data transfer from the system controller 122 to the CPU 121 is limited by using the tri-state buffer 126. Normally, the output of the buffer limit signal B from the input control interface 125 is "0". Only when data is input from the input / output buffer 124, "1" is output to the buffer limit signal B, and the system controller 122
Tri-state output from. The data from the input control interface 125 is set on the CPU data bus. The timing at which the CPU 121 fetches the data is the same as the timing at which the CPU 121 fetches the data from the system controller 122. As in the previous embodiment, signal group A is input by the input control interface 125 from the extended data bus to determine if the current data transfer is an input from the input / output port 124.

[0050]

[Second Modification of Second Embodiment] A second modification is shown in FIG. The same components as in FIG. 12 are assigned the same numbers. In this example, the data input from the input control interface 125 is
It is input to the CPU 121 through the system controller 122 via the extended data bus. In this case, on the expansion bus, the existing output control interface 123
Although the above-mentioned input data is input, there is no problem because the output control interface 123 does not operate during data input.

[0051]

[Third Modification of Second Embodiment] A third modification is shown in FIG. The same components as in FIG. 12 are assigned the same numbers. 12 to 1
In the case of 4, the same IO address as that at the time of output is used when inputting the data, but FIG. 15 shows an example in which a different IO address can be used. In the device of FIG.
The CPU address is decoded and the read command is issued in the input control interface 125, and the data input from the input / output port 124 is input to the CPU 121 via the CPU data bus.

As described above, according to the present embodiment and its modification, in the information processing apparatus having the interface capable of only outputting data, the interface for newly inputting data is provided and the data is inputted. A bidirectional interface that enables input / output transfer of data can be realized by controlling the timing of the data transfer.

[0053]

[Third Embodiment] A third embodiment will be described below with reference to the drawings.

FIG. 16 is an external view showing the structure of the connector extension system of the present invention. Connector expansion device 1602
Are attached to the information processing device 1601. The connector expansion device 1602 is connected to the existing connector 1603 of the information processing device 1601, and
02, additional connectors 1604 and 1605 are provided. In FIG. 16, the connector expansion device 1602 is directly connected to the information processing device 1, but it may be connected via a cable.

FIG. 17 is a block diagram showing the configuration when the system external device A1607 and the external device B1608 are connected to the additional connector of this embodiment. The additional connector switching circuit 1606 is configured in the additional connector device 1602.

FIG. 18 shows a block diagram of the extension connector switching circuit 1606. The STB signal and ACK signal in the figure are
This is a transfer protocol signal for data transfer between the information processing device 1601 and the external device A1607 (or B1608), and data transfer is performed by handshake. ST
The B signal is a signal output from the information processing device 1601, and the ACK signal is the external device A1607 (or B1).
This is a signal input from (608). RST is a reset signal, and the counter 1609 and the external device A 160
7 (or B1608) is initialized. Counter 1
In 609, when counting 5 and 10, “1” is output. The counter 1609 is reset (outputs "0") by the RST signal. The latch 1610 receives the output from the counter 1609, and when the count is 5 "1",
"10" is output at 10 count. Mask circuit 161
1 masks signals with a certain pulse width or less. The buffer 1612 selects the extension connectors A1604 and B1605 according to the output of the latch 1610.

The information processing device 1601 is capable of outputting STB signals having two types of pulse widths, STB (1) and STB (2), as shown in FIG. STB
(1) The signal is a normal transfer protocol signal, and this signal and A
External device A1607 (or B1 using CK signal)
608) and data transfer. The STB (2) signal is a signal for switching the extension connectors A1604 and B1605. The pulse width of the STB (2) signal is STB (1)
, Which is sufficiently small, and is masked by the mask circuit 1611.

The block diagram of FIG. 18 will be described while describing the sequence of selecting the actually added connectors A1604 and B1605 with the above configuration and transferring the data.

Before starting data transfer, add-on connector A
1604 and B1605 are selected. First, counter 1
The RST signal is output to reset 609. Next, the STB (2) signal is output from the information processing device 1601. When this signal is counted by the counter 1609 and is output five times in succession, the output of the latch 1610 becomes 1,
Select expansion connector B. When it is output 10 times in succession, the output of the latch 1610 becomes 0, and the extension connector A is selected. That is, the output of the latch 1610 serves as a switching signal for the extension connectors A and B. Since this STB (2) signal is unnecessary for data transfer, it is masked in the mask circuit 1611 and the external device A1607 (or B160) is used.
It is not output to 8). With the above, additional connector A160
4, the selection of B1605 is confirmed. ST in FIG.
Although only the B signal is described, additional connectors A1604 and B160 are provided for other signals on the interface by providing similar buffers 1612.
Either of 5 is selected.

After that, normal data transfer is performed. STB
Since the signal and the ACK signal are transferred by handshake for each cycle, the value of the counter 1609 is reset every time one cycle is transferred and does not continue counting up. Therefore, the switching signal does not change until all the data transfer tasks are completed and the next data transfer task starts, and the extension connector selected before the start of the current data transfer task remains selected.

As described above, the connector A160 added from the information processing apparatus 1601 using the data transfer signal.
4, external device A1607 connected to B1605,
B1608 can be switched and used.

[0062]

[Modification 1 of Third Embodiment] FIG. 20 shows a modification. Figure 1
6 to 19 are assigned the same numbers and names. In the embodiment of FIG. 20, an ACK that is normally an input to the information processing device 1601 as described in the third embodiment.
A mechanism is provided so that a signal can be output from the information processing device 1601 side. When output from the information processing device 1601 side, the ACK signal is the extension connector A1604, B16.
05 switching signal. In FIG. 20, the signal 102 is an ACK from the external device A1607 (or B1608).
Input signal, signal 101 is external device A1607
(Or B1608) for the ACK input signal,
A switching signal may be output from the information processing device 1601.

External device 1607 (or 1608)
In the case of the normal ACK from, the signal 101 is almost the same signal, although there is some delay with respect to the signal 102 as shown in the lower part of FIG. When the switching signal is output from the information processing device 1601, the signal 1 is output as shown in FIG.
01 changes, but signal 102 remains high. Therefore, the determination circuit 161 of the connector expansion device 1602
By confirming the change of the signal 101 and the signal 102 in 3, it is possible to determine whether it is the normal ACK input signal or the switching signal. If the ACK signal as the switching signal is provided with signals having different pulse widths, pulse numbers, etc., and these signals are output from the information processing apparatus 1, the respective extension connectors A1604 or B1605 can be selected.

From the above, the information processing device 1601 has a mechanism capable of outputting ACK signals having different pulse widths and pulse numbers.
By installing in the expansion connector A1604, B16
A plurality of external devices A1607, B1 connected to
Switching control of 608 can be performed from the information processing device 1601.

[0065]

[Modification 2 of Third Embodiment] FIG. 22 shows a second modification. The same numbers are given to the same components as those in FIGS. 16 to 18. In this embodiment, additional connectors A1604, B
This is an example in which a dedicated switching signal is provided for switching 1605. In this embodiment, signals which are not necessarily required for data transfer in the standard interface are added to the extension connector
It is used as a switching signal of 1604 and B1605. For example, a part of the ground line or the like can be used as the switching signal. In the case of an information processing apparatus that has the connector expansion device 1602 built therein and already has a plurality of connectors, the simplest circuit configuration is possible by adopting this embodiment.

[0066]

[Third Modification of Third Embodiment] Since the third embodiment and its first modification do not use a dedicated signal line for switching an additional connector, they are compatible with the conventional interface. In addition, the number of extension connectors can be relatively easily increased as compared with the modification 2 in which a dedicated switching signal is provided. For example, in the third embodiment, there are two extension connectors, but it is also possible to implement three or more. FIG. 23 shows a case where there are four expansion connectors. The same numbers are given to the same components as those in FIGS. 16 to 18. FIG. 23 is an extension of the third embodiment, and although the circuit configuration becomes a little complicated, it can be realized by the same idea as in the case of two expansion connectors. At the stage of selecting the extension connector before data transfer, if the STB (2) signal is counted 5 times, the extension connector A is counted 10 times, the extension connector B is counted, if it is counted 15, the extension connector C is counted 20 times. If so, the extension connector D is selected. By expanding in this way, the present invention can be applied to three or more extension connector systems.

As described above, according to this embodiment and the modification, it is possible to easily add a connector and easily control switching of a plurality of external devices connected to the imaged connector from the information processing apparatus. can do. For example, if the apparatus of this embodiment is used in the parallel interface, it is possible to simultaneously connect a monochrome printing apparatus and a color printing apparatus to the information processing apparatus,
Switching control of both printing devices can be performed from the information processing device.

[0068]

[Fourth Embodiment] FIG. 24 shows a device control mechanism with a bus conversion function 2401 according to a fourth embodiment (hereinafter, this control mechanism 240).
1) is shown. The control mechanism 2401 includes a CPU bus I / F unit 2402 and a main control unit 2403.
1, device information storage means 2404, signal information storage means 2405, device control means 2406, and signal information input / output means 2407. Bus I / F means 24
02 is the CPU bus control signal 2408 and the address signal 2
409 and the data signal 2410 can be input / output. The main control unit 2403 includes a bus I / F unit 2402, a device information storage unit 2404, and a signal information storage unit 240.
5, device control means 2406, signal information input / output means 2
407 can be controlled. The device information storage unit 2404 stores the device information received by the bus I / F unit 2402 and notifies the main control unit 2403 of the control method. The signal information storage means 2405 is the bus I / F means 24.
02 and signal information input / output unit 2407 can input / output an address signal or a data signal. The device control unit 2406 can change the control signal to the device according to the device information and input / output. The signal information input / output unit 2407 is a position of a signal line for inputting / outputting an address signal or a data signal according to device information,
The time and the number can be changed, and the signal information storage means 2
Signals can also be input / output to / from 405. If the device controlled here does not require an address signal with the same data line width as the CPU, the signal information storage means 2405 may be omitted. Signal 2408 is a bus control signal. The signal 2409 is an address signal. Signal 2410 is a data signal. Signal 2420 is a device control signal. The signal 2421 is an address signal. Signal 2422
Is a data signal.

FIG. 25 shows a block diagram of a system using the present control mechanism shown in FIG. Device 2102
Is directly connected to a signal line operated directly by the CPU 2101. The devices 2105, 2106, and 2107 are controlled by the control mechanism 2401. Device 2105
It is controlled by the device control signal 2423, the address signal 2424, and the data signal 2425. Device 2106
It is controlled by the device control signal 2426, the address signal 2427, and the data signal 2428. Device 2107
It is controlled by the device control signal 2429, the address signal 2430, and the data signal 2431. Signals 2423 and 242
6, 2429 is included in the signal 2420, and the signal 2424,
2427 and 2430 are included in the signal 2421, and the signal 24
25, 2428, and 2431 are included in the signal 22.
Each device connects only necessary signals from signals 2420, 2421, and 2422.

Next, the operation of the system of this embodiment will be described. 27 to 31 show operation flowcharts. First, the main operation flow shown in FIG. 27 will be described.

The CPU 2101 uses the devices 2105, 21.
When writing or reading data to or from any of 06 and 2107, first, it is confirmed whether or not the device information has already been written (step S302).
The write confirmation operation may be performed inside the CPU or may be confirmed by a signal from the control mechanism 2401 as long as the CPU 2101 can confirm the execution or non-execution of the writing. If the write operation has not been executed, the device information write operation is performed (step S303. The operation flow is shown in FIG. 28). It is confirmed whether it is necessary (step S304). When it is necessary, the address information write operation is performed (step S305. The operation flow is shown in FIG. 29). When the address is not needed or the address information write is completed, the actual device access is started (step S305). S306). CPU 2101 uses control signal 2408
-The address signal 2409 and the data signal 2410 are output. This control mechanism 2401 uses the signals 2408 and 2409.
The bus I / F means 2402 recognizes 2410 and determines whether it is a read command or a write command for the device (step S307). If it is a read command, a read operation is performed (step S308). If it is a write command, a write operation is performed (step S309). At the end of each operation, the CPU 2101 to the device 2105
Writing or reading to any of 106 and 107 is completed (step S310).

Next, the device information writing operation shown in FIG. 28 will be described. When the device information needs to be written to the control mechanism 2401, the CPU 2101 sends the signal 240
The device information write command is output using the 8/2409/2410 (step S321). Main control mechanism 2
The bus I / F unit 2402 recognizes the instruction 401 and stores the device information in the device information storage unit 2404.
Based on the information, the device information storage unit 2404 recognizes the device control method and notifies the control unit 2403 (step S323). In response to the notification, the main control unit 2403 outputs a device information write command end signal from the bus I / F unit 2402 to the CPU 2101, and the step S32 is performed.
4) The device information writing operation ends (step S325).

Further, the address information writing operation shown in FIG. 29 will be described. When the accessing device needs an address, the CPU 2101 sends the signal 2408.
409/2410 is used to output an address information write command (step S331). Main control mechanism 2401
Recognizes the instruction by the bus I / F means 2402 and stores the address information in the signal information storage means 2405 (step S
332). From the bus I / F means 2402 to the CPU 2101
An address information write command end signal is output to (step S333), and the address information write operation ends (step S334). Here, a device that requires an address is a device whose address signal specifies the data part, such as a mask ROM. is there.

The read operation shown in FIG. 30 will be described. The control mechanism 2401 starts the read operation when the bus I / F means 2402 recognizes that the read command is for a device controlled by the control mechanism 2401 (step S340). Device information storage means 2404
If the device specified by the device information stored in the device requires an address (step S34)
1), the signal information storage unit 2 is controlled by the main control unit 2403 notified of the control method from the device information storage unit 2404.
The address information stored in 405 is output from the signal information input / output unit 2407 as a signal 2421, and the device control signal is output from the device control unit 2406 to the signal 24.
It is output as 20 (step S342). If the device does not need an address (step S
341), under the control of the main control unit 2403 notified of the control method from the device information storage unit 2404, only the device control signal is output as the signal 2420 from the device control unit 2406 (step S343). The signal 2420,
Alternatively, both signals 2420 and 2421 cause devices 2105, 2106, and 2107 to signal 242 respectively.
3.2424, 2426/2427, 2429.243
When 0 is received, the selected device performs the read information output operation. Data signals 242425, 2428, 24
Readout information is output using the signal line connected to the device selected from among 31. Main control mechanism 24
01 takes in the read information from the device from the data signal 2422 to the signal information input / output means 2407 and stores it in the signal information storage means 2405 (step S344).
The read information is sent to the signal 24 from the bus I / F means 2402.
It is output as 10 (step S345). The signal 24
The CPU 2101 receives 10 and the read operation to the device ends (step S346).

The write operation shown in FIG. 31 will be described. When the bus I / F unit 2402 recognizes the write command to the device, the control mechanism 2401 starts the write operation (step S350). The write information received by the bus I / F means 2402 is stored in the signal information storage means 2405 (step S351). Device information storage means 24
If the selected device requires an address by recognizing the device information stored in 04 (step S352), it is controlled by the main control unit 2403 notified of the control method by the device information storage unit 2404. The address information stored in the signal information storage unit 2405 is output from the signal information input / output unit 2407 as a signal 2421, and the device control signal is output from the device control unit 2406 as a signal 2420 (step S35).
3). If the device does not need the address, the device control unit 2406 outputs only the device control signal as the signal 2420 under the control of the main control unit 2403 notified of the control method from the device information storage unit 2404 (step S354). Then, the signal information input / output unit 2407
The write information from the CPU is output as the signal 2422 (step S355). The signals 2420 and 242
2 or the signals 2420, 2421, and 2422 to the devices 2105, 2106, and 2107 respectively.
23/2424/2425, 2426/2427/24
Received as 28, 2429/2430/2431,
The selected device performs the write information input operation. The selected device receives signals 242425, 2428, 243.
The write information is fetched by the signal line connected to the first line. The write operation is completed by this operation (step S356). Here, this control mechanism 2401 is a bus I / F.
It is necessary to output the write command end signal from the means 2402, but this signal may be output any time after the write information is stored in the signal information storage means 2405 in step S351.

The above is the description of the operation of the control mechanism 2401.

When the device recognizes the address line and the data line in common by time division, the device side signal 2425 or 2428 or 2431 is not used. At this time, the signal information input / output means Address and data are output from 2407 to signal 2421 in a time division manner. The control is performed by recognizing the device information, and the main control unit 2
Reference numeral 403 manages an address / data switching signal.

As described above, in the system using this control mechanism, the load capacity of the CPU bus can be made constant regardless of the number of devices even if a plurality of devices having different connection forms and control methods are connected.

With the above structure, the operation of the system is stabilized because the load capacity of the CPU bus is constant regardless of the number of devices connected.

Further, the buffer memory required for each device can be shared.

Further, since the connection form and control are optimized for each device, the operation of the device becomes faster.

If the read operation to the device is performed immediately after writing the device information and the address information, when the CPU starts the read operation by the actual access operation to the device, the read data can be read in the minimum time. Can be output from the control mechanism to the CPU.

[0083]

[Modification 1 of Fourth Embodiment] FIG. 32 shows a block diagram of a device control mechanism 3400 with a bus conversion function (hereinafter referred to as the present control mechanism 3400) which is a modification of the fourth embodiment of the present invention. This control mechanism 3400 uses the CPU bus I / F means 34.
02, main controller 3401, and address information storage means 3
This is a device control mechanism including 403, device information storage means 3405, signal information storage means 3404, device control means 3406, and signal information input / output means 3407. The bus I / F unit 3402 has a CPU bus control signal 2408, an address signal 2409, and a data signal 24.
10 can be input and output. The main control unit 3401 includes a bus I / F unit 3402 and an address information storage unit 340.
3, it is possible to control the signal information storage means 3404, the device information storage means 3405, the device information storage means 240406, and the signal information input / output means 3407. Address information storage The address information storage means 3403 can store the address information assigned to the device controlled by the control mechanism 3400, and compare the address information with the address signal from the bus I / F means 3402. This makes it possible to determine which device is accessed. Device information storage Device information storage means 3
Reference numeral 405 stores the device information received by the bus I / F unit 3402, and notifies the main control unit 3401 of the control method. The address information storage means 3403 and the device information storage means 3405 can correspond to each other's information. The signal information storage means 3404 is the bus I / F means 3
Signal information can be input and output to and from the 402 and the signal information input / output unit 3407. Device control means 3406
Can change the control signal to the device according to the device information and input / output. Signal information input / output means 34
07 is the position and time of the signal line for inputting / outputting the address signal 2421 and the data signal 2422 according to the device information,
The number can be changed, and the signal information storage means 3404
Signals can be input and output to and from. Here, if the device controlled by the control mechanism 3400 has a signal line width equal to the data signal line width of the CPU, the signal information storage means 3404.
It doesn't matter. When the address information and the device information are sent as one data from the CPU, the address information storage means 3403 and the device information storage means 3
405 may be one storage means.

FIG. 33 shows the system configuration of this embodiment.
The device 4102 is a device that can be directly connected to a signal line operated by the CPU 4101. Device 210
Reference numerals 5, 2106 and 2107 are devices controlled by the control mechanism 3400. The device 2105 has a device control signal 2423, an address signal 2424, and a data signal 2.
Controlled at 425. The device 2106 is controlled by a device bus control signal 2426, an address signal 2427, and a data signal 2428. The device 2107 is controlled by the device control signal 2429, the address signal 2430, and the data signal 2431. Signals 2423, 2426, 2
429 is included in the signal 2420, and the signals 2424 and 242 are included.
7, 2430 is included in the signal 2421, and the signal 24242
5, 2428 and 2431 are included in the signal 22. Each device connects only necessary signals from signals 2420, 2421, and 2422.

Next, the operation will be described. FIG. 24 shows the main operation flow. The system starts from the place where it is reset (step S500). Main control mechanism 3400
Since neither device information nor address information has been written in, the CPU starts the device information writing operation (step S501). Then, the address information writing operation is started (step S502). The CPU confirms that there is no error signal from the control mechanism 3400 (step S50).
3). When there is no error signal, the actual device can be accessed. If there is the error signal, the process returns to step S501 again. However, since there is a risk of an infinite loop, a means for counting the number of errors and notifying the system user or the like at an arbitrary number may be provided somewhere in steps S501 to 503. In step S504, the control mechanism 3400 is in a real device accessible state. When a device controlled by the control mechanism 3400 is accessed from the CPU, the bus I / F means 3402, the address information storage means 3403, and the device information storage means 340.
It recognizes which device is accessed from 5. The bus I / F unit 3402 determines whether the actual device access is a read command or a write command (step S505).
If it is a read command, the process proceeds to step S506, and if it is a write command, the process proceeds to step S507. Step S5
When 06 and 507 are completed, the control mechanism 3400 enters the real device accessible state and moves to step S504. The end of the loop operation flow is a system reset such as power OFF. Here, the case where the control mechanism 3400 does not have the device information and the address information immediately after the reset has been described, but it may have the device information and the address information from the beginning. In this case, steps S501 to S403 are unnecessary.

FIG. 35 shows a device information writing operation flow. The CPU outputs a device information write command to the control mechanism 3400 (step S511). The control mechanism 3400 recognizes the instruction by the bus I / F unit 3402 and stores the device information in the device information storage unit 3405 (step S512). When the information storage is completed, the bus I / F unit 3402 outputs the write command end signal to the CPU (step S513). The CPU recognizes the end signal and ends the device information writing operation (step S514).

FIG. 36 shows an address information write operation flow. The CPU outputs an address information write command to the control mechanism 3400 (step S521). When the control mechanism 3400 recognizes the instruction by the bus I / F unit 3402, the main control unit 3401 confirms that the device information is already written (step S522). If the device information is written, the device information storage means 340
The address information is stored in the address information storage means 3403 while recognizing the correspondence with the device information 5 (step S523). When the storage of the information is completed, the bus I / F unit 3402 outputs a signal for the write command unit to the CPU (step S524). The CPU recognizes the end signal and the address information writing operation ends (step S
526). If the device information is not written, the bus I / F unit 3402 outputs an error signal to the CPU (step S525). The address information writing operation is also ended when the CPU recognizes the signal (step S526). The error signal output operation is C
Anything can be used as long as it can notify the PU of the occurrence of an error from the control mechanism 3400, such as an interrupt signal, or an error bit may be provided in a register and read by the CPU.

A case where the device information writing operation and the address information writing operation are performed in the reverse order in the main operation flow, that is, the device information writing operation is performed after the address information writing operation will be described. In the operation order, the operation flow of FIG. 35 becomes the address information writing operation,
The operation flow of FIG. 36 is the device information writing operation. However, the operation is such that the device information storage means 3405 and the address information storage means 3403 in the two operation flows are exchanged. When the address information storage means 3403 and the device information storage means 3405 are integrated, the device / address information write operation is performed in one operation flow of FIG. 35, and step S in the main operation flow.
Since 501 and S502 are integrated, step S503 is eliminated.

The read operation flow of FIG. 37 will be described.
During the main operation flow, the bus I / F unit 3402 and the address information storage unit 3403 allow the devices 2105 and 210 to operate.
When it is recognized that the access is to the 6, 2107 and is a read command, the read operation is started (step S530). The device information storage unit 3405 notifies the main control unit 3401 of the control method from the device information corresponding to the selected device (step S531). Under the control of the main control unit 3401 which has recognized the control method by the notification, the device control unit 3406 outputs a read control signal as a signal 2420, and the signal information input / output unit 3407.
The address signal is output as the signal 2421 (step S532). The signals 2420 and 2421 cause the devices 2105, 2106 and 2107 to receive the signal 24 respectively.
23/2424, 2426/2427, 2429/24
Upon receiving 30, the selected device performs a read data output operation. Data signals 2425, 2428, 24
Read data is output using the signal line connected to the device selected from among 31. Main control mechanism 3
The signal 400 is taken into the signal information input / output unit 3407 as the signal 2422 and stored in the signal information storage unit 3404 (step S533). The data signal is transferred to the bus I
The / F means 3402 outputs the signal 2410 to the CPU (step S534). The CPU fetches the signal, and the read operation ends (step S535).

The write operation flow of FIG. 38 will be described.
In the main operation flow, the bus I / F means 3402, 3 address information storage means 403 causes the devices 2105, 210
When it is recognized that the access is to 6, 2107 and it is a write command, the write operation is started (step S540). The write data signal is stored in the signal information storage unit 3404, and the control method is notified to the main control unit 3401 from the device information corresponding to the device selected from the device information storage unit 3405 (step S54).
1). The main controller 340 which has recognized the control method by the notification
Signal 2420 from the device control means 3406 under the control of 1
A control signal for writing to the device selected as is output from the signal information input / output unit 3407, and an address signal is set as the signal 2421 and a writing data signal is set as the signal 24.
22 is output. The signals 2420/2421/24
22 to the devices 2105, 2106, 2107 for the signals 2423, 2424, 2425, 2426, 24 respectively.
27/2428, 2429/2430/2431, and the selected device performs the write data input operation. The selected device is the data signal 2425,
Write data is taken in from the connected signal line of 2428 and 2431. The write operation is completed by this operation (step S543).

The above is the operation of the present embodiment.

Here, when the device recognizes the address line and the data line in common by time division, the signal 2425 or the signal 2431 on the device side is not used. At this time, the signal information input / output means 3407. Signal from 24
The address and data are output to 21 in a time division manner. The control is performed by recognizing the device information, and the main control unit 3401 manages the switching time between the address and the data.

As described above, in the system using this control mechanism, the load capacity of the CPU bus can be made constant regardless of the number of devices even if a plurality of devices having different connection forms and control methods are connected.

That is, according to the apparatus of the present embodiment, the operation of the system is stable because the load capacity of the CPU bus is constant regardless of the number of connected devices.

Further, the buffer memory required for each device can be shared.

Further, since the connection form and the control are optimized for each device, the operation of the device becomes faster.

Further, once the device information and the address information are written, the compatibility with the prior art can be completely taken from the viewpoint of software.

[0098]

[Modification 2 of Fourth Embodiment] FIG. 39 shows a block diagram of a device control mechanism 3600 with a bus conversion function (hereinafter referred to as the present control mechanism 3600) according to a modification 2 of the fourth embodiment 3 of the present invention. The control mechanism 3600 is a CPU bus I / F unit 36.
02, a main control unit 3601, and a device information storage unit 3
603, a command information storage unit 3407, a signal information storage unit 3405, a device control unit 3406, and a signal information input / output 3407. Bus I / F means 3
A CPU 602 can input and output a CPU bus control signal 2408, an address signal 2409, and a data signal 2410 to the CPU, and inputs a data signal to the device information storage means 3603, the command information storage means 3604, and the signal information storage means 3605. Can be output. Main control unit 3
A bus 601 can control the bus I / F means 3602, device information storage means 3603, command information storage means 3604, signal information storage means 3605, device control means 3606, and signal information input / output means 3607. The device information storage unit 3603 stores the device information received by the bus I / F unit 3602 and notifies the main control unit 601 of the control method. Each command information storage unit 3604 stores the command information for simultaneous operation from the CPU received by the bus I / F unit 3602, and notifies the main control unit 3601 of the content of the information. The signal information storage means 3605 can input / output signals to / from the bus I / F means 3602 and the signal information input / output means 3607. The device control unit 3606 can change the control signal to the device according to the device information and input / output, and can input / output a plurality of required signals at the same time. The signal information input / output unit 3607 can change the position, time, and the number of signal lines for inputting / outputting an address signal or a data signal in accordance with device information. Can input and output. Signal 8 is a bus control signal. Signal 2409
Is an address signal. Signal 2410 is a data signal. Signal 2420 is a device control signal. Signal 24
21 is an address signal. Signal 2422 is a data signal.

FIG. 40 shows a block diagram of a system using this control mechanism 3600. The CPU 2101 and the device 2102 are connected to the bus. Device 210
Reference numerals 5, 2106 and 2107 are devices controlled by the control mechanism 3600. Device 2105 has an address
A device control signal 242 that is a data line separation device
Controlled by 3 · address signal 2424 · data signal 2425. The address holding mechanism 3619 is the device 2105.
Address signal 2 when both device and device 2107 operate simultaneously
4 can be held by the hold signal 3621. The device 2106 is an address / data line separation device, and includes a device control signal 2426 and an address signal 242.
7. Controlled by data signal 2428. The address holding mechanism 3620 holds the address signal 2427 when the device 2106 and the device 2107 operate simultaneously.
2 can be held. Device 2107
The address / data line is the same device, and is controlled by the device control signal 2429 and the address signal 2430. Signals 2423, 2426, 2429, 3621, 3622
Is included in signal 2420, and signals 2424, 2427, 2
430 is included in the signal 2421, and the signals 2425 and 242 are included.
8 is included in signal 2422. Each device has signal 2
Only necessary signals from 420, 2421, and 2422 are connected.

Next, the operation will be described. 41 to 48 show operation flowcharts. First, the main operation flow of FIG. 41 will be described.

The CPU 2101 is the device 2105, 21.
When writing or reading information to or from any of 06 and 2107, first, it is confirmed whether or not the device information has already been written (step S63).
1). The write confirmation operation may be performed inside the CPU as long as the CPU can recognize the execution or non-execution of the writing, or may be confirmed by a signal from the control mechanism 3600. If the write operation has not been executed, a device information write operation is performed (step S632). FIG. 42 shows the operation flow. When the device information writing operation has been executed and ended, it is confirmed that the device to be accessed requires an address (step S633).
When it is necessary, the address information writing operation is performed (step S634. The operation flow is shown in FIG. 43). When the address is not required and when the address information writing is completed, it is confirmed that the simultaneous operation is performed (step S634). S635). In the case of simultaneous operation, a command information write operation for simultaneous operation is performed (step S636. The operation flow is shown in FIG. 44). It is confirmed that the device information of the simultaneous operation device designated by the command information is written without any shortage. Confirm (step S637). If there is a shortage, the device information write operation of the device required for the simultaneous operation is performed (step S638). If there is no shortage and if the write operation has ended, it is confirmed that the address information has been written without any shortage (step S639). If it is insufficient, the address information writing operation is performed (step S640). When there is no shortage and when the write operation is completed, command execution is started. First, it is confirmed whether the simultaneous operation is read or write (step S641). In the case of reading, the simultaneous reading operation is started (step S642). Figure 45
Shows the operation flow. In the case of writing, the simultaneous writing operation is started (step S643. The operation flow is shown in FIG. 46). When the operation ends, the main operation ends (step S647).

When the simultaneous operation is not performed in step S635,
The CPU initiates access to the device. The control mechanism 3600 confirms whether the access from the CPU to the device is read or write by the bus I / F unit 3602 (step S644). In the case of reading, the reading operation is performed (step S645; the operation flow is shown in FIG. 47). In the case of writing, the writing operation is performed (step S646). FIG. 48 shows the operation flow. When the operation ends, the main operation ends (step S647).

Next, the device information writing operation shown in FIG. 42 will be described. When the device information needs to be written to the control mechanism 3600, the CPU 2101 sends the signal 240
A device information write command is output using 8, 2409 and 2410 (step S651). Main control mechanism 3
The bus 600 recognizes the instruction by the bus I / F means 3602, and confirms that the instructions operate simultaneously (step S652). When operating simultaneously, the CPU stores device information in the device information storage unit 3603 as device information for simultaneous operation (step S653). If not operating at the same time, CP
Device information from U is stored in the device information storage means 3603.
It is stored as device information for main access in (step S654). Based on the information, the device information storage unit 360
3 recognizes the device control method and notifies it to the main control unit 3601 (step S655). In response to the notification, the main control unit 3601 outputs a device information write command end signal from the bus I / F means 3602 to the CPU (step S6).
56), the device information writing operation ends (step S657).

The address information writing operation shown in FIG. 43 will be described. When the accessing device needs an address, the CPU 2101 sends signals 2408, 2409, 2
An address information write command is output using 410 (step S661). This control mechanism 3600 is a bus I /
The F unit 3602 recognizes the command and confirms that the commands operate simultaneously (step S662). When operating simultaneously, CP
The address information from U is stored in the signal information storage means 3605 as address information exclusively for simultaneous operation (step S6).
63). If they do not operate simultaneously, the address information from the CPU is stored in the signal information storage means 3605 as the main access address information (step S664). When the storage of the information is completed, the bus I / F means 3602 causes the CPU 21
An address information write command end signal is output to 01 (step S665), and the address information write operation ends (step S666). Here, a device that requires an address is a device whose address signal specifies the data part, such as a mask ROM. is there.

The command information writing operation shown in FIG. 44 will be described. When the device to access needs an address, the CPU 2101 sends signals 2408, 2409 ,.
A command information write command is output using 2410 (step S671). This control mechanism 3600 is a bus I
The / F means 3602 recognizes the instruction and stores the command information in the command information storage means 3604 (step S67).
2). A command information write command end signal is output from the bus I / F means 3602 to the CPU 2101 (step S
673) and the write operation is completed (step S67).
4).

The simultaneous read operation shown in FIG. 43 will be described. In the simultaneous read operation, it is confirmed whether or not the address signal is switched during the simultaneous read operation (step S681). If the address is switched, the process proceeds to step S684, and if not, the process proceeds to step S682. In step S682, the device control unit 3606 outputs a simultaneous read control signal to the simultaneous operation device as a signal 2420, and if the signal information input / output unit 3607 stores the address information in the signal information storage unit 3605, the address signal is output as the signal 242.
Output as 1. Then, the address signal of the address / data line separation device is held at a predetermined time (step S
683) and the process moves to step S687. Step S6
At 84, the device control means 3606 outputs a read control signal to the address / data line separation device as a signal 2420.
If the address information is stored in the signal information storage unit 3605 from the signal information input / output unit 3607, the address signal is output as the signal 2420 to the address / data line separation device. In step S685, the device address signal is held. Step S686
Then, the device control means 3606 applies a read control signal to the same device of the address / data line to the signal 2420, and the signal information input / output means 3607 outputs the address signal 2
The address / data line 421 is changed to the same device address and is output. Then, the process proceeds to step S687.
In step S687, the signal information input / output unit 3607 stops the output of the signal 2421 and fetches the read data output by the same device of the address / data line from the signal 2421 and fetches the read data output by the address / data line separation device from the signal 2422. . The data is stored in the signal information storage means 3605. Step S688
Then, the bus I / F means 2402 outputs the data to the CPU, and the simultaneous read operation is completed (step S68).
9).

The simultaneous write operation of FIG. 46 will be described. C
Data for simultaneous writing is written from the PU to the control mechanism 3600 (step S691). The same data may be written to the devices to be written simultaneously, or may be different data. The data is stored in the signal information storage means 3605 (step S692). Next, access to the device is started. In step S693, it is confirmed whether or not the address is switched during the simultaneous writing operation. If the address is switched, the process proceeds to step S697, and if not, the process proceeds to step S694. In step S694, the device control unit 3606 outputs a simultaneous write control signal as a signal 2420 to the simultaneously operating devices.
In step S685, the device address signal is held. In step S686, the device control means 3606
A read control signal for the same device of the address and data lines is added to the signal 2420, and the signal information input / output means 36
From 07, the address signal 2421 is changed to the address for the same device of the address / data line and output. Then, the process proceeds to step S687. In step S687, the signal information input / output unit 3607 stops the output of the signal 2421 and fetches the read data output from the same address / data line device from the signal 2421 and fetches the read data output from the address / data line separation device from the signal 2422. The data is stored in the signal information storage means 3605. In step S688, the bus I / F unit 2402 outputs the data to the CPU, and the simultaneous read operation is completed (step S689).

The simultaneous write operation of FIG. 46 will be described. C
Data for simultaneous writing is written from the PU to the control mechanism 3600 (step S691). The same data may be written to the devices to be written simultaneously, or may be different data. The data is stored in the signal information storage means 3605 (step S692). Next, access to the device is started. In step S693, it is confirmed whether or not the address is switched during the simultaneous writing operation. If the address is switched, the process proceeds to step S697, and if not, the process proceeds to step S694. In step S694, the device control unit 3606 outputs a simultaneous write control signal as a signal 2420 to the simultaneously operating devices. In step S695, if the address information is stored in the signal information storage unit 3605 from the signal information input / output unit 3607, the address signal is output as the signal 2421, and for the address / data line separation device stored in the signal information storage unit 3605. The write data is output as the signal 2422. The address / data line separation device address is held (step S696), and the process proceeds to step S701. In step S697, device control means 3606
A write control signal is output as a signal 2420 to the address / data line separation device. Step S698
Then, the signal information input / output unit 3607 outputs the device address as a signal 2421 and the write data as a signal 2422. The device address is held (step S699). In step S700, the device control unit 3606 adds a control signal for writing to the same device of the address / data line to the signal 2420,
In the signal information input / output means 3607, the address signal 2421
Is changed to the address for the same device of the address / data line and is output, and the process proceeds to step S701. Step S7
In 01, the signal information input / output means 3607 causes the address signal 2
The address signal output to 421 is converted into the write data signal for the same device of the address and data lines. Therefore, the write data for the device is output to the address signal 2421, and the write data for the address / data line separation device is output to the data line. The respective devices take in the data and the simultaneous write operation ends (step S703). Here, the control mechanism 3600 needs to output the simultaneous write command end signal from the bus I / F means 3602, but this signal may be sent any time after the simultaneous write data is stored in the signal information storage means 3605 in step S692. .

The read operation shown in FIG. 47 will be described. The control mechanism 3600 starts the read operation when the bus I / F unit 3602 recognizes that the read command is for the device (step S710). If the device requires an address (step S711),
The address information stored in the signal information storage means 3605 is output as the signal 2421 from the signal information input / output means 3607. Further, a read control signal is signal 242 from the device control means 3606 under the control of the main control portion 3601 notified of the control method from the device information storage means 3603.
It is output as 0 (step S712). If the device does not need an address (step S7)
11), under the control of the main control unit 3601 notified of the control method from the device information storage unit 3603, the device control unit 3606 outputs a read control signal as a signal 2420 (step S713). The device 210 by the signal 2420, or both the signals 2420 and 21.
5, 2106 and 2107 are signals 2423 and 24, respectively.
24, 2426/2427, 2429/2430 are received, and the selected device performs a read information output operation. Data signals 2425, 2 depending on the selected device
Readout information is output using the signal line connected to either 428 or the address signal 2430. The control mechanism 3600 takes in the read information from the device to the signal information input / output unit 3607 from the data signal 2422 or the address signal 2421, and the signal information storage unit 360.
5 (step S714). The read information is output from the bus I / F means 3602 as a signal 2410 (step S715). The signal 2410 is sent to the CPU 21
01, the read operation to the receiving device ends (step S716).

The write operation shown in FIG. 48 will be described. When the bus I / F unit 3602 recognizes the write command to the device, the control mechanism 3600 starts the write operation (step S720). The write information received by the bus I / F means 3602 is stored in the signal information storage means 3605 (step S721). If the device requires an address (step S722), the address information stored in the signal information storage means 3605 is output as the signal 2421 from the signal information input / output means 3607. Further, under the control of the main controller 3601 notified of the control method from the device information storage means 3603, the device control means 3606 outputs a write control signal as a signal 2420 (step S723). If the device does not need an address, the device control unit 3606 controls the write control signal 24 by the control of the main control unit 3601 notified of the control method from the device information storage unit 3603.
It is output as 20 (step S724). Then, the write information from the CPU is output as the signal 2422 or 2421 from the signal information input / output unit 3607 according to the device (step S725). The signal 2420/2
421 and 2422 are connected to the signal 2423
2424/2425, 2426/2427/2428,
2429 and 2430 are received, and the selected device performs the write information input operation. The selected device fetches the write information from the connected signal line of the signals 2425, 2428, 2430. The write operation is completed by this operation (step S726). Here, the control mechanism 3600 needs to output the write command end signal from the bus I / F means 3602, but this signal may be sent any time after the write information is stored in the signal information storage means 3605 in step S721.

The above is the description of the operation of the control mechanism 3600.

As described above, in the system using this control mechanism, the load capacity of the CPU bus can be made constant regardless of the number of devices even if a plurality of devices having different connection forms and control methods are connected.

The address / data line same device and the address / data line separation device can be simultaneously operated.

That is, in the apparatus of this embodiment, the operation of the system is stable because the load capacity of the CPU bus is constant regardless of the number of connected devices.

Furthermore, the buffer memory required for each device can be shared.

Furthermore, since the connection form and control are optimized for each device, the operation of the device becomes faster.

Further, if the read operation to the device is started immediately after the device information and the address information are written, the read operation can be performed in the minimum time when the CPU starts the read operation in the actual access operation to the device. Data can be output from the control mechanism to the CPU.

Further, since the present control mechanism 3600 handles the data twice the data line width handled by the CPU by the simultaneous operation, even if the present control mechanism has a mechanism for inputting / outputting the double data, the CPU capable of handling the double data can operate. The control mechanism 3600 and the controlled device can be connected as they are.

[0119]

[Modification 3 of Fourth Embodiment] FIG. 49 shows a block diagram of a device control mechanism 3800 with a bus conversion function (hereinafter referred to as the present control mechanism 3800) according to Modification 3 of the fourth embodiment of the present invention. The control mechanism 3800 is a CPU bus I / F unit 380.
2, a main control unit 3801, and a command information storage unit 38
03, address information storage means 3804, device information storage means 3805, signal information storage means 3806,
Device control means 3807 and signal information input / output means 38
08 is a device control mechanism. Means 380
2 is a CPU bus control signal 2408 and an address signal 240
9 and the data signal 2410 can be input and output.
The main control unit 3801 includes a bus I / F unit 802, address information storage unit 3804, device information storage unit 3805.
Signal information storage means 3806, device control means 380
7. The signal information input / output unit 3808 can be controlled. The command information storage means 803 is the bus I / F means 3
The command information for simultaneous operation from the CPU received at 802 is stored, and the content of the information is notified to the main control unit 3801. The address information storage means 3804 is the control mechanism 38.
00, the address information assigned to the controlled device can be stored, and the address information and the bus I can be stored.
By comparing the address signal from the / F means 3802, it is possible to determine which device is accessed. The device information storage unit 3805 stores the device information received by the bus I / F unit 3802 and notifies the main control unit 3801 of the control method. Then, the device information is stored so that it can be known which device has which address information. The signal information storage means 3806 can input / output signal information to / from the bus I / F means 3802 and the signal information input / output means 3808. Device control means 38
07 can change the control signal to the device according to the device information and can input / output. The signal information input / output unit 3808 is provided with the position, time, and signal line for inputting / outputting the address signal 2421 and the data signal 2422 according to the device.
The number can be changed, and the signal information storage means 3806
Signals can be input and output to and from. Here, when the address information and the device information are sent from the CPU as one data, the address information storage means 3804 and the device information storage 3805 may be one storage means.

FIG. 50 shows the system configuration of this embodiment.
The device 2102 is a device directly connected to a signal line operated directly by the CPU 2101. Device 210
Reference numerals 5, 2106 and 2107 are devices controlled by the control mechanism 3800. The device 2105 has a bus control signal 2423, an address signal 2424, and a data signal 242.
Controlled by 5. The device 2106 uses the bus control signal 2
Controlled by 426, address signal 2427, and data signal 2428. The device 2107 uses the bus control signal 242.
9. Controlled by address signal 2430. The address holding mechanism 3822 is controlled by the holding signal 3824, and the address holding mechanism 3823 is controlled by the holding signal 3825. Signals 2423, 2426, 2429, 3824, 3825
Is included in signal 2420, and signals 2424, 2427, 2
430 is included in the signal 2421, and the signals 2425 and 242 are included.
8, 2431 is included in the signal 2422. Each device connects only necessary signals from signals 2420, 2421, and 2422.

Next, the operation will be described. The main operation flow will be described with reference to FIG. The system starts from the place where it was reset (step S830). This control mechanism 38
Since neither device information nor address information is written in 00, the CPU starts a device information writing operation (step S831). Then, the address information writing operation is started (step S832). CPU is this control mechanism 380
Confirm that there is no error signal from 0 (step S
833). If there is no error signal, the process proceeds to step S834. If there is the error signal, the process returns to step S831 again. However, since there is a risk of an infinite loop, means for counting the number of errors and notifying the user of the system at an arbitrary number may be provided somewhere in steps S831 to 833. In step S834, it is confirmed whether or not a plurality of devices are simultaneously operated. If they operate simultaneously, the process proceeds to step S835. If they do not operate simultaneously, the process proceeds to step S838. CPU to operate simultaneously
Outputs a command information write command for simultaneous operation to the control mechanism 3800. The command information writing operation is performed by the output of the command (step S835). Step S83
At 6, it is determined whether the simultaneous operation is read or write. Any determination method can be used as long as it can be confirmed by the main control unit 3801. The normal control signal 2408 is used to determine the bus I / F unit 38.
02 may be recognized, or the command information may be included in the command information and recognized by the command information storage unit 3803. If the simultaneous operation is a read operation, the simultaneous read operation is performed (step S837), and if the simultaneous operation is a write operation, the simultaneous write operation is performed (step S838). When each operation is completed, the process returns to step S834 to wait for the next instruction. If not operating simultaneously in step S834, CP
U starts access to the device controlled by this control mechanism 3800 without writing the command information. The control mechanism 3800 recognizes that the instruction is not simultaneous operation using the bus I / F means 3802 and the command information storage means 3803, and proceeds to step S839. In step S839, it is determined whether the instruction is read or written by the bus I / F unit 3802. If it is a read command, a read operation is performed (step S840), and if it is a write command, a write operation is performed (step S841). When each operation is completed, the process returns to step S834 to wait for the next instruction. The end of the loop operation flow is a system reset such as power OFF.

FIG. 52 shows a device information writing operation flow. The CPU outputs a device information write command to the control mechanism 3800 (step S851). The control mechanism 3800 recognizes the instruction by the bus I / F unit 3802 and stores the device information in the device information storage unit 3805 (step S852). When the information storage is completed, the bus I / F means 3802 outputs the write command end signal to the CPU (step S853). Confirm that the CPU has written all device information (step S8)
54). If it has not been written, the process returns to step S851 and the device information that has not been written is written. If all device information has been written, the device information writing operation ends (step S855).

FIG. 53 shows an address information write operation flow. The CPU outputs an address information write command to the control mechanism 3800 (step S857). When the control mechanism 3800 recognizes the instruction by the bus I / F unit 3802, the main control unit 3801 confirms that the device information is already written (step S858). If the device information is written, the process proceeds to step S859, and if not, the process proceeds to step S862. In step S859, the address information is stored in the address information storage unit 3804, but this is performed while recognizing the correspondence with the device information in the device information storage unit 3805. When the storage of the information is completed, the bus I / F means 3802 outputs the write command end signal to the CPU (step S86).
0). The CPU confirms that the address information for all devices has been written (step S861). If it has not been written, the process returns to step S857 to write the address information that has not been written. When the address information for all devices has been written, the address information writing operation ends (step S863). If the device information is not written in step S857, the bus I / F unit 3
An error signal is output from the 802 to the CPU (step S
862). The address information writing operation is also ended when the CPU recognizes the signal (step S86).
3). The error signal output operation is performed by the CPU by the main control mechanism 38.
Anything can be used as long as it can notify the error occurrence from 00, it can be an interrupt signal, and an error bit is provided in the register C
You may make it read in PU.

A case where the device information writing operation and the address information writing operation are performed in the reverse order in the main operation flow, that is, the device information writing operation is performed after the address information writing operation will be described. In the operation order, the operation flow of FIG. 52 becomes the address information write operation, and the operation flow of FIG. 53 becomes the device information write operation.
Device information storage means 3805 in the two operation flows
And the address information storage means 3804 are replaced. Further, when the address information storage unit 3804 and the device information storage 3805 are integrated, the device / address information writing operation is performed by one operation flow in FIG. 52, and steps S831 and S83 are performed in the main operation flow.
2 becomes one and step S833 is eliminated.

The command write operation shown in FIG. 54 will be described. When the command write command is output from the CPU, the command write operation is started (step S86).
4). The control mechanism 3800 recognizes the instruction by the bus I / F means 3802 and stores it in the command information storage means 3803 (step S865). The command end signal is output from the bus I / F means 3802 to the CPU (step S86).
6). The CPU recognizes the signal, and the command writing operation ends (step S867).

The simultaneous read operation shown in FIG. 55 will be described. In the simultaneous read operation, it is confirmed whether or not the address signal is switched during the simultaneous read operation (step S871). If the address is switched, the process proceeds to step S874, and if not, the process proceeds to step S872. In step S872, the device control unit 3807 outputs a simultaneous read control signal to the simultaneous operation device as a signal 2420, and the signal information input / output unit 3808 outputs an address signal as a signal 2421. The address signal of the address / data line separation device is held at a predetermined time (step S873), and the process proceeds to step S877. In step S874, the device control unit 3807 outputs a read control signal to the address / data line separation device as a signal 2420, and the signal information input / output unit 3808 outputs an address signal to the device as a signal 2421. Step S
At 875, the device address signal is held. In step S876, the device control means 3807 applies a read control signal to the signal / data line same device to the signal 2420, and the signal information input / output means 3808 changes the address signal 2421 to a work address and outputs the address. Then, the process proceeds to step S877. In step S877, the signal information input / output unit 3808 stops the output of the signal 2421, fetches read data from the same address / data line device from the signal, and fetches read data from the address / data line separation device from signal 2422.
The data is stored in the signal information storage means 3806. In step S878, the bus I / F unit 3802 outputs the data to the CPU, and the simultaneous read operation is completed (step S879).

The simultaneous write operation of FIG. 56 will be described. C
Data for simultaneous writing is written from the PU to the control mechanism 3800 (step S881). The same data may be written to the devices to be written simultaneously, or may be different data. The data is stored in the signal information storage means 3806 (step S882). Next, access to the device is started. In step S883, it is confirmed whether or not the address is switched during the simultaneous writing operation. If the address is switched, the process proceeds to step S886, and if not, the process proceeds to step S884. In step S884, the device control means 3807 outputs a simultaneous write control signal as a signal 2420 to the simultaneously operating devices. The signal information input / output unit 3808 outputs the address signal as the signal 2421 and the address / data line separation device write data as the signal 2422.
After a predetermined time, the address / data line separation device address is held (step S885), and the process proceeds to step S889. If there is address switching in step S883, the device control means 3807 outputs a write control signal to the address / data line separation device, and the signal information input / output means 3808 holds the device address (step S887). The signal information input / output unit 3808 changes the signal 2421 into the address signal for the same device of the address / data line and outputs the address signal (step S888), and proceeds to step S889. In step S889, the address output from the signal information input / output unit 3808 to the address line is changed to the write data signal for the same device on the address / data line. Therefore,
The device write data is output to the address signal 2421, and the address / data line separation device write data is output to the data line. The respective devices import the data and the process ends (step S
890). Here, the control mechanism 3800 needs to output the simultaneous write command end signal from the bus I / F means 3802, but this signal is always output after the simultaneous write data is stored in the signal information storage means 3806 in step S882. good.

The read operation flow of FIG. 57 will be described.
During the main operation, the bus I / F unit 3802, the command information storage unit 3803, the address information storage unit 3804, and the device information storage unit 3805 are access to the devices 2105, 2106, and 2107 that are not in simultaneous operation, and a read command is issued. When it is confirmed that there is the read operation, the read operation is started (step S900). Main control mechanism 3
Reference numeral 800 identifies the device selected from the bus I / F unit 3802 and the address information storage unit 3804, and reads the device selected from the device control unit 3807 based on the device information stored in the device information storage unit 3805. Output a control signal. At this time, the signal information input / output unit 3808 outputs the address signal as the signal 2421 (step S901). The selected device receives the control signal in one of the signals 2423, 2426, 2429 and receives the data signal in the signals 2425, 2
It outputs as 428 and 2431. The control mechanism 3800 outputs the signal as a signal 2422 to the signal information input / output means 38.
It is input from 08 and is stored in the signal information storage means 3806 (step S902). The stored data signal is transferred to the bus I / F
The means 3802 outputs the signal 2410 to the CPU (step S903). The CPU inputs the signal and the read operation ends (step S904).

The write operation flow of FIG. 58 will be described.
During the main operation, the bus I / F means 3802, the command information storage means 3803, the address information storage means 3804, and the device information storage means 3805 cause the devices 2105, 2
When it is confirmed that the access is to 106 and 2107 and the command is a write command, the write operation is started (step S910). The write data signal is stored in the signal information storage means 3806 (step S911). In step S912, the device control unit 3807 of the control mechanism 3800 outputs a write control signal to the device selected based on the device information stored in the device information storage unit 3805 as the signal 2420, and outputs the signal information input / output unit. The address signal from the 3808 is the signal 2421
And a write data signal is output as a signal 2422. Controlled devices 2105, 2106
Reference numeral 2107 designates the control signal as signals 2423, 2426, 24.
29, and the address signal is received in the form of signals 2424, 2427, 2430. The device selected by the control signal and the address signal sends the write data signal to the signals 2425, 2428, 24.
Receive as 31. This completes the write command to the device (step S913). Here, the control mechanism 3800 needs to output the simultaneous write command end signal from the bus I / F means 3802, but this signal may be sent any time after the simultaneous write data is stored in the signal information storage means 3806 in step S911. .

The above is the operation of the fourth embodiment.

As described above, in the system using this control mechanism, the load capacity of the CPU bus can be made constant regardless of the number of devices even if a plurality of devices having different connection forms and control methods are connected.

The address / data line same device and the address / data line separation device can be simultaneously operated.

Furthermore, since the load capacity of the CPU bus is constant regardless of the increase in the number of connected devices, the operation of the system is stable.

Furthermore, the buffer memory required for each device can be shared.

Furthermore, since the connection form and control are optimized for each device, the operation of the device becomes faster.

Further, once the device information and the address information are written, if they are not operated at the same time, the compatibility with the conventional one can be taken from the viewpoint of software.

Further, since the present control mechanism 3800 handles the data twice the data line width handled by the CPU by the simultaneous operation, even if the present control mechanism has a mechanism for inputting / outputting the double data, the CPU capable of handling the double data will operate. The control mechanism 3800 and the controlled device can be connected as they are.

[0138]

As described above, the device control apparatus of the present invention has the effect of automatically setting the optimum operating frequency for the number of devices and improving the reliability of the apparatus.

Furthermore, there is an effect that a data input section can be added to the existing data output interface and the data input timing can be controlled to realize a bidirectional interface with one port.

Furthermore, there is an effect that a connector can be easily added.

Further, there is an effect that a plurality of devices having different connection forms and control methods can be operated stably and simultaneously.

[0142]

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus that is a first embodiment of the present invention.

FIG. 2 is a block diagram of the entire information processing apparatus that is the first embodiment of the present invention.

FIG. 3 is a block diagram of an example of a conventional information processing device.

FIG. 4 is a timing chart showing the processing of the first embodiment of the present invention.

FIG. 5 is a flowchart of the first embodiment of the present invention.

FIG. 6 is a block diagram of the inside of a device according to a modified example 1 of the first embodiment.

FIG. 7 is a block diagram of an information processing device of a modified example 2 of the first embodiment.

FIG. 8 is a timing chart showing the process of the second modification.

FIG. 9 is a block diagram of the inside of a device in Modification 2.

FIG. 10 is a block diagram of a modified example 3 of the first embodiment.

FIG. 11 is a graph showing the relationship between the number of devices N and the voltage level VS in Modification 3.

FIG. 12 is a block diagram of a system of a second embodiment.

FIG. 13 is a block diagram of a system of Modification 1 of the second embodiment.

FIG. 14 is a block diagram of a system of Modification 2 of the second embodiment.

FIG. 15 is a block diagram of a system of Modification 3 of the second embodiment.

FIG. 16 is an external view of the device according to the third embodiment.

FIG. 17 is a block diagram of a system according to a third embodiment.

FIG. 18 is a block diagram of a switching circuit according to a third embodiment.

FIG. 19 is a timing diagram of strobe signals of the switching circuit of the second embodiment.

FIG. 20 is a block diagram of a switching circuit according to a modified example 1 of the third embodiment.

FIG. 21 is a timing diagram of the switching circuit according to the first modification of the third embodiment.

FIG. 22 is a block diagram of a switching circuit according to a second modification of the third embodiment.

FIG. 23 is a block diagram of a switching circuit according to Modification 3 of the third embodiment.

FIG. 24 is a timing diagram of a switching circuit according to Modification 3 of the third embodiment.

FIG. 25 is a block diagram of a device control mechanism with a bus conversion function according to a fourth embodiment.

FIG. 26 is a block diagram of a system using a device control mechanism.

FIG. 27 is a main operation flowchart of the system of the fourth embodiment.

FIG. 28 is a flowchart of a device information writing operation by the system of the fourth embodiment.

FIG. 29 is a flowchart of address information writing operation by the system of the fourth embodiment.

FIG. 30 is a flowchart of a read operation by the system of the fourth embodiment.

FIG. 31 is a flowchart of a write operation by the system of the fourth embodiment.

FIG. 32 is a block diagram of a device control mechanism with a bus conversion function according to a first modification of the fourth embodiment.

FIG. 33 is a block diagram of a system using a device control mechanism according to Modification 1.

FIG. 34 is a main operation flowchart by the system of Modification 1 of the fourth embodiment.

FIG. 35 is a flowchart of a device information writing operation by the system of Modification 1 of the fourth embodiment.

FIG. 36 is a flow chart of an address information write operation by the system of Modification 1 of the fourth embodiment.

FIG. 37 is a flowchart of a read operation by the system of Modification 1 of the fourth embodiment.

FIG. 38 is a flowchart of a write operation by the system of Modification 1 of the fourth embodiment.

FIG. 39 is a block diagram of a device control mechanism with a bus conversion function according to a second modification of the fourth embodiment.

FIG. 40 is a block diagram of a system using a device control mechanism according to Modification 2.

FIG. 41 is a main operation flowchart for the system according to the second modification of the fourth embodiment.

FIG. 42 is a flowchart of a device information writing operation by the system of Modification 2 of the fourth embodiment.

FIG. 43 is a flowchart of address information writing operation by the system of Modification 2 of the fourth embodiment.

FIG. 44 is a flowchart of a command write operation by the system of Modification 2 of the fourth embodiment.

FIG. 45 is a flowchart of a simultaneous read operation by the system of Modification 2 of the fourth embodiment.

FIG. 46 is a flowchart of a simultaneous write operation by the system of Modification 2 of the fourth embodiment.

FIG. 47 is a flowchart of a read operation by the system of Modification 2 of the fourth embodiment.

FIG. 48 is a flowchart of a write operation by the system of Modification 2 of the fourth embodiment.

FIG. 49 is a block diagram of a device control mechanism with a bus conversion function according to Modification 3 of the fourth embodiment.

50 is a block diagram of a system using a device control mechanism according to Modification 3. FIG.

FIG. 51 is a main operation flowchart for a system according to Modification 3 of the fourth embodiment.

FIG. 52 is a flowchart of a device information writing operation by the system of Modification 3 of the fourth embodiment.

FIG. 53 is a flowchart of the address information writing operation by the system of Modification 3 of the fourth embodiment.

FIG. 54 is a flowchart of a command write operation by the system of Modification 3 of the fourth embodiment.

FIG. 55 is a flowchart of a simultaneous read operation by the system of Modification 3 of the fourth embodiment.

FIG. 56 is a flowchart of a simultaneous write operation by the system of Modification 3 of the fourth embodiment.

FIG. 57 is a flowchart of a read operation by the system of Modification 3 of the fourth embodiment.

FIG. 58 is a flowchart of a write operation by the system of Modification 3 of the fourth embodiment.

FIG. 59 is a block diagram of a conventional system in a fourth embodiment.

[Explanation of symbols]

101 pulse generator 102 latches 103 to 105 device 106 counter 107 clock driver 108, 109 crystal oscillator 110 output signal CLK of crystal oscillator 108 CLK 111 signal D obtained by dividing the output signal of crystal oscillator 109
CLK (clock to each device) 112 reset signal / SRST 113 device reset signal / DRST 114 to 117 pulse generator output signal 118 counter 106 enable signal / EN 119 clock driver 107 register setting signal 201 controlling the entire device CPU 202 Memory control circuit 203 Memory controlled by the memory control circuit 202 204 DMA control circuit (Direct Memory Acces) that transfers data between the memory and I / O without intervention of the CPU
s Controller) 205 Interface with LAN such as Ethernet 206 ROM, SRAM, RS232C, etc. I / O type 207 Hard disk 208 Interface with hard disk 209 Printer 210 Printer interface 211 Keyboard and mouse interface 212 Keyboard 213 Mouse as a pointing device 214 Local area network such as Ethernet 215 Image display device such as CRT 216 Interface of image display device 215 1 System bus connecting each device 301 Jumper switch 601 Device 602 Address signal 603 Data signal 604 Device reset signal / DRST113 input terminal 605 606 Address / data input / output buffer 607 Selector circuit 60 Internal data 609 Output data control signal 701 Pulse continuous generator 702 Shift register 703 Pull-up signal / REQ 704 Pull-up signal / ACK 901 Device 902 Pull-up signal / REQ 903 Pull-up signal / ACK 904 Pull-up resistor 905 Device reset signal / DRST113 terminal 906, 907 Pull-up signal input / output buffer 908 Shift register 909 Logic gate 910 Selector circuit 1001 Terminal 1002 pulled up by a constant value resistor R 1002 Terminal 1001 is connected Signal line 1003 A / D converter 1004 Digital output value of 1003 1005 Pull-up resistance power supply

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kun Fumio 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Kazuki Ota 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Yasuhiro Tani 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (6)

[Claims] 1. A device control device that operates in synchronization with a clock, the generating device generating a signal according to the number of connected devices, and the device controlling device based on the signal generated by the generating device. A device control apparatus comprising: a counting unit that counts a number; and a unit that determines a frequency of a clock input to a connected device according to the number of devices counted by the counting unit. 2. The generation means passes a signal delayed by a predetermined time for each device through a signal line short-circuited in the device, and outputs a logical sum of the signals depending on the number of devices. The device control apparatus according to claim 1, wherein the device control apparatus is a signal. 3. The device control apparatus according to claim 2, wherein the generation means has means for selectively short-circuiting a signal line of the device. 4. The device control apparatus according to claim 1, wherein the generation unit outputs a unique voltage according to the number of the devices. 5. Input / output means for inputting / outputting a signal, a plurality of connector means, selecting means for selecting a desired connector from the plurality of connector means, and the plurality of connectors based on the selection by the selecting means. A device control apparatus, comprising: a connection unit that connects one of the units to the input / output unit. 6. Storage means for storing information of a connected device, switching means for switching a control signal based on information of the device stored in the storage means, and information of the device stored in the storage means. On the basis of,
Change means for changing the position, time and number of signal lines to be operated, and control means for controlling the device described by the control signal switched by the switching means and the operation of the signal lines changed by the changing means. And a device control apparatus.