JP3039503B2 - Control device and control method in printer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control device and a control method for a storage device such as a DRAM, and more particularly, to an image forming system.
That is, the present invention belongs to the technical field of a control device and a control method of the DRAM and the like in a printer system including a CPU and a DRAM and the like .

[0002]

2. Description of the Related Art An example of such an image forming system includes a personal computer and a printer.
Printer systems can be mentioned. In this printer system, print data such as bitmap data is transmitted from a personal computer to a printer, and the print data is converted into printable data in the printer. Prints on recording paper etc.

Accordingly, the printer is provided with a storage device for storing the print data and for storing printable data, which is data obtained by converting the stored print data. Generally, a DRAM capable of increasing the capacity and speeding up is generally used as such a storage device. For example, a memory space capable of storing print data for one page of recording paper and printable data is used. It is composed of DRAM.

[0004] In such a printer, a video memory is provided for the purpose of further shortening the print execution time. As the video memory, a line memory capable of storing one line of printable data or a field memory capable of storing a plurality of lines of printable data is used. While the transmission is being performed, one line or a plurality of lines of printable data are read from the DRAM into the video memory and transmitted to the printer engine.

Therefore, such data transfer from the DRAM to the video memory is performed by using the print data of the DRAM.
Must be faster than the transfer to
(Direct Memory Access) The memory control circuit using a controller or the like directly transfers data of the video memory from the DRAM without the intervention of a CPU.

[0006]

However, the memory control circuit is configured to operate in synchronization with the system clock signal of the CPU. However, the video memory stores a clock corresponding to the dot diameter of the printer engine. It is configured to operate in synchronization with a video clock signal.

The reason why the video clock signal is used for the video memory is that the throughput varies depending on the specifications of each printer, and it is necessary to transfer printable data in accordance with the characteristics of each printer engine. is there.

Therefore, when data is directly transferred from the DRAM to the video memory, data transferred from the DRAM in synchronization with the system clock signal is sampled by the video clock signal in the video memory.
It is stored in the memory area of the video memory in synchronization with the video clock signal.

However, the system clock signal is
Since it is determined by the specifications of the CPU, a problem has arisen that the printable data cannot be sampled on the video memory side with the recent increase in the speed of the CPU.

That is, the video clock signal is a clock whose throughput is as fast as 82.3 MHz in the case of a 20-sheet machine, but is 41.7 MHz in a 10-sheet machine, 32.7 MHz in an 8-sheet machine, and 32.7 MHz in a 6-machine. 24.
5 MHz. For example, when the system clock signal is 33 MHz, accurate sampling could not be performed with respect to the above-described eight-sheet and six-sheet machines because they are slower than the system clock signal.

Therefore, in order to use a common memory control circuit in printers of all specifications, it is necessary to make settings so as to be compatible with a slow video clock.
The only solution was to divide the system clock signal.

For this reason, a low data transfer speed is set in terms of product specifications, even though high-speed data transfer is possible, or a memory control circuit having a different clock setting between a high-speed printer and a low-speed printer. There was a problem that it had to be used.

Therefore, the present invention solves the above problems,
While achieving commonality of the memory control circuit, and an object of the invention to provide the most system that put the printer system which can perform high-speed data transfer control device and a control method according to the respective throughput.

[0014]

A pudding according to claim 1 wherein:
In order to solve the above-mentioned problem, a control device in the printer system includes a printer system including image forming means for performing drawing based on image information in a dot matrix drawing region.
A first storage device that stores the image information, and a second storage device that stores the image information read from the first storage device as image information to be drawn by the image forming unit. A storage device, a storage device control unit that controls writing or reading of the image information to or from the first storage device or the second storage device based on a predetermined clock signal, and a control signal from the storage device control unit. A clock signal to be supplied to the storage device control means based on the non-image forming operation ,
The pudding during operation of storing image information to憶device
Reading of image information from the first storage device in response to a system clock signal of the
Characterized by comprising a clock signal switching means for switching the reference writing clock signal when the drawing of the dot interval by the image forming means at the time.

According to the control device in the printer system of the first aspect, first, at the time of non-image forming operation , that is, at the time of non-image forming operation ,
In the operation of storing image information in the first storage device ,
For example, when image information is transmitted from an external personal computer or the like, the storage device control unit outputs a control signal to the clock signal switching unit, and outputs a clock signal to be supplied to the storage device control unit to a system clock signal. Switch to. Therefore, the storage device control unit, the Purine
A control means Tashisutemu, for example, it is possible to control the first storage device based on the control signal outputted from the CPU or the like in a state in which such a synchronization CPU has been established, image information sent from an external personal computer The data is securely stored in the first storage device. On the other hand, during the image forming operation ,
At the time of reading image information from the first storage device ,
The storage device control unit outputs a control signal to the clock signal switching unit, and switches a clock signal supplied to the storage device control unit to a reference drawing clock signal for drawing the dot interval by the image forming unit. . Therefore, the first storage device that has been controlled based on the signal synchronized with the system clock signal during the non-image forming operation is controlled in synchronization with the reference drawing clock signal during the image forming operation. Thus, synchronization with the second storage device which is originally controlled in synchronization with the reference drawing clock signal is established. That is, the storage device control means stores the image information read from the first storage device,
The image information is stored in the second storage device as image information to be drawn by the image forming means. These storage devices operate on the basis of the reference drawing clock signal, and store the image stored in the first storage device. Make sure the information is secondary
Sampled and stored in a storage device. As described above, during the non-image forming operation, the storage device is controlled based on the system clock signal, so that the data transfer is performed without lowering the speed. Since both the storage device and the second storage device are controlled based on the reference drawing clock signal, even if the reference drawing clock signal is slower than the system clock signal, it is possible to reliably transfer the data from the first storage device to the second storage device. Is transferred. As a result, even when the reference drawing clock signal is different in each system, there is no need to change the configuration of the storage device control means, and an efficient printer system can be provided.

[0016] <br/> Ru controller put the printer system according to claim 2, in order to solve the above problems, in the control device in the printer system of claim 1, wherein the storage device control unit, From the first storage device to the second
A DMA (Direct Memory Access) controller for transferring image information to a storage device is provided.

According to the control device in the printer system according to the second aspect, the first device is used at the time of image formation.
The transfer of the image information from the storage device to the second storage device is performed by a DMA (Direct Memory Access) controller. Therefore, without the intervention of a CPU or the like,
Even when high-speed transfer is performed and the reference drawing clock signal is slower than the system clock signal,
The image information transferred from the A controller is reliably sampled and stored by the second storage device controlled in synchronization with the reference drawing clock signal.

[0018] Ru <br/> put the printer system of claim 3 control device, in order to solve the above problems, in the control device in the printer system of claim 2, to the clock signal switching means The output of the control signal is D
It is performed by an MA (Direct Memory Access) controller.

According to the control device in the printer system according to the third aspect, when the image forming operation is performed, the CP is controlled.
U or the like outputs a control signal to the DMA (direct memory access) controller to perform direct memory-to-memory transfer without the intervention of a CPU or the like. The DMA (direct memory access) controller that receives the control signal inputs the following signal. The transfer of the image information between the first storage device and the second storage device is performed.

First, a DMA (Direct Memory Access) controller outputs a predetermined control signal to a clock signal switching means, and supplies a clock signal to be supplied to a storage device control means to the drawing of the dot interval by the image forming means. Is switched to the reference drawing clock signal at that time.
Then, a DMA (direct memory access) controller transfers the image information read from the first storage device to the second storage device in synchronization with the reference drawing clock signal, and further transfers the image information to the second storage device. The image information is read at a timing synchronized with a signal.
As described above, after the switching to the reference drawing clock signal is performed by the control signal output from the DMA (Direct Memory Access) controller itself, the direct memory transfer synchronized with the reference drawing clock signal is performed. Therefore, reliable transfer of image information is always performed without synchronization loss.

According to a fourth aspect of the present invention, there is provided a control method for a printer system , comprising: an image forming unit configured to perform drawing based on image information in a dot matrix drawing area in order to solve the above problem. a control method in a printer system having, controls the first storage device based on a predetermined clock signal, a first storage step of storing the image information in the first storage device, based on a predetermined clock signal And controls the first storage device and the second storage device to store the image information stored in the first storage device in the second storage device as image information to be drawn by the image forming unit. In the second storage step, the clock signal in the control of each of the storage devices is changed during the non-image forming operation ,
When storing image information in the first storage device,
Reading the image information from the first storage device during the image forming operation , that is, reading the image information from the system clock signal of the printer system.
And a clock signal switching step of switching to a reference drawing clock signal when the image forming means draws the dot interval.

According to the control method in the printer system of the present invention, first, at the time of non-image forming operation, for example, image information is transmitted from an external personal computer or the like, and the image information is received. In the case of performing the process of storing the data in the memory, the clock signal used for controlling the first storage device is switched to the system clock signal, and
The transmitted image information is stored in the first storage device in a state synchronized with the clock signal of the stem . On the other hand, at the time of image forming operation, for example, when the image information stored in the first storage device is stored in the second storage device to be transferred to the image forming unit as a drawing target, the first storage device and the second storage device A clock signal used for controlling the storage device is switched to a reference drawing clock signal when the image forming unit draws the dot interval. Therefore,
The image information stored in the first storage device as described above is read out in synchronization with the reference drawing clock signal, and is sampled in synchronization with the reference drawing clock signal in the second storage device, and Stored in the storage device. As described above, during the non-image forming operation, since the control of the first storage device is performed based on the system clock signal, the data transfer to the first storage device is performed without lowering the speed, and the image formation is performed. In operation, the first
Since both the storage device and the second storage device are controlled based on the reference drawing clock signal, even if the reference drawing clock signal is slower than the system clock signal, it is possible to reliably transfer the data from the first storage device to the second storage device. Is transferred. As a result, even when the reference drawing clock signal is different in each system, it is not necessary to change the configuration of the control process of the storage device, and an efficient printer
A system can be provided.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 illustrates a printer system as an image forming system according to the present embodiment.
It is a block diagram showing a schematic configuration systems out.

This printer system comprises a printer device A surrounded by a dotted line in FIG. 1 and a host device 10 such as a personal computer connected to the printer device A, and outputs from the host device 10. This is a system in which print data is temporarily stored in a RAM of the printing apparatus A, and video data generated based on the print data is output to a print engine as appropriate, thereby performing a print process. Hereinafter, the configuration of the printer A will be described in detail.

The CPU 1 controls the components of the printer A such as the ASIC 5 based on the control program stored in the ROM 2. The CPU 1 controls the output of the address data and the means assigned to the address. Input / output of data and input / output of control signals to / from each means.

The ROM 2 is a memory for storing a control program as described above, and stores table data and the like in addition to the execution program.

The built-in RAM 3 as the first storage device stores
A work area required for the arithmetic processing by the PU 1 and a memory serving as a main memory in the data processing system. In this embodiment, a DRAM is used.

The extension RAM 4 as the other first storage device is a memory attached to increase the capacity of the main storage, and like the built-in RAM 3, a DRAM is used in this embodiment.

The ASIC 5 is an IC circuit provided to reduce the processing load on the CPU 1 and unique to the image forming system. The ASIC 5 is a memory control circuit 5a for controlling the ROM 2, the built-in RAM 3, and the extended RAM 4.
And an I / O control circuit 5b for controlling the switch panel 6, an engine control circuit 5c for controlling the print engine 7, and an interface control circuit 5d for controlling communication with the host device 10. Have been.

Each control circuit in the ASIC 5 is assigned a specific address in the image forming system, and can access each control circuit by accessing each specific address from the CPU 1. It has become.

The switch panel 6 is composed of display means provided on the panel section of the printer A, stitches and the like. The operation mode of the printer A is set by operating switches, or an error message is displayed on the display. Display etc. are performed.

The print engine 7 is an image forming means of an electrophotographic type or an ink jet type, and is a means for forming an image on a recording sheet based on video data output from the engine control circuit 5c.

Next, the configuration of the memory control portion in the above-described printer system will be described in more detail.

FIG. 2 is a block diagram of the CPU 1 shown in FIG.
FIG. 2 is a block diagram illustrating a memory control circuit 5a and an engine control circuit 5c of the ASIC 5, and peripheral circuits thereof, and a built-in RAM 3 and an extended RAM 4. In addition,
In FIG. 2, the built-in RAM 3 and the extended RAM 4 are described as “RAM 3 (4)” for simplification of description.
Hereinafter, these are collectively referred to simply as RAM3.

As shown in FIG. 2, the memory control circuit 5a of the ASIC 5 controls the RAM based on address data and control signals output from the CPU 1 during non-image formation.
3 is a circuit that controls the RAM 3 based on a control signal from a DMA controller 5e described later during image formation. Here, the time of non-image formation means, for example, when print data is transmitted from the host device 10,
This print data is received via the I / F control circuit 5d, temporarily stored in the RAM 3, and after storage, the print data is expanded into print executable data. Is not transmitted. In the image forming operation, the print executable data is transferred from the RAM 3 as the first storage device to the video memory 5g as the second storage device, and is transmitted to the print engine 7 as needed to execute the actual drawing operation. Say if you do.

The clock signal supplied to the memory control circuit 5a is configured so as to supply either the system clock signal SYSCLK or the video clock signal VCLK. This is performed by the selector 5f as switching means.

During the non-image forming operation, the clock signal supplied to the memory control circuit 5a is supplied to the selector 5
Switching to the system clock signal SYSCLK by f, the system clock signal SYSCLK is also supplied to the CPU 1. Therefore, the memory control circuit 5a operates in synchronization with the CPU 1, reliably reads the address data and the control signal output from the CPU 1, and controls the RAM 3 based on the address data and the control signal. . Specifically, by decoding the address data, the chip select signal is switched, or the read / write signal is switched,
An address strobe signal is output to RAM3.

The system clock signal SYSCLK is supplied to the CPU 1
And is supplied from the system clock signal oscillator 20. Also, as the system clock signal SYSCLK, a very high-speed clock signal has been adopted with the recent increase in specifications of CPUs. In the present embodiment, a 33 MHz clock signal is used. Then, the memory control circuit 5a and the RAM 3 operate in synchronization with such a high-speed system clock signal SYSCLK, so that the print data received from the host device 10 is stored and expanded into print executable data. Will be done very fast.

Here, the processing of expanding the print executable data refers to, for example, when the data transmitted from the host device 10 is bitmap data, decoding the bitmap data. In the present embodiment, when the print data for one page of the recording paper designated by the host device 10 is stored, the developing process into the print executable data is started.

The print executable data thus developed is transferred from the RAM 3 to the video memory 5g for each line when a data transfer request is received from the print engine 7, and the operation shifts to an image forming operation. Is configured to be performed.

That is, when the engine control circuit 5c receives a data transfer request from the print engine 7, the engine control circuit 5c outputs a direct data transfer processing request signal between memories to the DMA controller 5e. The DMA controller 5e receiving this signal inputs the signal to the CPU 1
When a bus release request signal is output from the CPU 1 and a bus release permission signal is input from the CPU 1, the CPU 1 controls the video memory 5g provided in the memory control circuit 5a and the engine control circuit 5c in place of the CPU 1.

As described above, the DMA controller 5e
During image forming operation, this circuit performs control so that print executable data stored in the RAM 3 is transferred to the video memory 5g of the engine control circuit 5c without the control of the CPU 1. Like the memory control circuit 5a, the DMA controller 5e is configured to be supplied with either the system clock signal SYSCLK or the video clock signal VCLK via the selector 5f. When the bus release permission signal is input, a control signal for switching the clock signal is output to the selector 5f, so that the clock signal output from the selector 5f is changed to the system clock signal SY.
Switching from SCLK to video clock signal VCLK.

The video clock signal VCLK is a clock signal corresponding to the dot diameter drawn by the print engine 7, and is a reference clock signal for drawing. The video clock signal VCLK is supplied from the video clock signal oscillator 21 to the engine control circuit 5c, and is supplied to the DMA controller 5e and the memory control circuit 5a via the selector 5f under the control of the DMA controller 5e as described above. You. The video clock signal VCLK is a clock signal that changes greatly depending on the characteristics of the print engine 7. For example, in a print engine having a throughput of 20 sheets per minute, 82.3 MH is used.
z, 41.7 for 10 print engines per minute
MHz, 8 print engines per minute.
7 MHz, or 24.5 MHz for a print engine with 6 sheets per minute. When the video clock signal VCLK is supplied to the engine control circuit 5c and supplied to the video memory 5g in the engine control circuit 5c,
In synchronization with the video clock signal VCLK, sampling and storage of print executable data and output to the print engine 7 are performed, and a print operation at a predetermined throughput is performed.

Here, the configuration of the video memory 5g in the present embodiment will be described in detail. FIG. 3 is a block diagram illustrating a configuration of the video memory 5g according to the present embodiment. As shown in FIG. 3, the video memory 5g is a RAM
3 that stores the data transferred from 3 for one row
Line buffer 30 and write line buffer 3
The memory includes a memory cell 31 for storing the data stored in 0 for each row or a plurality of rows, and a read line buffer 32 for outputting the data stored in the memory cell 31 for each row. Of these, Light Line
The buffer 30 and the read line buffer 32 are storage means constituted by a shift register or the like, and are configured so that the clock controller 34 supplies the video clock signal VCLK. That is, the write line buffer 30 and the read line buffer 32
Is a circuit for sampling or reading data read from the RAM 3 in synchronization with the video clock signal VCLK.

The memory cell 31 is a storage means having a memory cell similar to a DRAM and having a storage area specified by a row address. This row address signal is
The data is output from the memory controller 33, and the memory controller 33 has a write row counter 3
5. The row address data to be written, the row address data to be refreshed, or the row address data to be read are supplied from the refresh row counter 36 and the read row counter 37, respectively.

Writing of print executable data to the video memory 5g is performed under the control of the DMA controller 5e during image formation, as described above.
Basically, one line of data is stored in the write line buffer 30 while sampling the print executable data read from the RAM 3 in synchronization with the video clock signal VCLK. Memory cell 3
1 is performed. The clock signal serving as a reference at the time of writing is the video clock signal VCLK as described above, and is a signal different from the system clock signal SYSCLK supplied to the CPU 1.

Here, the video clock signal VCLK is used as the reference clock signal for the operation of the video memory 5g in the same configuration as in the prior art. However, as shown in FIG. The configuration is such that the clock signal VCLK is supplied.

Therefore, in the conventional system, a clock signal of an output system of print executable data to be sampled, that is, a system clock signal which is a clock signal used as a reference for operation of the RAM 3, the memory control circuit 5a and the DMA controller 5e. Since SYSCLK and the reference clock signal for the operation of the video memory 5g are different from each other, depending on the characteristics of the print engine 7,
There is a problem that the print executable data output from the RAM 3 cannot be properly sampled.

FIG. 7 shows an example of the sampling. The sampling is performed by the clock controller 34 shown in FIG.
The video memory 5 is synchronized with the rising edge of the system clock signal SYSCLK supplied from the MA controller 5e.
This is performed by reading the print executable data input to the data input terminal g at the rising edge of the video clock signal VCLK.

Therefore, for example, the system clock signal SY
SCLK is 33 MHz and video clock signal VCLK is 8
In the case of 2.3 MHz, as shown in FIG. 8, when print executable data is sampled at the rising timing of all video clock signals VCLK, the number of sampled data is two for the same print executable data. Or three, but there is no print executable data that cannot be sampled.

The video clock signal VCLK is 41.7.
Similarly, in the case of MHz, as shown in FIG. 8, the number of samples changes from one to two,
Sampling can be performed without skipping printable data.

Further, when the video clock signal VCLK is 32.
In the case of 7 MHz, as shown in FIG.
Although sampling can be performed at 1, t2 and t3, sampling cannot be performed at appropriate timings at timings t4 and t5. However, in this case, the system clock signal SYSCLK and the video clock signal
Since the difference between VCLKs is small, timings such as t4 and t5 occur less frequently, and may not be a problem depending on the sampling period.

However, when the video clock signal VCLK is 24.5 MHz, sampling can be properly performed at timings t6, t7, t8, and t9 as shown in FIG. Data cannot be sampled. Such a sampling error frequently occurs because the difference between the system clock signal SYSCLK and the video clock signal VCLK is large, which is a problem.

As described above, if one cycle of the video clock signal VCLK is longer than one cycle of the system clock signal SYSCLK, it is not possible to sample print executable data at an appropriate timing. Thus, one print executable data is output for two pulses. Therefore, even if the speed of the system clock signal SYSCLK is increased, the advantage cannot be reflected in the writing of data to the video memory 5g, and there is a problem that high-speed printing cannot be performed.

As a countermeasure against this problem, for example, in the example of FIG. 8, when the video clock signal VCLK is 82.3 MHz and 41.7 MHz, the system clock signal SYSCLK is used.
Is configured to output one print-executable data in one pulse, and the other lower video clock signal VC
It is conceivable that one print executable data is output to a print engine operated by LK in two pulses of the system clock signal SYSCLK. However, in this method, the configuration of the memory control portion of the ASIC 5 must be changed according to the characteristics of the print engine, and
There was a problem that C5 could not be shared.

Therefore, in the present embodiment, in order to solve the above-mentioned problem, a selector 5f is provided as a clock signal switching means, and a clock signal supplied to the memory control circuit 5a and the DMA controller 5e is changed as necessary. hand,
System clock signal SYSCLK and video clock signal VCLK
It was configured to switch between.

The switching of the clock signal is performed by a clock signal switching control signal output from the DMA controller 5e. After the DMA controller 5e secures the bus exclusive right of the system, the DMA controller 5e sends the signal to the memory control circuit 5a and the DMA controller 5e. The supplied clock signal is changed from the system clock signal SYSCLK to the video clock signal VCLK.
Is configured to be switched.

Hereinafter, the memory control processing according to this embodiment will be described with reference to the flowchart of FIG. 4 and the timing chart of FIG.

First, it is assumed that the system clock signal SYSCLK is supplied to the memory control circuit 5a and the DMA controller 5e when the power of the printer A is turned on.

When print data is received from the host device 10 via the I / F control circuit 5d (step S5).
1) The CPU 1 outputs a control signal for writing data to the memory control circuit 5a and address data of a write destination, and the memory control circuit 5a outputs the RAM 3 based on the control signal and the address data. The print data is stored in a predetermined area. Then, the stored print data is developed as print executable data.

Next, a data request for one raster (one line) from the print engine 7 is input to the engine control circuit 5c (step S2), and the engine control circuit 5c which has input this request sends the request to the DMA controller 5e. Then, a request to transfer one raster's worth of data from the RAM 3 to the video memory 5g is output (step S3).

Next, the DMA controller 5e
1 at the time when the CPU 1 outputs the bus release permission signal to the selector 5f (step S4), and outputs the clock signal to the selector 5f.
Output control signal to switch to LK (step S
5). Then, the DMA controller 5e performs a process of directly transferring the data of one raster from the RAM 3 to the video memory 5g (step S6).

That is, the DMA controller 5e outputs a control signal to the memory control circuit 5a so as to read data from the RAM 3, and in response, the memory control circuit 5a synchronizes with the video clock signal VCLK. At this timing, an address strobe signal or the like is output to the RAM 3.

Therefore, in the video memory 5g, R
As shown in FIG. 5, the print executable data is output from the AM 3 at the timing synchronized with the video clock signal VCLK, and the print executable data is sampled at the timing synchronized with the video clock signal VCLK. Become.

As described above, the RAM 5 and the video memory 5
g is directly transferred based on a video clock signal VCLK common to both systems, even if the value of the video clock signal VCLK changes according to the characteristics of the print engine, and the system clock signal
Even if the signal is slower than SYSCLK, it will be executed properly.

As described above, when the direct transfer of one raster data between memories is completed, the DMA controller 5e
Outputs a control signal to the selector 5f so that the clock signal supplied to the memory control circuit 5a and the DMA controller 5 is switched from the video clock signal VCLK to the system clock signal SYSCLK (step S7).

Then, the DMA controller 5 e
The bus release request signal output to U1 is stopped (step S8). As a result, the exclusive right of the bus is CPU
The state shifts to 1, and the print data can be stored from the host device 10 again.

Next, the engine control circuit 5c transmits printable data of one raster to the print engine 7, and the print engine 7 performs a printing operation (step S9).

Hereinafter, such processing is repeated until printing of one page is completed (step S10: NO).
The control ends when the printing of one page is completed (step S10: Yes).

As described above, according to the present embodiment, during non-image formation such as storage of print data from the host device 10, RA synchronized with the system clock signal SYSCLK is used.
Since the control of M3 is performed, a high-speed memory transfer can be performed with an increase in the speed of the system clock signal. Also, R
At the time of image formation in which print executable data is directly transferred from the AM 3 to the video memory 5g, not only the video memory 5g but also the memory controller 5a for controlling the RAM 3 and the reference clock signal of the DMA controller 5e are switched to the video clock signal VCLK. So print engine 7
Irrespective of the characteristics described above, it is possible to always execute appropriate memory transfer. Therefore, according to the configuration of the present embodiment, it is not necessary to change the configuration of the memory control unit according to the characteristics of the print engine 7, and a common ASIC 5 can be used. It is possible to

In the above embodiment, the memory control circuit 5 receives the system clock signal SYSCLK as it is.
Although an example in which the clock signal is used as the clock signal for the DMA controller 5e and the DMA controller 5e has been described, the present invention is not limited to this. You may comprise. With this configuration, the CPU
With the high performance of 1, the system clock signal becomes extremely high-speed, and even when the speed difference from the video clock signal becomes large, appropriate memory control can be performed.

The case where the selector 5f as the clock signal switching means is controlled by the DMA controller 5e has been described. However, the present invention is not limited to this, and the selector 1f is controlled by the CPU 1 to control the selector 5f. Is also good. However, when the configuration in which the selector 5f is controlled by the DMA controller 5e is adopted, it is possible to reliably prevent the timing of switching the clock signal from being shifted.

The video memory 5g in the present embodiment
Has been described as a DRAM-like device having a line buffer before and after a memory cell, but the present invention is not limited to this. For example, as shown in FIG. 6, a synchronous RAM having a capacity to store one line of video data may be used. The above-described video clock signal VCLK is used as a clock input to the synchronous RAM, and the synchronous RAM is read and written in synchronization with the clock.

Here, data writing from the DMA controller is performed via the memory controller 40.
Data transfer to the print engine 7 is performed by the memory controller 40 from the memory cell 41 by 1 word (32 bi).
This is achieved by reading data every t), converting the data from parallel to serial, and synchronizing with the video clock signal VCLK.

In the present embodiment, the case where the DRAM is used as the built-in RAM and the extension RAM has been described. However, the present invention is not limited to this, and various memories such as a synchronous DRAM can be used. . As the RAM, an appropriate RAM having one word of 1, 4, 16 bits or the like can be used, and various capacities can be used.

In this embodiment, the case where the present invention is applied to a printer system has been described. However, if the data processing system uses a storage device for setting the mode register as described above, another system may be used. Is also applicable. For example, the present invention is applicable to data processing systems such as personal computers, word processors, copiers, and communication devices.

[0077]

According to the control device of the printer system according to the first aspect, the first storage device for storing image information and the image information read from the first storage device are stored in the first storage device. A clock signal to be supplied to a storage device control unit that controls a second storage device that stores the image information to be drawn by the image forming unit ,
The Te storage operation when the smell of the image information <br/> to immediate Chi said first storage device to the system clock signal of the printer system,
Also, during the image forming operation , that is, when the image from the first storage device is
At the time of reading out information, the image forming means is configured to switch to a reference drawing clock signal when drawing the dot intervals. As a result, during the non-image forming operation, the data can be transferred without lowering the speed, and during the image forming operation, even if the reference drawing clock signal is slower than the system clock signal, Then, the image signal can be transferred from the first storage device to the second storage device. Therefore, even when the reference drawing clock signal is different in each system, there is no need to change the configuration of the storage device control means, and an efficient printer system can be provided.

According to the control device in the printer system of the present invention, the storage device control means transfers the image information from the first storage device to the second storage device. A direct memory access (DMA) controller is provided for performing high-speed transfer without the intervention of a CPU or the like. Even when the reference drawing clock signal is slower than the system clock signal, transfer from the DMA controller is performed. The sampled image information can be sampled and stored reliably.

According to the control device in the printer system according to the third aspect, since the output of the control signal to the clock signal switching means is performed by the DMA (Direct Memory Access) controller, the synchronization is lost. Therefore, it is possible to always surely transfer image information.

According to the control method in the printer system of the fourth aspect, the first storage device for storing image information and the image information read from the first storage device are stored in the first storage device.
The step of controlling the second storage device for storing as image information to be drawn by the image forming means is performed during a non-image forming operation , that is, storing the image information in the first storage device.
The system clock signal of said printer system is in operation, also during the image forming operation, i.e. the first memory instrumentation
At the time of reading image information from the device , the reading is performed based on a reference drawing clock signal at the time of drawing the dot interval by the image forming means. As a result, during the non-image forming operation, the data can be transferred without lowering the speed, and during the image forming operation, even if the reference drawing clock signal is slower than the system clock signal, Then, the image signal can be transferred from the first storage device to the second storage device. Therefore, even when the reference drawing clock signal is different in each system, there is no need to change the configuration of the storage device control process, and an efficient printer system can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a printer system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a storage device and a control device of the storage device extracted from the block diagram of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a video memory used in the printer system of FIG. 1;

4 is a flowchart showing a flow of control from reception of print data to completion of printing of one page in the printer system of FIG.

FIG. 5 is a timing chart of direct transfer between memories at the time of image formation in the printer system of FIG. 1;

FIG. 6 is a block diagram showing a configuration of another video memory used in the printer system of FIG. 1;

FIG. 7 is a block diagram illustrating a storage device and a control device of the storage device in a conventional printer system.

FIG. 8 is a timing chart for explaining a problem in direct transfer between memories during image formation in a conventional printer system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... ROM 3 ... Built-in RAM 4 ... Extended RAM 5 ... ASIC 5a ... Memory control circuit 5b ... I / O control circuit 5c ... Engine control circuit 5d ... I / F control circuit 5e ... DMA controller 5f ... Selector 5g ... Video memory 6 SW panel 7 Print engine 10 Host 20 System clock signal oscillator 21 Video clock signal oscillator

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification code FI G09G 5/12 G09G 5/12 (58) Investigated field (Int.Cl. ⁷ , DB name) B41J 5/30 G06F 3/12 G06F 13/28 310 G09G 5/00 510 G09G 5/12

Claims (4)

(57) [Claims] To 1. A dot-matrix of the drawing area, comprising an image forming means for drawing based on the image information flop
A control device in the linter system , wherein the first storage device stores the image information, and the image information read from the first storage device is stored as image information to be drawn by the image forming unit. Two storage devices,
Storage device control means for controlling writing or reading of the image information to or from the first storage device or the second storage device based on a predetermined clock signal; and storing the image information based on a control signal from the storage device control means. The clock signal to be supplied to the device control means is supplied during a non-image forming operation ,
During the operation of storing image information in the first storage device, a system clock signal of the printer system ,
During image forming operation , that is, image information from the first storage device
During the reading, characterized by comprising a clock signal switching means for switching the reference writing clock signal when the drawing of the dot spacing by said image forming means
Control device in printer system . 2. The apparatus according to claim 1, wherein said storage device control means includes a DMA (Direct Memory Access) controller for transferring image information from said first storage device to said second storage device. Printer according to 1
Controller in the system. Output of claim 3 wherein said control signal to said clock signal switching means, DMA (direct memory access) controller in the printer system of claim 2, characterized in that it is performed by the controller. To 4. A dot-matrix of the drawing area, comprising an image forming means for drawing based on the image information flop
A control method in a linter system , comprising: a first storage step of controlling a first storage device based on a predetermined clock signal and storing the image information in the first storage device; Controlling a first storage device and a second storage device to store the image information stored in the first storage device in the second storage device as image information to be drawn by the image forming unit; A storage step, and a clock signal in control of each storage device,
During non-image forming operation , that is, image information to the first storage device
During the storage operation , the system clock signal of the printer system is used.
A clock signal switching step of switching to a reference drawing clock signal at the time of drawing the dot intervals by the image forming means when reading image information from a storage device ;
A control method in a printer system , comprising: