JP2001134484A - Method and device for controlling memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently control a memory. SOLUTION: At the writing of print data from a host in a memory 1, whether or not the memory 1 is in an idle state is decided, and when it is decided that the memory 1 is in an idle state, the data of the writing address of data from the host are read from the memory 1, and held in a first data holding circuit 3, and the data from the host are held in a second data holding circuit 4, and whether or not the data in the first and second data holding circuits 3 and 4 are matched with each other is decided by a write data comparator circuit 5, and when decided that the both data are matched with each other, the data from the host are prevented from being written in the memory 1 so that the other operation, that is, the read operation of the data and the refresh of the memory can be operated during that time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method and device. The present invention relates to an ink jet printing apparatus that performs recording using a line recording head capable of discharging ink, and can be applied as a label printer or card printer that records on a label or card used in POS, FA, physical distribution, and the like. is there.

[0002]

2. Description of the Related Art For example, an ink-jet printing method using a line recording head capable of discharging ink is applicable as a label printer or a card printer for recording on labels or cards used in POS, FA, physical distribution, and the like. Devices are known, among which memory control devices are used. A frame memory in a page printer or the like requires a memory capacity capable of storing print data for one page of paper. The data received from the host is written to the memory by performing a memory write access, the written data is read from the memory by performing a read access, and the data is transferred to a print control unit for printing. This data transfer is related to the printing speed of the printer.

The method of write access and the method of read access differ depending on the memory, but what is generally called a DRAM method is an address multiplexer method, that is, a DRAM method.
A method is adopted in which one address input signal is time-divided by RAS (Row (row) address strobe) and CAS (Column (column) address strobe #) signals, thereby halving the number of address inputs and allocating addresses. WE (write enable), OE
This is a control method that operates in synchronization with a control signal such as (output enable).

In order to retain data, it is necessary to re-inject electric charge at regular intervals, and this re-injection is called refresh. By controlling the control signal of the DRAM system in accordance with the specification of the memory, a read cycle or a write cycle and a refresh can be performed.

When data is received from the host, the memory control unit receives a data write request signal from the interface control unit and performs write access to the memory to write data. Therefore, when data is transferred byte by byte, Write access is performed for each byte. When transferring print data to the print control unit, when transferring data on a byte-by-byte basis, read access is performed in accordance with a data transfer request signal from the print control unit, and data is read and transferred on a byte-by-byte basis. Further, as described above, the memory employing the DRAM method must be periodically refreshed. Thus, the memory will perform these three operations, which can occur with each request, resulting in operational conflicts.

Therefore, in order to control the memory, it is necessary to perform arbitration between three operations of reading data, writing data, and refreshing. For this purpose, three operation request signals, for example, a read request signal, a write request signal, and a refresh request signal are generated, and the signals are prioritized and sequentially processed. When data is transferred from the host, a write request is made to the memory, and a write operation is performed if writing is possible,
When data is to be transferred to the print head, a data read request is made to the memory, and if data can be read, a read operation is performed and data transfer is performed. When a data write request and a data read request occur at the same time, the conventional technique is to read the data and then write the data.

[0007]

However, in the above-described method, when the operations conflict with each other, the respective operations have to wait for each other, so that the system efficiency is reduced. When the system efficiency is reduced in this manner, the data transfer speed is reduced, and the printing speed is reduced. Contention between memory read, write, and refresh is a problem that will inevitably occur, and it is necessary to reduce the waiting time caused by the conflict.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory control method and device which solve the above problems.

[0009]

According to the present invention, data is read, written and refreshed by reading the data in advance at the timing when the data is actually required, that is, before the read / write request signal. Avoid conflicts.

[0010] Normally, an address is generated by incrementing or decrementing the image data, and when the data is read from the memory or the data is written to the memory, the next read address and write address are known. First, for a write cycle, data of a write address to be written next is read in advance and stored in the first data holding circuit. When the write data is determined, the data in the first data holding circuit is compared with the write data in the second data holding circuit. If the data is different, the data is written. If the data is the same, the data is not written. Since the next write address is determined after the previous data write, after the data comparison is completed, the data in the memory is read at the next write data address. When the next write data is determined, data comparison is performed. If they are different, data is written, and if they are the same, no data is written. By repeating this, data writing is performed. When performing data reading, data is read from the memory and stored in the third data holding circuit. When the data becomes necessary, the data is read from the third data holding circuit, and when the data of the third data holding circuit has been transferred by the system, the data at the next address is read and stored in the third data holding circuit. Refresh is performed by performing a distributed refresh, setting the refresh period to be shorter than a required refresh period, and performing refresh when neither reading nor writing is performed on the memory. The set time is determined by determining the maximum continuous time when reading and writing occur continuously, and is set with a margin based on the determination result.

According to a first aspect of the present invention, when writing external data to a memory, it is determined whether or not the memory is in an idle state, and if it is determined that the memory is in an idle state, The data of the write address of the data from the outside is read from the memory and held in the first data holding means, the data from the outside is held in the second data holding means, and the data in the first and second data holding means are read out. It is characterized in that it is determined whether or not the data matches, and when it is determined that the data in the first and second data holding units match, the external data is not written into the memory.

According to a second aspect of the present invention, when data in a memory is read and output to the outside, it is determined whether or not the memory is in an idle state, and when it is determined that the memory is in an idle state, Reading data from the memory, holding the data in a third data holding unit, and outputting the data from the third data holding unit.

According to a third aspect of the present invention, in the first or second aspect, it is further determined whether or not the memory is in an idle state when a predetermined refresh interval has elapsed, and it is determined that the memory is in an idle state. In some cases, a refresh operation of the memory is performed.

Further, according to a fourth aspect of the present invention, there is provided a memory, comprising:
A data holding unit, a second data holding unit, a first determination unit that determines whether the memory is in an idle state when writing external data to the memory, and the first determination unit Means for reading the data at the write address of the external data from the memory and holding the data in the first data holding means when the memory is determined to be in an idle state; Means for holding the data and means for determining whether or not the data in the first and second data holding means coincide with each other. Means.

The invention according to claim 5 further comprises a memory and a third memory.
A data holding unit, a second determination unit that determines whether the memory is in an idle state when reading data in the memory and outputting the data to the outside, and the memory is in an idle state by the second determination unit. Means for reading out the data in the memory, holding the data in the third data holding means, and outputting the data from the third data holding means.

According to a sixth aspect of the present invention, in the fourth or fifth aspect, a third determining means for determining whether or not the memory is in an idle state when a predetermined refresh interval has elapsed, and the third determining means. Means for executing a refresh operation of the memory when it is determined that the memory is in an idle state.

According to a seventh aspect of the present invention, there is provided a memory control device in a device for inputting image data from an external device and recording an image on a recording medium, wherein a write address generating circuit for generating a write address to a memory; A first data holding circuit for reading and holding data in the memory at an address generated by the address generation circuit, and a second data holding circuit for holding data newly written to the address generated by the write address generation circuit in the memory A data comparison circuit that compares data held in the first data holding circuit with data held in the second data holding circuit, a read address generation circuit that generates a read address to the memory, The memory of the address generated by the read address generation circuit Third to read the data retention
A data holding circuit, a data transfer from the memory to the first data holding circuit, and a data transfer from the second data holding circuit to the memory based on at least one of a write enable signal, a read enable signal, and a refresh request signal. Means for selecting and executing one of transfer and data transfer from the memory to the third data holding circuit.

The invention of claim 8 is characterized in that, in claim 7, the refresh request signal has a refresh time set.

According to a ninth aspect of the present invention, in accordance with the seventh aspect, the external device is provided only when the data of the first data holding circuit and the data of the second data holding circuit are different by the comparison of the data comparing circuit. A means for writing the image data from the memory to the memory.

In a tenth aspect of the present invention, in the seventh aspect, the third data holding circuit holds the data until the transfer request by the data transfer request signal from the print control unit ends.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a page printer will be described below. The circuits constituting the page printer include a communication circuit with a host computer, a control circuit for developing the memory, a print head, a motor, a sensor control circuit, and the like. This is applied to a circuit for controlling a memory included in GA), and this portion will be described below.

FIG. 1 is a block diagram of a circuit for performing the function of interfacing the memory of the dedicated gate array.
In this GA, a write address generator 2, a first data holding circuit 3, a second data holding circuit 4, a write data comparison circuit 5, and a memory for writing data sent from a host into a memory (DRAM) 1 internally. A recording request signal generator 6, a read address generator 7 for reading data from the memory 1 when transferring print data to the print head controller, a data transfer request signal generator 8, and a third data holding unit for holding the read data Circuit 9, refresh timer for refreshing memory 1, refresh request signal generator 10, address multiplexer 11, read / write request arbiter 12, RAS / CAS controller 1
3, a write enable signal generator 14 and a read enable signal generator 15 are included. The request arbitration circuit 12 includes a CPU, a RAM including a work area of the CPU, and
And a ROM storing a control procedure of the CPU including the respective flowcharts as described above. The request arbitration circuit 12 can include the above-described refresh timer. Further, the request arbitration circuit 12 includes a signal from the interface control unit, a signal from the print control unit, a signal from the write data comparison circuit 5, a signal from the refresh request signal generation unit 10, a signal from the write permission signal generation unit 14, A signal from the read permission signal generation unit 15 is input, and the address multiplexer unit 11 and the RAS / CAS control unit 13 are controlled to control read access, write access, and refresh to the memory 1, and further control the entire memory control unit. Control.

A 32-bit SIMM was adopted as the memory 1, and a memory area of 32 MB was prepared.

Communication with the host is performed by bidirectional Centronics (IEEE1284). The operation frequency is set to 20 MHz.

The main operations on the memory 1 are writing data to the memory 1, reading data from the memory 1, and refreshing the memory 1. FIGS. 2 to 4 are flow charts for explaining the operation in each mode. Indicated. Each of these modes will be described in detail. Hereinafter, the idle state is a state in which the write cycle (from the start to the end of data writing), the read cycle (from the start to the end of data reading), and the refresh cycle (from the start to the end of the refresh) of the memory 1 are not performed. The determination is made in the request arbitration circuit 12.
A state in which any of the operations is performed is a busy state of the memory, and the determination is also made in the request arbitration circuit 12.

FIG. 2 is a flowchart for explaining the operation in the data write cycle. First, a buffer (first data holding circuit 3) is used to read in advance data of an initial address to be written first.
It is determined whether or not a signal for determining whether or not data can be written to the device, that is, whether or not a write enable signal from the write enable signal generator 14 is valid (S11). If it is valid, it is determined whether or not the memory 1 is in an idle state (S12). If the memory 1 is in a busy state, it is waited for its release. If the memory 1 is in an idle state, read access to the memory 1 is performed and a write address is Is read and held in the first data holding circuit 3 (S13), and then the print data from the host is held in the second data holding circuit 4 (S14 to S17). The data at this time is 4 bytes. Data is transferred from the host in units of 1 byte, and the transfer data is held in the second data holding circuit 4 for 4 bytes.

When all the data is received, the data comparison circuit of FIG. 5 determines whether the data in the first data holding circuit 3 and the data in the second data holding circuit 4 are correct or not (coincidence / mismatch) ( S18). Here, if the data is the same, that is, if the data validity signal is valid, the write address of the write address generation unit is incremented without performing the data write cycle, and if the data is different, that is, if the data validity signal is invalid, Write data in the second data holding circuit 4 to the memory 1 (S
19) and then increment the address (S
20). After the end of the address increment, the write enable signal of the write enable signal generation unit 14 is enabled (S2
0), and enters the next write cycle. Thereafter, this is repeated until the last data (S22). When the last data of one page from the host is less than 4 bytes, the data is compared with 4 bytes or less.

FIG. 3 is a flowchart for explaining the operation in the data read cycle. In order to read the data in the memory 1 into the third data holding circuit 9, it is confirmed that the read permission signal of the read permission signal generator 15 is valid (S23). And memory 1 is ID
In the LE state, the memory 1 is accessed, data is read, and the data is held in the third data holding circuit 9 (S24 to S26). Here, the read permission signal generation unit 1
The read permission signal 5 is invalidated to avoid overwriting of data. A permission to transfer the data held in the third data holding circuit 9 to the printing unit is issued, and the process waits until the data transfer request signal from the data transfer request signal generation unit 8 becomes valid (S27). When the transfer of data from the printer to the printing unit is completed (S28), the read address of the read address generation unit 7 is incremented (S2).
9) Then, the read permission signal of the read permission signal generation unit 15 is enabled (S30). This completes the data read cycle.

FIG. 4 is a flowchart for explaining a refresh cycle of the memory. The refresh interval is measured at a refresh interval set in a register inside the request arbitration circuit using a timer inside the GA. After the refresh is started, the refresh timer is started (S31). When the refresh timing comes, the refresh request signal is made valid, and the refresh timer is stopped (S32), and S3
In step 3, it is determined whether the refresh request signal is valid. If the signal is valid, the process waits until the memory becomes idle in step S34. If the memory becomes idle, the refresh operation is started in step S35 and the refresh execution register is invalidated. Then, the refresh timer is cleared, the refresh execution register is enabled in S36, and the process returns to S31.

FIG. 6 is a timing chart for explaining a data write cycle and a data read cycle.

First, the write cycle will be described. Since the memory read cycle is performed in three clocks (clk), three clocks during the data reading are used in the memory BUSY
State. In this embodiment, the data transfer rate with the host is 2000 ns until one byte is transferred to the printer because one byte is transferred in 500 ns. After the data is determined, the data is compared. This can be sufficiently determined with two clocks because the data comparison circuit of FIG. 5 is used. If writing becomes necessary due to this determination, the memory uses three clocks B as a write cycle.
It becomes a USY state. In order to write 4 bytes of data to the memory, the BUSY period of the memory becomes 6 clocks in total,
While the other memories are in the IDLE state, other operations, that is, data read operation and memory refresh can be performed. This is particularly effective when there are many prints in which only one part of data is changed by writing after comparing data.

Next, a read cycle of the memory will be described. When data is read into the buffer (third data holding circuit), the memory enters the BUSY state for three clocks. When transferring data to the printing unit, it is only necessary to read data from the buffer, so there is no need to access the memory, and the memory is in the IDLE state. Therefore, during this period, data can be written and the memory can be refreshed.

Since the write cycle and the read cycle of the memory are performed with a margin more than the timing when data is actually required, even if the memory is kept in the BUSY state, the system efficiency is reduced. There is no.

Since the refresh has the lowest priority, even if the refresh request is valid, if the read request or the write request is valid before the request is executed, that priority is given. Is done. However, due to restrictions on data transfer to and from the host and restrictions on data transfer to the printing unit, there is always a timing at which the memory enters the IDLE state even if requests overlap, so the priority is lowered and time is reduced. There is no guarantee that no refresh will occur. If the refresh interval is set with a margin assuming the worst case, a decrease in system efficiency due to refresh can be suppressed.

[0035]

As described above, according to the present invention,
The memory can be controlled efficiently. By performing a predetermined operation even in the IDLE state of the memory,
Elimination of system efficiency caused by prioritizing operations is eliminated. In particular, the data transfer speed increases,
In the case where data transfer based on the IEEE 1394 standard is used, if data is written at a high speed, the effect can be greatly exerted. Further, a method of accessing the memory in the IDLE state is performed by a synchronous DRAM or the like.
This can be performed even when a memory that will be used frequently is used.

[Brief description of the drawings]

FIG. 1 is a block diagram of a circuit that performs an interface function to a memory of a dedicated gate array.

FIG. 2 is a flowchart illustrating an operation in a data write cycle.

FIG. 3 is a flowchart illustrating an operation in a data read cycle.

FIG. 4 is a flowchart for explaining a refresh cycle of a memory;

FIG. 5 is a diagram illustrating a data comparison circuit.

FIG. 6 is a diagram showing a timing chart for describing a data write cycle and a data read cycle.

[Explanation of symbols]

 Reference Signs List 1 memory 2 write address generation unit 3 first data holding circuit 4 second data holding circuit 5 write data comparison circuit 6 memory recording request signal generation unit 7 read address generation unit 8 data transfer request signal generation unit 9 third data holding circuit 10 Refresh request signal generation unit 11 Address multiplexer unit 12 Request arbitration circuit 13 RAS / CAS control unit 14 Write permission signal generation unit 15 Read permission signal generation unit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hironobu Yanagida 5540-11 Sakate-cho, Mizukaido-shi, Ibaraki F-term in Canon Aptex Co., Ltd. (Reference) 5B060 CA10 CB10

Claims (10)

[Claims] When writing external data to a memory, it is determined whether or not the memory is in an idle state. When it is determined that the memory is in an idle state,
The data of the write address of the external data is read from the memory and held in a first data holding unit. The external data is held in a second data holding unit. Determining whether the data in the first and second data holding units match, and not writing the external data to the memory when it is determined that the data in the first and second data holding units match. . 2. When reading data in a memory and outputting the data to the outside, it is determined whether or not the memory is in an idle state, and when it is determined that the memory is in an idle state,
A memory control method, comprising reading data in the memory, holding the data in a third data holding unit, and outputting the data from the third data holding unit. 3. The method according to claim 1, further comprising: determining whether the memory is in an idle state when a predetermined refresh interval has elapsed; and determining that the memory is in an idle state,
A memory control method, comprising performing a refresh operation of the memory. 4. When writing external data to the memory, the first data holding unit, the second data holding unit, and the memory,
First determining means for determining whether or not the memory is in an idle state; and when the first determining means determines that the memory is in an idle state, the memory stores the data of the write address of the external data into the memory. Means for reading data from the first data holding means, means for holding the external data in the second data holding means, and determining whether the data in the first and second data holding means match. And a control means for preventing the external data from being written into the memory when it is determined that they match. 5. A memory, a third data holding unit, a second determination unit for determining whether the memory is in an idle state when reading data in the memory and outputting the read data to the outside, Means for reading data in the memory, holding the data in the third data holding means, and outputting the data from the third data holding means when the judgment means judges that the memory is in the idle state. A memory control device. 6. The apparatus according to claim 4, further comprising: third determining means for determining whether or not the memory is in an idle state at a point in time when a predetermined refresh interval has elapsed. Means for executing a refresh operation of the memory when it is determined that there is a memory control device. 7. A memory control device in an apparatus for inputting image data from an external device and recording an image on a recording medium, comprising: a write address generation circuit for generating a write address to a memory; A first data holding circuit for reading and holding data in the memory at the specified address; a second data holding circuit for holding data to be newly written at an address generated by the write address generation circuit of the memory; The data held in the data holding circuit and the second
A data comparing circuit for comparing data held in a data holding circuit; a read address generating circuit for generating a read address to the memory; and reading data in the memory at an address generated by the read address generating circuit. A third data holding circuit for holding, and a data transfer from the memory to the first data holding circuit based on at least one of a write enable signal, a read enable signal, and a refresh request signal; Means for selecting and executing one of data transfer to a memory and data transfer from the memory to the third data holding circuit. 8. The memory control device according to claim 7, wherein a refresh time is set in the refresh request signal. 9. The image data from the external device according to claim 7, wherein the comparison of the data comparison circuit only causes the data of the first data holding circuit and the data of the second data holding circuit to differ from each other. A memory control device comprising means for writing to a memory. 10. The memory control device according to claim 7, wherein the third data holding circuit holds data until a transfer request by a data transfer request signal from a print control unit ends.