JPH0743960B2 - Dynamic memory circuit - Google Patents
Dynamic memory circuitInfo
- Publication number
- JPH0743960B2 JPH0743960B2 JP62276386A JP27638687A JPH0743960B2 JP H0743960 B2 JPH0743960 B2 JP H0743960B2 JP 62276386 A JP62276386 A JP 62276386A JP 27638687 A JP27638687 A JP 27638687A JP H0743960 B2 JPH0743960 B2 JP H0743960B2
- Authority
- JP
- Japan
- Prior art keywords
- counter electrode
- potential
- power supply
- dynamic memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体メモリ装置のメモリセルのデータ蓄積に
コンデンサを用いたダイナミック型メモリ回路に関し、
且つ、そのコンデンサがMOS（Metal Oxide Silicon）型
コンデンサを用いて構成されるダイナミック型メモリ回
路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic memory circuit using a capacitor for storing data in a memory cell of a semiconductor memory device,
In addition, the present invention relates to a dynamic memory circuit whose capacitor is configured by using a MOS (Metal Oxide Silicon) type capacitor.
従来、半導体メモリ回路に於ける代表的なダイナミック
型メモリセルは１トランジスタ型と呼ばれ、第２図に示
される様に、トランジスタのMOS型コンデンサにより構
成されており、このコンデンサを構成する為に、コンデ
ンサのデータが供給される駆動側電極に対向する対向電
極の電位すなわち対極電位は電源電圧、又は、電源電圧
を分圧した特定電位を発生する対極電位供給回路の出力
電圧に接続される構成となっていた。Conventionally, a typical dynamic type memory cell in a semiconductor memory circuit is called a one-transistor type, and as shown in FIG. 2, it is composed of a MOS type capacitor of a transistor. The configuration in which the potential of the counter electrode facing the drive side electrode to which the data of the capacitor is supplied, that is, the counter electrode potential, is connected to the power supply voltage or the output voltage of the counter electrode potential supply circuit that generates a specific potential by dividing the power supply voltage It was.
上述した従来のダイナミック型メモリ回路においては、
メモリセルを構成するコンデンサには、MOS型コンデン
サが用いられている。ダイナミックメモリのビット数増
大によって、ダイナミックメモリの大容量化が進むにつ
れて、このメモリセルを構成するコンデンサの小型化が
要求されるが、ダイナミックメモリの信頼度の一つであ
るソフトエラーの問題を克服する為には、ある一定量の
要領を保つ必要がある。従って、小型、且つ、コンデン
サ容量を大きくする為に薄膜化の技術が進められてい
る。In the conventional dynamic memory circuit described above,
A MOS type capacitor is used as the capacitor forming the memory cell. As the capacity of dynamic memory increases due to the increase in the number of bits of dynamic memory, the miniaturization of the capacitor that constitutes this memory cell is required, but the problem of soft error, which is one of the reliability of dynamic memory, is overcome. In order to do so, it is necessary to keep a certain amount of points. Therefore, in order to reduce the size and increase the capacitance of the capacitor, thinning technology is being advanced.
しかし、薄膜化が進む事によって、コンデンサを構成す
る酸化膜等の耐圧は低下し、従って、メモリセルコンデ
ンサの対極にメモリ回路を電源電圧を直接印加する事は
困難になって来ており、メモリ回路の電源電圧より分圧
した対極電位供給回路を設けて、この出力電圧をコンデ
ンサの対極電位に接続する事が一般化しつつある。However, with the progress of thinning, the withstand voltage of the oxide film, etc. that composes the capacitor is lowered, and therefore it is becoming difficult to directly apply the power supply voltage to the memory circuit to the counter electrode of the memory cell capacitor. It is becoming common to provide a counter electrode potential supply circuit that is divided from the power supply voltage of the circuit and connect this output voltage to the counter electrode potential of the capacitor.
この為、メモリ回路の信頼度を実施例する為に、メモリ
の電源電圧を上昇させても、メモリセル対極電位は、常
に分圧された電位となる為に、メモリ電源電圧を上昇さ
せても、メモリセルを構成するコンデンサの信頼度検査
を実施できず、又、正確なメモリセルコンデンサの耐圧
に対する試験が不可能となるという欠点がある。Therefore, in order to implement the reliability of the memory circuit, even if the power supply voltage of the memory is raised, the memory cell counter electrode potential is always a divided potential, so that the memory power supply voltage is raised. However, there is a drawback in that the reliability test of the capacitors forming the memory cells cannot be carried out, and an accurate test for the withstand voltage of the memory cell capacitors becomes impossible.
本発明のダイナミック型メモリ回路は、データの供給を
受ける駆動側電極に対向して対向電極を有するデータの
蓄積用のコンデンサと、前記対向電極に電源電圧を予め
定めた分圧比で分圧した対極電位を供給する対極電位供
給回路とを備えるダイナミック型メモリ回路において、
電源と前記対向電極との間に挿入され試験時に前記電源
電圧を直接前記対向電極に供給するヒューズ手段を備え
て構成される。The dynamic memory circuit of the present invention includes a data storage capacitor having a counter electrode facing a driving electrode receiving data and a counter electrode obtained by dividing a power supply voltage at the counter electrode at a predetermined voltage dividing ratio. In a dynamic memory circuit including a counter potential supply circuit that supplies a potential,
It comprises fuse means inserted between a power source and the counter electrode to directly supply the power supply voltage to the counter electrode during a test.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例のダイナミック型メモリ回
路の構成図である。FIG. 1 is a configuration diagram of a dynamic memory circuit according to an embodiment of the present invention.
ダイナミック型メモリの信頼度試験を実施する場合、対
極電位供給回路１の出力電位V0は、電源パッド２から供
給されるメモリの外部電源電圧VCCに直接に接続される
為に、対極電位供給回路１の電位とは無関係に電源電圧
VCCの値そのものとなる。When performing the reliability test of the dynamic memory, since the output potential V 0 of the counter potential supply circuit 1 is directly connected to the external power supply voltage V CC of the memory supplied from the power supply pad 2, the counter potential supply is performed. Power supply voltage regardless of the potential of circuit 1
It becomes the value of V CC itself.
又、ヒューズ３を切断すると、メモリセル対極電位V1は
電源電圧線４から切離される為に、本来意図した対極電
位供給回路１の電圧V0が接続されるので、信頼度等の評
価が不要の場合はヒューズを溶断する事で、供給目的の
メモリ回路そのものとして実現しうる。Further, when the fuse 3 is cut, the memory cell counter electrode potential V 1 is disconnected from the power supply voltage line 4, so that the originally intended voltage V 0 of the counter electrode potential supply circuit 1 is connected. If unnecessary, the fuse can be blown to realize the memory circuit itself for the purpose of supply.
本発明の対象とする大容量のダイナミックメモリにおい
ては、一般に、メモリセルアレイ全体を一部をリダンダ
ンシーセル部として含む複数のブロックに分割し、上記
単位ブロックすなわちメモリセル部毎にヒューズを用い
て分離できるように構成し、試験結果製造不良と判定さ
れたメモリセル部を対応のヒューズの溶断により分離し
上記リダンダンシーセル部に置換する方式が用いられて
いる。したがって、上述したように信頼度試験および通
常動作の切替にヒューズを用いることは、特別な設備の
追加や工程の増加をもたらすことなく容易に実施でき
る。In a large-capacity dynamic memory to which the present invention is applied, generally, the entire memory cell array can be divided into a plurality of blocks including a part as a redundancy cell section, and the unit block, that is, each memory cell section can be separated by using a fuse. In this configuration, the memory cell portion determined to be defective in the test result is separated by fusing the corresponding fuse and replaced with the redundancy cell portion. Therefore, as described above, using the fuse for the reliability test and the switching of the normal operation can be easily performed without adding special equipment or increasing the number of steps.
以上説明したように本発明は、試験時にメモリセルのデ
ータ蓄積用のコンデンサの対極電位として電源電圧を直
接供給するよう挿入されたヒューズ手段を備えることに
より、特別な設備の追加や工程を増加することなく、供
給対象のデバイスと同一のデバイスを用いてメモリ回路
の信頼度評価のための上記コンデンサの耐圧試験を容易
に実施できるという効果がある。As described above, the present invention includes the fuse means inserted so as to directly supply the power supply voltage as the counter potential of the capacitor for data storage of the memory cell during the test, thereby increasing the addition of special equipment and the number of steps. Without the above, there is an effect that the withstand voltage test of the above-mentioned capacitor for the reliability evaluation of the memory circuit can be easily performed using the same device as the device to be supplied.
第１図は本発明の一実施例のダイナミック型メモリ回路
の構成図、第２図は従来用いられているダイナミック型
メモリセルの構成図を示す図である。 １……メモリセル対極電位、VCC……電源電圧、V0……
対極電位供給回路の出力電位、１……対極電位供給回
路、２……電源パッド、３……メモリ周辺回路入出力回
路、４……電源電圧線、５……メモリセル、10……ビッ
ト線、20……ワード線。FIG. 1 is a diagram showing the configuration of a dynamic memory circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional dynamic memory cell. 1 ... Memory cell counter potential, V CC ...... Power supply voltage, V 0 ......
Output potential of counter potential supply circuit, 1 ... Counter potential supply circuit, 2 ... Power supply pad, 3 ... Memory peripheral circuit input / output circuit, 4 ... Power supply voltage line, 5 ... Memory cell, 10 ... Bit line , 20 …… Word line.
Claims (1)
て対向電極を有するデータの蓄積用のコンデンサと、前
記対向電極に電源電圧を予め定めた分圧比で分圧した対
極電位を供給する対極電位供給回路とを備えるダイナミ
ック型メモリ回路において、 電源と前記対向電極との間に挿入され試験時に前記電源
電圧を直接前記対向電極に供給するヒューズ手段を備え
ることを特徴とするダイナミック型メモリ回路。1. A data storage capacitor having a counter electrode facing a driving electrode receiving data, and a counter electrode potential obtained by dividing a power supply voltage at a predetermined voltage dividing ratio to the counter electrode. A dynamic memory circuit including a counter potential supply circuit, comprising a fuse means that is inserted between a power source and the counter electrode to directly supply the power supply voltage to the counter electrode during a test. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62276386A JPH0743960B2 (en) | 1987-10-30 | 1987-10-30 | Dynamic memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62276386A JPH0743960B2 (en) | 1987-10-30 | 1987-10-30 | Dynamic memory circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01118299A JPH01118299A (en) | 1989-05-10 |
| JPH0743960B2 true JPH0743960B2 (en) | 1995-05-15 |
Family
ID=17568690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62276386A Expired - Lifetime JPH0743960B2 (en) | 1987-10-30 | 1987-10-30 | Dynamic memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0743960B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4527254A (en) * | 1982-11-15 | 1985-07-02 | International Business Machines Corporation | Dynamic random access memory having separated VDD pads for improved burn-in |
| JPS59180888A (en) * | 1983-03-31 | 1984-10-15 | Fujitsu Ltd | Semiconductor memory |
-
1987
- 1987-10-30 JP JP62276386A patent/JPH0743960B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01118299A (en) | 1989-05-10 |
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