JPS6284491A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To stabilize a cell plate potential by providing a sense circuit comparing the potential of a monitor memory cell with a reference potential and controlling the output impedance of a cell plate potential generator circuit. CONSTITUTION:At the time of an action after the cell node potential of the monitor memory cell 1 drops below a VCC, nodes N1 and N2 in the sense circuit 2 come to levels 'H' and 'L', respectively. A MOSFET-Q7 is turned off, and the gates of MOSFETs -Q1 and Q2 in the cell plate potential generator circuit 4 become a level H through a MOSFET-Q6, and are turned on. Namely the output impedance of a cell plate potential setting circuit CPG decreases, and speedily recovers even if a cell plate CP develops the potential fluctuation. Thus the cell plate potential is stabilized, whereby dRAM's erroneous action can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which a plurality of memory cells each having a capacitor for storing information charges are arranged in a seven-trix pattern to form a memory array.

[Technical disadvantages of inventions and their problems]

2. Description of the Related Art In recent years, semiconductor memory devices have rapidly become more highly integrated and their elements become smaller. In particular, the degree of integration of dynamic RAM (dRAM), in which one memory cell is composed of a capacitor that stores information in the form of charge and a switching MO8FET, is remarkable.

In highly integrated dRAM, soft errors have become a serious problem as the area occupied by memory cells is reduced.

In order to ensure sufficient resistance to soft errors and to maintain a sufficiently high sense sensitivity, the amount of charge stored in the capacitor cannot be made too small.

One method for keeping the volume of a memory cell capacitor large without increasing the occupied area is to make the capacitor insulating film thin. For example, 1Mbit dR
In AM, 100 to 150 8102 films are used as capacitor insulating films.

When using such a thin capacitor insulating film, if the so-called cell plate, which is the common electrode of multiple capacitors, is set to the ground potential (Vss) or 1ff (Vco), the dielectric strength of the capacitor insulating film may become a problem. Become. The capacitor insulation film thickness is 100 mm, and the cell plate potential is V.
When setting cc-5V or Ves = OV, the maximum electric field applied to the capacitor insulating film is 5 M V /
This is because it also reaches r:ia. Therefore, when such a thin capacitor insulating film is used, a method is adopted in which a potential (1/2) Vco, which is intermediate between Vco and Vss, is applied to the cell plate.

However, when a method of setting the cell plate potential to (1/2) Vcc is adopted, another problem arises. A cell plate i/potential setting circuit for setting the cell plate potential to (1/2) Vco [Basically, Vcc and Vco]
A resistor divider is used in which a resistor is connected in series between an and an. In this case, since a through current flows from Vco to Vas, a high-resistance dividing resistor is required to reduce current consumption. However, when a high resistance is used to apply a cell plate potential, variations in the cell node cause potential variations in the cell plate, causing malfunctions. To explain a little more concretely, for example, if a memory cell has “1°” (Vc
c level), and after enough time has passed, write “'
Consider the case where 0" (Vso level) is written. The cell node of the memory cell where 1" was written has a potential that has fallen to, for example, (2/3) Vcc due to leakage over time, but it is not selected. As a result of being refreshed, the memory cells connected to the same word line as the memory cells returned to the normal ``1'' level. This makes the cell node (
2/3) Since it fluctuates from Vco to Vco, this is a
Coupling raises the potential of the cell plate. This rise in cell plate potential raises the cell node of the selected memory cell to which "0" is written, causing a malfunction in which it is erroneously read as "1".

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a highly reliable semiconductor memory device in which cell plate potential is stabilized without increasing power consumption.

[Summary of the invention]

The present invention relates to a dRAM having a cell plate potential setting circuit that provides a predetermined potential between the power supply potential and the ground potential to the cell plate. ``When the potential drops below the level potential, this is detected, the output impedance decreases, and the structure has a function to quickly recover from fluctuations in the cell plate potential. Specifically, a base I'lIN level generation circuit and a monitor memory cell to which "1" level (Vcc level) is always written are provided, and a sense circuit is provided to compare the potential of the monitor memory cell with a reference potential. The sense circuit is configured to control the output impedance of the cell plate potential generation circuit.

〔Effect of the invention〕

According to the present invention, it is possible to increase the resilience to cell plate potential fluctuations only when the potential of a cell node decreases, thereby reliably preventing malfunctions due to cell plate potential fluctuations. During normal operation, the output impedance of the cell pre-potential setting circuit can be kept high and unnecessary through current can be reduced. This makes it possible to realize dRAM with low power consumption and high reliability.

(Example of the invention) The present invention will be explained in detail below.

FIG. 1 shows a schematic configuration of a dRAM according to an embodiment.

The memory array MA is constructed by arranging memory cells consisting of capacitors and MOSFETs in a matrix on a semiconductor substrate using a well-known method.

WLl, . . . , Wl-n are word lines for selectively driving memory cells, and BLl, BLt, BL+'.

BL1', . . . are bit lines that exchange information charges with memory cells. This embodiment shows a so-called folded bit line configuration.

SA is a sense amplifier, and RDl and RD2 are row decoders. CP indicates a cell plate arranged as a common electrode of capacitors of all memory cells. CPG is a cell plate potential setting circuit that applies a predetermined potential to this cell plate CP.

FIG. 2 shows a specific configuration of the cell plate potential setting circuit CPG. 1 is a memory cell for monitoring, 2 is a sense circuit, 3
4 is a reference potential generation circuit, 4 is a cell plate potential generation circuit,
5 is a delay circuit. The monitor memory cell 1 is a MOSFET-Q like the memory cells in the memory array MA.
It consists of a capacitor CM and a capacitor CM, and the Voo level is always written therein. The reference potential generation circuit 3 sandwiches resistors R3 and R4 between Vco and Vss, and obtains a desired reference potential by resistor division. Here, as the reference potential (2/3)
To obtain Vca, apply Vs to resistor R3 on the Vca side.
The resistance value of the s-side resistor R4 is set to double. Sense circuit 2 includes input gate MO8FET-03, Q4,
J to differential amplifier DA including MO8FET-Qs for activation.
: It is composed of: The activation MO8FET-Qs is controlled by a clock φ which is a "high level" only during operation.The cell plate potential generation circuit 4 is connected to a resistor with a first resistor R1 and a second resistor R2 sandwiched between Vcc and Vss. The basic part is the part that gives the cell plate potential by dividing.In this example, both resistors R1 and R2 are 25Ω, so that (1/2)Vco is given as the cell plate potential.These dividing resistors First and second MOSFETs Qs and Q2 whose gates are commonly controlled by the output of the sense circuit 2 are connected in parallel to Ri and R2, respectively.These MOSFETs Ql.

The dimension of Q2 is set to 2.5Ω (when Vcc=5V) in the on state.

The operation of this cell plate potential setting circuit will be explained next.

With the Vco level written in the monitor memory cell 1, sensing is performed when the clock φ goes to "H" level during operation, and the output node N1 goes to the "L" level and the node N
2 becomes the "H" level. At this time, MOSFET-07 is turned on via delay circuit 5, and MOS transistor Qs of cell plate potential generation circuit 4 is turned on.

Both Q2 are turned off. At this time, the cell plate potential is determined only by resistors R1 and R2. Therefore, the through current flowing at this time is 5V/(2,5Ω×2)=0.1mA, which is very small.

The cell node potential of monitor memory cell 1 is (2/3)V
If it falls below cc, sense circuit 2 will be activated during subsequent operation.
The output of node N1 becomes 'H' level and node N2 becomes 'L' level.As a result, MOSFET-07 is turned off, and the sense circuit 40M is outputted via MOSFET-Qr.
The gates of 08FET-01 and Q2 become 11 HII level, and these MOSFET-01 and Q2 are turned on. That is, the output impedance of this cell plate potential setting circuit CPG becomes small, and even if there is a potential fluctuation in the cell plate CP, this is quickly recovered.

Thereafter, the monitor memory cell 1 is refreshed and its cell node becomes the Voc level, and the output of the sense circuit 2 is inverted. This causes the node N1 to go to the "L" level, but since the MOSFET-Qa is turned off at this time, the input terminal of the sense circuit 4 remains at an idle level for a while. The "H" level of the node N2 turns on the MOSFET-B7 with a delay of, for example, 8 m5eC via the delay circuit 5. As a result, the input terminal of the sense circuit 4 becomes the "L" level, and the MOSFET-Ql turns on.

B2 turns off. The reason why the delay circuit 5 is provided to delay the time for returning the output impedance of the cell plate potential setting circuit to the high impedance state is the result of taking into consideration the variation in leakage current within the memory array MA.

Thus, according to this embodiment, 11111 of the memory cells
When the level decreases and the capacitive coupling between the cell node and the cell plate increases, the output impedance of the cell plate potential setting circuit becomes smaller and the cell plate potential fluctuation is quickly reset, thereby preventing dRAM malfunction. can do. Moreover, the through current during standby and normal operation is small, and the current consumption of dRAM does not increase.

FIG. 3 shows the main structure of another embodiment of the present invention.

Components corresponding to the embodiment in FIG. 2 are given the same reference numerals as in FIG. 2. In this embodiment, the memory array MA has two blocks MA1. (In the case of a JRAM configuration, monitor memory cells 11, 12 and sense circuits 21, 22 are provided for every 181° MA2 in each memory array block. Word l of each monitor memory cell 11.12
1lWl-x.

WLy is “H” only when the word line of the corresponding memory array block MAr, MA2 is selected.
'' level, the Vco level is written to the monitor memory cell.The reference signal generation port 3 is common.Then, the outputs of each sense circuit 2s and 22 are NORed.
The voltage J is input to the cell plate potential generation circuit 4 via the gate 6.

In this embodiment, two monitor memory cells 1 t
, 12 (D cell) -t'ff)Itfff is (2
/3) Cell plate potential optical circuit 4 only when Vcc or higher
output impedance becomes high. When the cell node of either one of the monitor memory cells falls below (2/3)Vco, the sense circuit operates in the same way as explained in the previous embodiment, and the output impedance of the cell plate potential generation circuit 4 becomes low. The plate potential fluctuations are reset.

As described above, in this embodiment, when there is variation in leakage current within the memory array MA, fine-grained control is performed by focusing on the cell node potential in the portion where the leakage current is large to increase the resilience to cell plate potential fluctuations. . Therefore, in this embodiment, unlike the previous embodiment, a delay circuit is not provided, and the cell play i/potential can be effectively stabilized to prevent malfunction of the dRAM.

The present invention is not limited to the above embodiments.

For example, the present invention can be similarly applied when setting the cell plate potential to (1/2>Vcc, but also to any other suitable value between Vcc and Vss.) Although a differential amplifier has been described as a sense circuit for detecting a drop in cell node potential, other circuits such as a flip-flop or the like may be used.

Further, in the embodiment shown in FIG. 3, an example in which the memory array is divided into two areas has been described, but it may be divided into more areas and a monitoring memitor may be provided for each block.

Furthermore, it is also possible to use the memory cell itself used for normal information storage for monitoring without providing a special memory cell for monitoring. It is also possible to use a method of detecting cell plate potential changes and keeping the cell plate voltage within a certain range of variation.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a dRAM according to an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration of its cell plate potential setting circuit, and FIG. 3 is a diagram showing a cell plate potential setting circuit of another embodiment. FIG. 1 shows a specific configuration of the circuit. MA...Memory array, CP...Cell plate, C
PG...Cell plate potential setting circuit, Bl-, B1.
-...Bit line, WL...Word line, SA...Sense amplifier, RDl, RD2...Row decoder, 1
...Memory cell for monitor, 2...Sense circuit, 3.
...Reference signal generation circuit, 4...Cell plate potential generation circuit, 5...Delay circuit, MAl, MA2...Memory array block, 11.12...Memory cell for monitor, 21°22. ...Sense circuit.

Claims (4)

[Claims] (1) A semiconductor substrate has a memory array in which a plurality of memory cells each having a capacitor for storing information charges are arranged in a matrix, and a cell plate, which is a common electrode of the plurality of capacitors, is connected to a power supply potential and a ground potential. In a semiconductor memory device, the cell plate potential setting circuit includes a monitor memory cell into which a power supply potential is written, a reference potential generation circuit, and a cell plate potential setting circuit that provides a predetermined potential between the monitor memory cells. 1. A semiconductor memory device comprising: a sense circuit that compares an output with an output of a reference potential generation circuit; and a cell plate potential generation circuit whose output impedance is varied by being controlled by the sense circuit. (2) The cell plate potential generation circuit includes a first resistor and a second resistor connected between the cell plate, a power supply potential, and a ground potential, respectively, to determine the cell plate potential; 2. The semiconductor memory device according to claim 1, further comprising first and second MOSFETs connected between each other and having gates commonly controlled by the output of the sense circuit. (3) The memory array is divided into a plurality of blocks that are selectively activated, the monitor memory cell is provided for each memory array block, and the sense circuit is provided for each monitor memory cell. Claim 1, wherein the cell plate potential generation circuit is controlled by a logical sum of outputs of a plurality of sense circuits.
The semiconductor storage device described in 1. (4) The semiconductor memory device according to claim 1, wherein the monitor memory cell is a memory cell itself used for normal information storage.