JPH0740431B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a wiring structure in a memory array of a semiconductor memory device, and more particularly to an improvement in the above wiring structure in a dynamic semiconductor memory device.

[Prior Art] Taking a conventional dynamic semiconductor memory device as an example, its configuration and problems in high integration will be described.

FIG. 3 shows a circuit diagram of a memory array portion of a conventional dynamic semiconductor memory device.

In the highly integrated dynamic semiconductor memory device, in order to reduce the array of the column decoders 1, a method of sharing the column decoder 1 among a plurality of memory cell array blocks # 1 and # 2 is adopted. In the case of this method, the decode outputs CS0, CS1, ... Of the column decoder 1 must be supplied also to the memory cell array block # 2, and therefore,
A column decoder output line 2 is arranged in the memory cell array block # 1.

Also, a plurality of bit line pairs BL0 and ▲ ▼, BL1 and ▲ ▼, ... Arranged in the memory cell array block # 1.
Are column select gates T0 and ▲ ▼, T1 and ▲, respectively.
A plurality of bit line pairs BL0 'and ▲ ▼, BL1' and ▲ connected to the data input / output line pair I / O, ▲ ▼ via ▼, ... and arranged in the memory cell array block # 2.
▼, ... are column select gate pair T0 ′ and ▲, respectively.
It is connected to the data input / output line pair I / O ′ and ▲ ▼ via ▼, T1 ′ and ▲ ▼, ....

FIG. 4 is another circuit diagram of a memory array of a conventional dynamic semiconductor memory device. In FIG. 4, the same or corresponding parts as those in FIG. 3 are designated by the same reference numerals.

In FIG. 4, column decoder outputs CS0, CS1, ... Are commonly applied to two bit line pairs in the memory cell array block # 1 and two bit line pairs in the memory cell array block # 2, respectively. It is like this. With such a configuration, the array pitch of the column decoder 1 can be doubled as compared with the case of FIG. 3, and the array area for the column decoder 1 can be reduced, which is advantageous. The circuit as shown in FIG. 4 is suitable for, for example, a multi-bit simultaneous input / output method.

[Problems to be Solved by the Invention] However, the conventional semiconductor memory device having the circuit configuration shown in FIGS. 3 and 4 has the following problems. Specifically, description will be made with reference to the circuit of FIG.

For example, focusing on the stray capacitance of the bit line pair BL1, ▲ ▼ in FIG. 4, it can be seen that the stray capacitance is coupled to the bit line pair BL1, ▲ ▼ as shown in FIG.

Where C0 is the capacitance between each bit line BL1 and ▲ ▼ with the ground potential, C1 is the capacitance between the paired bit lines, and C2 is the bit line and the column decoder adjacent to the bit line. A capacitance between the output line 2 and C3 is a capacitance generated between the bit lines closest to each other between one bit line forming a pair and the other bit line forming a pair.

As described above, since the bit line pair BL1, ▲ ▼ has various stray capacitances with other wirings, the bit line pair BL1,
The stray capacitances C _BL1 and ▲ ▼ of ▲ ▼ are respectively C _BL1 = C0 + C2 + C1 (1) Becomes Here, if the capacitances C2 and C3 are C2 ≠ C3, the stray capacitance is Therefore, a difference occurs in the stray capacitance between the pair of bit lines BL1 and ▲ ▼, and the operation margin at the time of reading a signal from the bit line pair BL1, ▲ ▼ is significantly reduced.

This situation also occurs for all other bit line pairs.

Further, not only in the circuit of FIG. 4 but also in the conventional semiconductor memory device shown in FIG. 3, especially when the bit line and the column selection line are formed in different wiring layers, due to mask shift or the like, The column select line does not always pass through the midpoint of the bit line, and similar imbalance occurs.

Therefore, the present invention has been made in order to solve the above problems, and eliminates the imbalance of the stray capacitance between the bit line pairs, and suppresses the maximum value of the stray capacitance of the bit lines, It is an object of the present invention to provide a highly reliable semiconductor memory device in which an operational margin at the time of reading a signal from is increased to reduce malfunction.

[Means for Solving the Problems] The semiconductor memory device according to the present invention is one in which each bit line pair is three-dimensionally intersected at an arbitrary position so that the arrangement positions of the paired bit lines are interchanged. is there.

[Operation] Since the bit line pairs in the present invention are three-dimensionally intersected at any appropriate place, the imbalance of the stray capacitance between the bit line pairs is canceled out.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a memory array portion of a semiconductor memory device according to an embodiment of the present invention. FIG. 1 is an improvement of the conventional semiconductor memory device described in FIG.
In FIG. 1, the same or corresponding parts as those of FIG. 4 are designated by the same reference numerals.

The feature of the circuit of FIG. 1 is that each bit line pair BL0 and ▲ ▼,
BL1 and ▲ ▼, BL2 and ▲ ▼, BL0 'and ▲
.., BL1 'and ▲ ▼, ... Are crossed at the center in the length direction, and the positions of the bit lines are interchanged on the left and right sides of the crossover.

With this structure, the stray capacitance of the bit line is as follows. That is, taking the stray capacitance C _BL1 , ▲ ▼ of the bit line pair BL 1, ▲ ▼ as an example, C _BL1 = C0 + C1 + C2 / 2 + C3 / 2 (3) Becomes So the stray capacitance is It can be seen that both are equal.

Further, in practice, the distance between a certain bit line and the column decoder output line 2 is smaller than the distance between the closest bit lines between a certain bit line pair and an adjacent bit line pair. Therefore, comparing the capacitance C2 and the capacitance C3, C2> C3. From this, the maximum value of the stray capacitance of the bit line is the above-mentioned expression (1) in the case of the conventional circuit, but in the embodiment of the present invention, the expression (3) or (4).
Therefore, it can be understood that it is smaller than the stray capacitance of the equation (1).

Therefore, since the stray capacitances of the two bit lines forming the bit line pair are equal and the maximum stray capacitance is suppressed to a low value, the operation margin at the time of reading the signal from the bit lines is significantly improved, and malfunction occurs. It can be prevented.

FIG. 2 is a circuit diagram of a memory array portion of a semiconductor memory device according to another embodiment of the present invention. In the circuit of FIG. 2,
In addition to the circuit shown in FIG. 1, the open ends of each bit line pair are further crossed.

This has the following advantages. Generally, when the bit lines cross over,
At least one bit line must pass through the other wiring layer. When the other wiring layer is a wiring layer made of a material different from that of the bit line, the capacitance balance of the bit line may be lost at the grade intersection.

For example, in the three-dimensional intersection, an aluminum wiring layer is used for the bit line BL1 and a polysilicon wiring layer is used for the bit line ▲ as connection lines for intersection.

In the embodiment shown in FIG. 2, the capacity imbalance of the bit lines at the grade crossing that occurs in the above case is canceled.

More specifically, in the configuration of FIG. 2, the bit line BL1 uses an aluminum wiring layer, the bit line ▲ ▼ uses a polysilicon wiring layer, and the bit line BL1 has an open end. Since the bit line BL1 is made of a polysilicon wiring layer and the bit line ▲ ▼ is made of an aluminum wiring layer at the intersection of the portions, the unbalance of the capacitance generated at the intersection of the bit line center portions is caused by the bit line open end portion. It will be canceled by the imbalance of capacity that occurred at the intersection of.

Therefore, the stray capacitances of the bit lines forming the bit line pair are completely equal.

The above-mentioned two embodiments are improvements of the conventional semiconductor memory device described with reference to FIG. 4, but the semiconductor memory device described with reference to FIG. Needless to say, the same effect can be obtained as a result of making similar improvements by utilizing the idea.

In each of the above embodiments, the column decoder output line 2 extending from the column decoder 1 may be formed in the same wiring layer as each bit line or in a different wiring layer. It doesn't matter.

Further, in the description of the above embodiment, the memory cell array block has two cases of # 1 and # 2, but the memory cell array block is divided into a larger number of blocks, and columns common to these blocks are used. It may be the case where a decoder is provided.

Further, in the above description, the number of overpasses of the bit line pair is one or two, but more overpasses may be formed if necessary.

Furthermore, not only when the column decoder output lines 2 are arranged at appropriate intervals between a plurality of bit line pairs arranged in parallel, but also as a factor that causes the imbalance of the stray capacitance of the bit line pairs. The present invention can be applied to prevent the imbalance of the stray capacitance of the bit lines even when the signal lines, such as the mother data line and the address line, are provided between the bit line arrays.

[Effects of the Invention] As described above, according to the present invention, each bit line pair is integrally intersected at an arbitrary place so that the arrangement positions of the paired bit lines are interchanged. Can be made equal to each other, the margin of the signal read operation from the bit line pair can be improved, and a highly reliable semiconductor memory device can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory array portion of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a memory array portion of a semiconductor memory device according to another embodiment of the present invention. 3 and 4 are circuit diagrams of a memory array portion of a conventional semiconductor memory device. In the figure, 1 is a column decoder, 2 is a column decoder output line, and BL and ▲ ▼ are bit lines.

Claims (5)

[Claims] 1. A plurality of bit line pairs arranged in parallel, memory cells for storing information charges respectively connected to the plurality of bit line pairs, and a predetermined pair of the plurality of bit line pairs. A column signal line for selectively activating each bit line pair, and each bit line pair is arranged so that the arrangement positions of the bit lines forming the pair are interchanged. A semiconductor memory device characterized in that it is three-dimensionally intersected at the location. 2. The semiconductor memory device according to claim 1, wherein one column signal line is arranged for each of a plurality of bit line pairs. 3. A plurality of bit line pairs arranged in parallel, memory cells for storing information charges respectively connected to the plurality of bit line pairs, and a predetermined pair of the plurality of bit line pairs. A pair of signal supply lines arranged between the pair of bit lines, each bit line pair having an open end at one end, and each bit line pair having an arrangement position of bit lines forming a pair. It is three-dimensionally intersected at any place so that it can be replaced.
The semiconductor memory device is characterized in that the three-dimensional intersection is formed at least near a central portion and an open end in the length direction of each bit line pair. 4. A plurality of bit line pairs arranged in parallel, memory cells for storing information charges respectively connected to the plurality of bit line pairs, and a predetermined pair of the plurality of bit line pairs. And a signal supply line arranged between the pair, each bit line pair is three-dimensionally intersected at any place so that the arrangement position of the bit line forming a pair is switched,
Further, the semiconductor memory device is characterized in that the intersection of each bit line pair is arranged so that each bit line forming a pair balances stray capacitance. 5. The semiconductor memory device according to claim 4, wherein the three-dimensional intersection is formed at least at a central portion in the length direction of each bit line pair.