JP2845526B2 - Dynamic semiconductor memory device - Google Patents

Description

The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly to a dynamic semiconductor memory device in which interference noise between bit lines is reduced. .

(Prior Art) A DRAM having a one-transistor / one-capacitor memory cell structure has been highly integrated due to an improvement in the memory cell structure and advances in microfabrication technology. Data in the DRAM memory cell array is amplified and read by a sense amplifier via a bit line pair. Due to the increase in the density of DRAMs, the interval between bit lines has become extremely fine, and interference noise between bit lines due to an increase in coupling capacity between bit lines has become a significant problem in accurately reading data.

As a method of solving such a problem, a method of reducing interference noise by crossing bit lines has been conventionally proposed. For example, JP-A-63-148489,
ISSCC 88 Digest of Technical Papers pp239-239. However, in these systems, although a certain effect can be obtained in noise reduction, it is not sufficient yet, and there arises a problem that the configuration of the memory cell array is complicated.

(Problems to be Solved by the Invention) As described above, in the conventional high-density DRAM, there is a problem that a large interference noise occurs due to a coupling capacity between bits, and the memory cell array becomes complicated to solve the problem. Was.

An object of the present invention is to provide a DRAM in which interference noise between bit lines is effectively reduced.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a dynamic semiconductor memory device of the present invention comprises a plurality of bit lines, a plurality of word lines, and four dummy words. A plurality of memory cells, a plurality of dummy cells, and a plurality of sense amplifiers, and the plurality of bit lines form a bit line pair in which the bit lines are folded every two lines, These bit line pairs form a bit line unit for every two pairs, the first pair of bit line units are parallel to each other, and the second pair of bit line units are bit line units. A first pair of bit lines extending between the second pair and extending substantially parallel to the pair of bit lines and intersecting at approximately the midpoint of the second pair; Four word lines cross at right angles to the bit lines, and four dummy word lines Extending in parallel and intersecting the bit lines, two dummy word lines are located on one side of the second pair of intersections, and the other two dummy word lines are the other of the second pair of intersections. A plurality of memory cells are connected to an intersection selected from intersections of bit lines and word lines, and any two adjacent memory cells connected to the same word line Also form a group arranged for every two adjacent bit lines,
Any two adjacent memory cells connected to the same bit line are shifted by half a pitch from two corresponding adjacent memory cells connected to any adjacent word line, and a plurality of dummy cells And at least one dummy cell is connected to each bit line, and each of the plurality of sense amplifiers is connected to each of the bit lines. Are provided in pairs.

Further, another semiconductor memory device of the present invention is a dynamic semiconductor memory device having a memory cell array including a plurality of sub-arrays in which two adjacent ones share a sense amplifier. A plurality of word lines, four dummy word lines, a plurality of memory cells, a plurality of dummy cells, and a plurality of sense amplifiers. Forming a pair of bit lines which are folded into a pair of bit lines, forming a bit line unit for every two pairs, the first pair of bit lines of the bit line unit being arranged in parallel with each other, A second pair of bit lines extend parallel to the first pair of bit lines and intersect each other at approximately the midpoint of the second pair, wherein one of the first pair of bit lines is Between the two pairs, The word line intersects the bit line at right angles, four dummy word lines extend parallel to the word line and intersect the bit line, and two dummy word lines are on one side of the second pair of intersections. And another two dummy word lines are arranged on the other side of the intersection of the second pair, and a plurality of memory cells are selected from intersections of the bit line and the word line. Any two adjacent memory cells connected to the same word line and connected to the same word line form a group arranged for every two adjacent bit lines,
Any two adjacent memory cells connected to the same bit line are connected to any adjacent word line and are shifted from the corresponding two adjacent memory cells by a half pitch, and a plurality of dummy cells are At least one dummy cell is connected to each bit line connected to an intersection selected from the intersections of bit lines and dummy word lines, and a plurality of sense amplifiers are adjacent to each other. It is characterized in that it is provided for two corresponding pairs of bit lines of both sub arrays.

(Operation) In the dynamic semiconductor memory device of the present invention, one of two pairs of bit lines constituting a bit line unit is disposed between the other pair of bit lines, and the pair intersects (twisted). ), The influence of the coupling capacitance between adjacent bit lines can be reduced without increasing the chip area, and interference noise can be reduced. Further, the interval between the bit lines forming a pair is increased because another bit line is arranged therebetween, and therefore, the layout of the bit line sense amplifier provided for each bit line pair is also easy.

Further, in the memory cell array, memory cells are arranged every other two rows in a diagonal direction with respect to the arrangement of the intersections of the bit lines and the word lines. In this case, the cell plates can be arranged in a band shape with a constant width in the oblique direction between the memory cell arrays.

(Example) Hereinafter, an example of the present invention is described with reference to drawings.

FIG. 1 shows a main configuration of a DRAM according to a first embodiment of the present invention. This DRAM has a folded bit line structure. Multiple pairs of bit lines BL (BL0, ▲ ▼, BL1, ▲ ▼, BL
2, ▲ ▼, BL3, ▲ ▼...) Constitute a bit line unit in two pairs, and are repeatedly arranged in a state in which one of the pairs is arranged between one pair. One of the two pairs of bit lines BL and ▼ constituting the bit line unit crosses at the center in the longitudinal direction as shown in the figure.
In this embodiment, the bit line sense amplifier for amplifying the memory cell data is a PMOS using a p-channel MOS transistor disposed at the intersection of one bit line pair BL, ▲ ▼.
Sense amplifier PSA (PSA0, PSA1, ...) and bit line pair BL, ▲
.. Are arranged at both ends of the ▼, and are constituted by NMOS sense amplifiers NSA (NSA0, NSA1,...) Composed of n-channel MOS transistors. Such a plurality of bit line pairs BL, ▲
▼ multiple word lines so as to intersect this
WL (WL0, WL1, WL2, WL3,...) Are provided. In the figure, 4
Although only one word line is shown, more word lines are actually arranged in parallel. The memory cell M is located at the intersection of the bit line BL, ▲ ▼ and the word line WL.
Is arranged. The memory cell M, as shown in FIG. 2, is composed of one switching MOS transistor Q _M and a memory capacitor C _M.

In this embodiment, in the memory cell array, two memory cells M are arranged for four word lines.
These memory cells are arranged in every two bit lines continuously along the word line direction and every two bit lines, and are sequentially shifted by 1/2 pitch in the bit line direction. In other words, this memory cell array includes the bit lines BL, ▲
With respect to the grid array formed by the intersections of the ▼ and the word lines WL, every other two rows are arranged diagonally.

This memory cell array also has two spare word lines SWL (SWL0, SWL2) on each side of the bit line intersection.
1, SWL2, SWL3) are prepared. In addition, bit line BL, ▲
Two dummy word lines ▲ ▼ (▲ ▼, ▲ ▼, ▲) on each side of the intersection of ▼
▼, ▲ ▼) are provided. Two dummy word lines ▼ and ▼ are arranged at both ends of the right cell array area, and the other two dummy word lines ▼ and ▲ are arranged at both ends of the left cell array area. Along these dummy word lines ▼, dummy cells DC are arranged at a ratio of one to two pairs of bit lines. Dummy cell, like the memory cell M, composed of one of the MOS transistors Q _D and one of the memory capacitor C _D As shown in Figure 3. The dummy cell may have a configuration including a write transistor _QDW as shown in FIG.

In this embodiment, four dummy word lines (▲ ▼
Is at “H” level during precharge, and one word line
When WL is selected, so-called reverse-phase driving is performed in which a dummy word line for driving a dummy cell connected to a bit line from which data of a selected memory cell is read is set to “L” level. In this case, furthermore, in this embodiment, driving is performed such that the two dummy word lines are simultaneously at the “L” level. For example, in FIG. 1, when the word line WL0 is selected and becomes “H” level, the dummy word line
▼ and ▲ ▼ are selected to go to L level. Similarly, when word line WL1 is selected, dummy word line ▲
▼ and ▲ ▼ are selected and become “L” level. When the word line WL2 is selected and becomes "H" level, the dummy word lines ▲ ▼ and ▲ ▼ are selected and become “L” level. When word line WL3 is selected, dummy word lines ▲ ▼, ▲ ▼
Is selected to attain the “L” level.

FIG. 5 schematically shows a main part layout of the memory cell array. Element forming regions 1 surrounded by an element isolation insulating film are formed on a silicon substrate as shown in the figure, and a lower polycrystalline silicon film forms a cell plate 2 which is a capacitor common electrode of a memory cell with strip-shaped turns running in an oblique direction. Have been. Then, the gate electrode 3 of the switching MOS transistor of the memory cell serving as the word line W is provided by the upper polycrystalline silicon film,
A MOS transistor is formed in a region sandwiched between the cell plates 2. The shaded area in the figure is the gate area of each MOS transistor. The bit lines BL and ▲ are simply shown by straight lines in the figure, but are formed by Al wiring or the like so as to contact the common drain region of the adjacent MOS transistor.

The crossing of the bit line pair is performed by the PMOS sense amplifier PSA as shown in FIG.
By using the gate electrode of the MOS transistor that constitutes the above, it can be realized without using a special cross wiring. FIG. 6 shows the principle configuration. The gate electrodes 51 and 52 in the figure are those of a sense-up MOS transistor connected to the pair of bit lines BL1 and BL. For example, the gate electrodes 51 and 52 are first-layer polysilicon film wirings, and the bit lines BL and ▲ ▼ is formed by the second layer polycrystalline silicon film. That is, the bit line BL0 is provided across the gate electrode 51 by using the gate electrode 51 connected to the bit line ▲ ▼ as a part of the wiring. Similarly, the bit line BL0 and ▼ are traversed on the gate electrode 52 by using the gate electrode 52 connected to the bit line と し て as a part of the wiring.

FIG. 7 more specifically shows the configuration of the bit line intersection and the PMOS sense amplifier PSA arranged here as an equivalent circuit. FIG. 8 shows the layout. As shown in FIG. 1, two pairs of bit lines BL0,
PMOS sense amplifier PSA provided for ▼, BL1, ▲ ▼
0 is actually a bit line pair BL0, ▲, as shown in FIG.
It comprises a sense amplifier PSA01 connected to ▼ and a sense amplifier PSA02 connected to the bit line pair BL1, ▲ ▼. The sense amplifier PSA01 is a dynamic sense amplifier constituted by p-channel MOS transistors Tr1 and Tr2, and the sense amplifier PSA02 is a dynamic sense amplifier constituted by p-channel MOS transistors Tr3 and Tr4. 4 that constitute these sense amplifiers
MOS transistors are arranged in four stages with their elongated gate electrodes arranged in the bit line direction. PMOS of Fig. 1
Sense amplifiers PSA11 and PSA12 that make up sense amplifier PSA1
The same applies to. Looking at the word line direction,
The MOS transistors constituting the sense amplifier are arranged at a ratio of one to four bit lines. Sense amplifier PSA11, PS
MOS transistors Tr3, Tr4, Tr5, Tr6,
In the region of..., Bit line intersections are performed on those gate electrodes in accordance with the configuration shown in FIG.

Although the specific configuration of the NMOS sense amplifier NSA is not shown, the configuration principle is the same as that of the PMOS sense amplifier, and is a dynamic type sense amplifier using an n-channel MOS transistor.

According to this embodiment, since one of the two pairs of bit lines constituting the bit line unit intersect at the center, the interference noise between the bit lines is reduced. For example, looking at the crossing bit line pairs BL1, ▲ ▼, these are the bit line pairs L0, ▲ ▼ and ▲
It is adjacent to ▼. The bit line pairs BL1, ▲ ▼ are not adjacent to each other. Therefore, interference noise between the pair of bit lines BL1, ▲ ▼ is greatly reduced. Bit line pair ▲
The interference effect of ▼ on the bit line pair BL1 and ▲ ▼ is BL
1, ▲ ▼ are almost the same because they intersect at about half the length of the wiring. That is, the interference by the bit line ▲ does not appear as a potential difference between BL1 and ▼, and does not lead to a decrease in the sense margin of the sense amplifier. Similarly,
The interference effect of the bit lines BL0 and ▼ on the bit lines BL1 and BL1 does not appear as a potential difference between BL1 and ▼.

Next, attention is paid to the bit line pair BL2, ▲ ▼. The bit line adjacent to the bit line pair BL2, ▲ ▼ is BL1, ▲ ▼
And BL3, ▲ ▼. Now the word line WL in Figure 1
0 is selected and the bit line ▲ along this word line WL0
Consider the worst pattern in which the "H" level is read from the upper memory cell and the "L" level is read from the memory cell on bit line BL3. At this time, the bit lines ▲ ▼ are bit lines
Although it receives interference noise from BL1, BL1 and ▲ ▼ are adjacent to each other for half the wiring length, so the size is
1/2. With respect to the interference noise received from the bit line BL3, the interference noise from the left half of BL3 is canceled out because it is capacitively coupled equal to BL2, ▲ ▼. Bit line BL
The right half of 3 gives interference noise to the bit line BL2 due to the coupling capacitance of half the wiring length. Bit line BL2, ▲
Since there is no adjacency, there is no interference noise between them. Since there is no memory cell at the intersection with the bit lines BL1 and BL3 on the word line WL0, the bit lines BL1 and BL3 are at the precharge potential, for example, (1/2) Vcc and do not change. As described above, even in the sense amplifier of the bit line pair BL2, ▲ ▼, the interference noise is reduced to 従 来 of the conventional case even in the worst case.

Further, in this embodiment, when selecting one word line, it is necessary to select two dummy word lines. However, two dummy word lines are prepared and one dummy word line is selected. The load on each dummy word line is lighter than in the system. Furthermore, in the method in which one of the four dummy word lines is selected and set to the “L” level, the remaining three dummy word lines are set to the “H” level and the bit line capacity increases by the dummy cell capacity. However, in this embodiment, since only one dummy cell is connected to one bit line, there is no increase in bit line capacity. Therefore, high sense sensitivity can be obtained.

Further, according to the memory cell arrangement method according to this embodiment,
As shown in FIG. 5, the cell plate 2 is arranged in a band shape with a constant width without being constricted, the line / space is gentle, processing is easy, and a stable reference potential can be given to the memory cell array. .

FIG. 9 shows a main configuration of a DRAM according to a second embodiment of the present invention. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted. This embodiment differs from the embodiment of FIG. 1 in that the driving of the dummy word line DWL is in normal phase. That is, the four dummy word lines DWL are kept at “L” level during the precharge time, and when one word line is selected and turned to “H” level, two of the four dummy word lines DWL become The book is selected and becomes “H” level. For example, when word line WL0 is selected, dummy word line DWL0
1, DWL03 is selected and becomes “H” level. Similarly, when the word line WL1 is selected, the dummy word lines DWL01 and DWL12 are selected. When the word line WL2 is selected, the dummy word lines DWL12 and DWL23 are selected. When the word line WL3 is selected, the dummy word lines DWL23 and DWL03 are selected.

According to this embodiment, the same effect as that of the previous embodiment can be obtained.

FIG. 10 shows a main configuration of a DRAM according to a third embodiment of the present invention, which is a modification of the configuration shown in FIG. In the embodiment of FIG.
Although the PMOS sense amplifier PSA is arranged at the center of the memory cell array, in this embodiment, it is divided for each bit line and arranged at both ends of the memory cell array together with the NMOS sense amplifier. That is, the bit line sense amplifier SA (SA0, SA0,
SA1, SA2,...) Respectively include an NMOS sense amplifier and a PMOS sense amplifier. When the PMOS sense amplifiers are also arranged at both ends of the memory cell array in this manner, the gate electrodes of the sense amplifiers cannot be used as they are for the cross wiring of the bit lines as described with reference to FIGS. Cross wiring can be performed in the same manner as in the figure.

Although not shown in the figure, the arrangement of the sense amplifiers can be changed in the same manner as in FIG. 10 for the embodiment shown in FIG.

According to this embodiment, the same effect as that of the previous embodiment can be obtained.

FIG. 11 shows a DRAM according to a fourth embodiment of the present invention. The difference from the embodiment of FIG. 1 is that two dummy cells DC are provided for one bit line. That is,
One side of the pair of bit lines BL0, ▲ ▼ has dummy word lines ▲ ▼, ▲
The dummy cell DC selected by ▼ is placed, while BL
0 has a dummy word line ▲
Dummy cells DC selected by ▼ and ▲ ▼ are arranged. In other words, the dummy word line ▲ ▼
(▲ ▼, ▲ ▼, ▲ ▼, ▲
In ▼), two dummy cells DC are arranged for each two pairs of bit lines.

In this embodiment, the dummy word line ▼ is driven at the “H” level at the time of precharging, and is driven in the opposite phase. However, one of the four lines is selected and set to the “L” level. For example, when the word line WL0 is selected and becomes “H” level, the dummy word line 線 is simultaneously selected and becomes “L” level. Similarly, when word line WL1 is selected, dummy word line ▲ ▼ is selected, when word line WL2 is selected, dummy word line ▲ ▼ is selected, and when word line WL3 is selected, dummy word line ▲ ▼ is selected. Is selected.

Therefore, in this embodiment, one dummy cell is connected to the bit line to which the selected memory cell is connected, and two dummy cells are connected to the bit line paired with this.
Further, the number of dummy cells is required twice as compared with the embodiment of FIG. However, since only one dummy word line needs to be selected, the selecting means is simplified.

FIG. 12 shows a DRAM according to a fifth embodiment of the present invention. This is a modification of the embodiment of FIG. 11, in which the dummy word line DWL is driven in normal phase. The dummy word line DWL is at the “L” level at the time of precharge, and one of the dummy word lines DWL is selectively at the “H” level. For example, when word line WL0 is selected, dummy word line DWL0 is selected, and when word line WL1 is selected, dummy word line DWL1 is selected, and word line WL2 is selected.
Is selected, the dummy word line DWL2 is selected,
When word line WL3 is selected, dummy word line DWL3
Is selected.

FIG. 13 shows a DRAM according to a sixth embodiment of the present invention. This embodiment uses the PMPS sense amplifier PSA of the DRAM of the embodiment shown in FIG.
Are arranged together with NMOS sense amplifiers at both ends of the memory cell array as in FIG. A similar change in the sense amplifier arrangement can be made for the embodiment shown in FIG.

By the way, in a large-scale DRAM, a memory cell array is divided into a plurality of (for example, four or eight) sub-cell arrays in a bit line direction, and a shared sense amplifier system in which a bit line sense amplifier is shared by adjacent sub-cell arrays is employed. You. The memory cell array in the embodiments described so far corresponds to one subcell array in such a large-scale DRAM of the shared sense amplifier system. The bit line sense amplifiers arranged at both ends of the memory cell array are shared with the adjacent sub cell array. Further, in such a shared sense amplifier type DRAM, not only the bit line sense amplifier but also the dummy cell and the dummy word line can be shared by the adjacent sub-cell arrays to improve the degree of integration. Such an embodiment is described below.

FIG. 14 shows a main configuration of a DRAM of such an embodiment. This is based on the memory cell array configuration shown in FIG. The NMOS sense amplifiers MSA arranged at both ends of the subcell array 11 are connected to the subcell array via select gates SG0 and SG1.
11 is connected to the bit line BL. Subcell array 11
Is connected to the bit line BL in the adjacent sub-cell array 12 via the selection gate SG, and is shared by the two sub-cell arrays 11 and 12. Although omitted in the figure, the left side of the sub-cell array 11
Similarly, the NMOS sense amplifier NSA is shared with the adjacent sub cell array. In this embodiment, the dummy cell DC is also arranged near the NMOS sense amplifier NSA, and is connected to the bit line in the sub-cell array via the selection gate SG. That is, the dummy cell DC and the dummy word line ▼ for driving the dummy cell DC share the adjacent sub-cell array similarly to the NMOS sense amplifier.

According to this embodiment, the number of dummy cells and dummy word lines is reduced by half, and high integration of the DRAM is achieved.

FIG. 15 shows a DRAM of another embodiment of the shared sense amplifier system.
It is a main part configuration. In this embodiment, the dummy cells and the dummy word lines are shared similarly to FIG. 14, based on the memory cell array configuration of the embodiment in FIG. 9 in which the dummy word lines are driven in normal phase.

FIG. 16 shows another embodiment of the shared sense amplifier system.
This is the main configuration of the DRAM. This embodiment shares a dummy cell and a dummy word line based on the configuration of the embodiment of FIG. 10 in which a PMOS sense amplifier is arranged at both ends of a memory cell array together with an NMOS sense amplifier. The PMOS sense amplifier PSA is located at both ends of each sub-cell array.
Unlike the S sense amplifier, it is not shared.

The same effects as those of the embodiment shown in FIG. 14 can be obtained by the embodiments shown in FIGS.

According to the present invention, one of the two bit lines intersects at the center of the memory array, and the other bit line pair is interposed between one bit side pair. By inserting one bit line, the effect of capacitive coupling between adjacent bit lines can be reduced, and interference noise can be reduced. By properly arranging dummy word lines and dummy cells, even if twisted bit lines exist, DRAM
Can be operated properly. Further, according to the memory cell arrangement of the present invention, the layout of the cell plate electrodes is facilitated. Furthermore, in the DRAM of the shared sense amplifier type, the integration of the dummy cells and the dummy word lines can be achieved to achieve high integration.

[Brief description of the drawings]

1 is a circuit diagram of a DRAM according to a first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram showing a memory cell configuration thereof, FIG. 3 is an equivalent circuit diagram showing a dummy cell configuration thereof, and FIG. FIG. 5 is a schematic layout diagram of a memory cell array, FIG. 6 is a diagram showing a method of crossing bit lines, and FIG. 7 is a specific configuration of a PMOS sense amplifier unit. FIG. 8 is a layout diagram thereof, FIG. 9 is a circuit diagram of a DRAM according to a second embodiment of the present invention, and FIG. 10 is a circuit of a DRAM according to a third embodiment of the present invention. FIG. 11, FIG. 11 is a circuit diagram of a DRAM according to a fourth embodiment of the present invention, FIG. 12 is a circuit diagram of a DRAM according to a fifth embodiment of the present invention, and FIG. 13 is a sixth embodiment of the present invention. FIG. 14 is a circuit diagram of such a DRAM, and FIG. FIG. 15 is a circuit diagram of the DRAM of the embodiment of the shared sense amplifier system based on the configuration of the second embodiment. FIG. 16 is an embodiment of the shared sense amplifier system based on the configuration of the third embodiment. FIG. 4 is a circuit diagram of an example DRAM. BL, ▲ ▼… Bit line, WL …… Word line, DWL, ▲
▼… Dummy word line, SWL …… Spare word line,
M: memory cell, DC: dummy cell, PSA: PMOS sense amplifier, NSA: NMOS sense amplifier, 1 ... element formation region, 2 ... cell plate, 3 ... gate electrode (word line), 11, 12 ... Sub cell array, SG ... Select gate.

Continuation of front page (56) References JP-A-64-14793 (JP, A) JP-A-64-79994 (JP, A) JP-A-64-57494 (JP, A) JP-A-63-237291 (JP) JP-A-63-241788 (JP, A) JP-A-2-1833491 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/407

Claims (2)

(57) [Claims] A plurality of bit lines, a plurality of word lines, four dummy word lines, a plurality of memory cells,
A plurality of dummy cells and a plurality of sense amplifiers are provided, and the plurality of bit lines form bit line pairs in which the bit lines are folded every two lines, and these bit line pairs are formed every two pairs. Forming a bit line unit, wherein a first pair of bit lines in a bit line unit are parallel to each other and a second pair of bit lines in a bit line unit extend parallel to the first pair of bit lines And intersect each other at approximately the midpoint of the second pair, one of the bit lines of the first pair is provided between the second pair, and the plurality of word lines are perpendicular to the bit lines. Intersect, four dummy word lines extend parallel to the word lines and intersect the bit lines, two dummy word lines are located on one side of the intersection of the second pair, and the other two A dummy word line is disposed on the other side of the intersection of the second pair, and a plurality of memory cells are formed by bit lines and word lines. Any two adjacent memory cells connected to an intersection selected from the intersections with the same word line and connected to the same word line form a group arranged for every two adjacent bit lines. , Any two adjacent memory cells connected to the same bit line are shifted by a half pitch from two corresponding adjacent memory cells connected to any adjacent word line, and a plurality of dummy cells At least one dummy cell is connected to each of the bit lines, and each of the plurality of sense amplifiers is connected to a selected one of the intersections between the bit line and the dummy word line. A dynamic semiconductor memory device provided for each pair. 2. A dynamic semiconductor memory device having a memory cell array composed of a plurality of sub-arrays in which two adjacent ones share a sense amplifier, comprising: a plurality of bit lines; a plurality of word lines; A plurality of dummy word lines, a plurality of memory cells, a plurality of dummy cells, and a plurality of sense amplifiers, and the plurality of bit lines are bit line pairs each having a folded bit line. These bit line pairs form a bit line unit for every two pairs, the bit lines of the first pair of bit line units are arranged parallel to each other, and the bit line units of the second pair of bit line units are formed. Bit lines extend parallel to the first pair of bit lines and intersect each other at approximately the midpoint of the second pair, with one of the first pair of bit lines being between the second pair. Multiple word lines are perpendicular to the bit lines Intersect, four dummy word lines extend parallel to the word lines and intersect the bit lines, two dummy word lines are located on one side of the intersection of the second pair, and the other two A dummy word line is disposed on the other side of the second pair of intersections, and a plurality of memory cells are connected to an intersection selected from bit line and word line intersections, and Any two adjacent memory cells connected to the same line form a group arranged for every two adjacent bit lines, and any two adjacent memory cells connected to the same bit line 2 corresponding to the adjacent word line
A plurality of dummy cells are connected to an intersection selected from the intersections of the bit lines and the dummy word lines, and at least one dummy cell is shifted from the adjacent memory cells by a half pitch. A dynamic semiconductor memory device connected to each bit line, wherein a plurality of sense amplifiers are provided for two corresponding pairs of bit lines of both adjacent sub arrays.