JPH0738555B2 - Hybrid circuit - Google Patents

Hybrid circuit

Info

Publication number
JPH0738555B2
JPH0738555B2 JP1117713A JP11771389A JPH0738555B2 JP H0738555 B2 JPH0738555 B2 JP H0738555B2 JP 1117713 A JP1117713 A JP 1117713A JP 11771389 A JP11771389 A JP 11771389A JP H0738555 B2 JPH0738555 B2 JP H0738555B2
Authority
JP
Japan
Prior art keywords
circuit
impedance
balanced impedance
transmission
subscriber line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1117713A
Other languages
Japanese (ja)
Other versions
JPH02295304A (en
Inventor
友一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1117713A priority Critical patent/JPH0738555B2/en
Publication of JPH02295304A publication Critical patent/JPH02295304A/en
Publication of JPH0738555B2 publication Critical patent/JPH0738555B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、メタリック加入者線路および送受信回路間の
2線−4線変換用に使用され、近端エコーを抑圧するた
めの平衡インピーダンス回路を具備した、ハイブリッド
回路に関する。
The present invention relates to a balanced impedance circuit for suppressing near-end echo, which is used for 2-wire to 4-wire conversion between a metallic subscriber line and a transmitting / receiving circuit. The present invention relates to a hybrid circuit provided.

〔従来の技術〕[Conventional technology]

従来のこの種のハイブリッド回路は、第2図に示すよう
な構成を有する。第2図において、参照番号22は平衡イ
ンピーダンス回路、14は加入者線路、15は減算器を、そ
れぞれ示す。第3図は、平衡インピーダンス回路22の一
構成例を示す。第2図において、遠端を抵抗Rで終端し
た加入者線路の近端側の入力インピーダンスをZinと
し、平衡インピーダンス回路22のインピーダンスをZaと
する。
A conventional hybrid circuit of this type has a configuration as shown in FIG. In FIG. 2, reference numeral 22 is a balanced impedance circuit, 14 is a subscriber line, and 15 is a subtractor. FIG. 3 shows an example of the configuration of the balanced impedance circuit 22. In FIG. 2, the input impedance on the near end side of the subscriber line whose far end is terminated by a resistor R is Zin, and the impedance of the balanced impedance circuit 22 is Za.

2つの抵抗Rと、インピーダンスZaおよびZinとでブリ
ッジ回路を構成してあるので、送信端Aから受信端Bへ
回り込む回り込む送信信号成分である近端エコーEは、
次式(1)で表わされる。
Since the bridge circuit is configured by the two resistors R and the impedances Za and Zin, the near-end echo E, which is the transmission signal component that wraps around from the transmission end A to the reception end B, is
It is expressed by the following equation (1).

式(1)から明らかなごとく、近端エコーを完全に抑圧
できる平衡インピーダンスZaは、 Za=Zin …(2) となる。つまり、平衡インピーダンスZaを加入者線路の
インピーダンスZinに一致させれば、近端エコーを完全
に抑圧できる。しかし通常、回路を簡単化するため、平
衡インピーダンスZaを一定値に固定することが多い。
As is clear from the equation (1), the balanced impedance Za that can completely suppress the near-end echo is Za = Zin (2). That is, the near-end echo can be completely suppressed by matching the balanced impedance Za with the impedance Zin of the subscriber line. However, usually, in order to simplify the circuit, the balanced impedance Za is often fixed to a constant value.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上述した従来のハイブリッド回路では、平衡インピーダ
ンスZaを一定値に固定してあるので、加入者線路の長さ
が変ったり、加入者線路の線種が異なったり、あるいは
線路にブリッジドタップが付加接続されている場合の様
に、加入者線路の入力インピーダンスZinが一定してい
ない場合、おのおのに対し最適な平衡インピーダンスを
求めないと近端エコーを十分に抑圧できないという欠点
を持つ。更に、送受信回路をLSI化した場合、平衡イン
ピーダンスZaを固定してしまうと、上述した様に入力イ
ンピーダンスZinが異なる場合に近端エコーを十分に抑
圧できなくなり、LSIのダイナミックレンジを狭めると
いう欠点もある。
In the conventional hybrid circuit described above, the balanced impedance Za is fixed to a constant value, so the length of the subscriber line changes, the line type of the subscriber line is different, or a bridged tap is additionally connected to the line. When the input impedance Zin of the subscriber line is not constant, as in the case described above, the near-end echo cannot be sufficiently suppressed unless the optimum balanced impedance is obtained. Furthermore, if the transmitter / receiver circuit is an LSI, if the balanced impedance Za is fixed, the near-end echo cannot be sufficiently suppressed when the input impedance Zin is different, as described above, and the dynamic range of the LSI is narrowed. is there.

〔課題を解決するための手段〕 本発明のハイブリッド回路は、加入者線路および送受信
回路の間で2線−4線変換を行うハイブリッド回路にお
いて、前記送受信回路の送信側から受信側への信号回り
込みで生じる近端エコーのピーク値を検出するピーク検
出回路と、前記ピーク検出回路の出力信号に応答して平
衡インピーダンスの選択指示用の制御信号を発生する制
御回路と、前記制御信号に応答して平衡インピーダンス
を可変設定する平衡インピーダンス回路とを備えてい
る。
[Means for Solving the Problems] A hybrid circuit of the present invention is a hybrid circuit that performs 2-wire to 4-wire conversion between a subscriber line and a transmission / reception circuit, and a signal sneak from the transmission side to the reception side of the transmission / reception circuit. In the peak detection circuit for detecting the peak value of the near-end echo generated in, the control circuit for generating a control signal for selecting the balanced impedance in response to the output signal of the peak detection circuit, and in response to the control signal And a balanced impedance circuit that variably sets the balanced impedance.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。同図に
おいて、参照番号11は平衡インピーダンス回路、12は制
御回路、13はピーク検出回路、14は加入者線路、15は減
算器を、それぞれ示す。平衡インピーダンス回路11の一
構成例を第4図に示す。
FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, reference numeral 11 is a balanced impedance circuit, 12 is a control circuit, 13 is a peak detection circuit, 14 is a subscriber line, and 15 is a subtractor. A configuration example of the balanced impedance circuit 11 is shown in FIG.

まず、実際の通信を行う前にトレーニング期間を設けて
おき、送信信号として孤立波を入力する。入力された孤
立波の送信端Aでの振幅をVin、受信端Cに伝わる孤立
波の振幅をV2とすると、加入者線路14の入力インピーダ
ンスZinおよび抵抗Rでの分圧により、 となる。この孤立波の振幅V2は加入者線路の線種、長
さ、及びブリッジドタップの有無によって、第5図に示
すように変化する。
First, a training period is provided before actual communication, and a solitary wave is input as a transmission signal. Assuming that the amplitude of the input solitary wave at the transmission end A is Vin and the amplitude of the solitary wave transmitted to the reception end C is V 2 , the input impedance Zin of the subscriber line 14 and the voltage division at the resistance R result in Becomes The amplitude V 2 of this solitary wave changes as shown in FIG. 5 depending on the line type of the subscriber line, the length, and the presence / absence of a bridged tap.

ピーク検出回路13は、受信端Cでの孤立波の振幅V2のピ
ーク値を検出し、制御回路12に入力する。制御回路12に
は、あらおじめ複数種のしきい値V0〜V4を設定してお
り、振幅V2のピーク値がどのしきい値区間に属するかを
検出して、平衡インピーダンス回路11に制御信号を送
る。
The peak detection circuit 13 detects the peak value of the amplitude V 2 of the solitary wave at the receiving end C and inputs it to the control circuit 12. In the control circuit 12, a plurality of types of threshold values V 0 to V 4 are set, and it is detected which threshold value the peak value of the amplitude V 2 belongs to, and the balanced impedance circuit 11 is detected. Send a control signal to.

平衡インピーダンス回路11は、第4図に示す様に、あら
かじめ孤立波のピーク値の区間に対応するインピーダン
ス成分Ra1〜Ra4を内蔵してあり、制御回路12の制御信号
に応じて、そのつど最適な平衡インピーダンスを選択す
ることにより、受信端Bでの孤立波エコーを抑圧でき
る。通信へ移行する時に、上述した手順で選択された平
衡インピーダンスをホールドすることにより、通信中に
おける近端エコーは抑圧されることになる。
As shown in FIG. 4, the balanced impedance circuit 11 has built-in impedance components Ra 1 to Ra 4 corresponding to the section of the peak value of the solitary wave in advance, and in accordance with the control signal of the control circuit 12, each time. By selecting the optimum balanced impedance, the solitary wave echo at the receiving end B can be suppressed. By holding the balanced impedance selected by the above-mentioned procedure when shifting to communication, the near-end echo during communication is suppressed.

なお本実施例では、近端エコーのピーク値を検出し、こ
れに応じた平衡インピーダンスを選択して近端エコーを
抑圧するので、第5図に示すような孤立波応答に2つの
山を生じるブリッジドタップの有る場合でも、応答波形
のピークを検出して近端エコーを抑圧でき、ブリッジド
タップの有無に拘らず近端エコーを抑圧できる。
In this embodiment, since the peak value of the near-end echo is detected and the balanced impedance corresponding to the peak value is selected to suppress the near-end echo, two peaks are generated in the solitary wave response as shown in FIG. Even when there is a bridged tap, the peak of the response waveform can be detected to suppress the near-end echo, and the near-end echo can be suppressed regardless of the presence or absence of the bridged tap.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明では、トレーニング期間に送
信信号としてトレーニング信号を入力して受信端に回り
込むトレーニング信号のレベル値を検出し、この検出結
果に応じて平衡インピーダンスを可変選択することによ
り、加入者線路の線種、長さ、及びブリッジドタップの
有無に拘らずに近端エコーを抑圧できる効果がある。
As described above, in the present invention, the training signal is input as the transmission signal during the training period, the level value of the training signal that wraps around to the receiving end is detected, and the balanced impedance is variably selected according to the detection result. The near-end echo can be suppressed regardless of the line type, the length, and the presence or absence of the bridged tap of the main line.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
従来のハイブリッド回路のブロック図、第3図は従来の
ハイブリッド回路中の平衡インピーダンス回路の構成例
を示す回路図、第4図は本発明の実施例中の平衡インピ
ーダンス回路の構成例を示す回路図、第5図は本発明の
実施例の動作を説明するための信号波形図である。 11,22……平衡インピーダンス回路、12……制御回路、1
3……ピーク検出回路、14……加入者線路、15……減算
器、R……抵抗。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional hybrid circuit, FIG. 3 is a circuit diagram showing a configuration example of a balanced impedance circuit in the conventional hybrid circuit, and FIG. FIG. 5 is a circuit diagram showing a configuration example of the balanced impedance circuit in the embodiment of the present invention, and FIG. 5 is a signal waveform diagram for explaining the operation of the embodiment of the present invention. 11,22 …… Balanced impedance circuit, 12 …… Control circuit, 1
3 ... Peak detection circuit, 14 ... Subscriber line, 15 ... Subtractor, R ... Resistance.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】加入者線路および送受信回路の間で2線−
4線変換を行うハイブリッド回路において、前記送受信
回路の送信側から受信側への信号回り込みで生じる近端
エコーのピーク値を検出するピーク検出回路と、前記ピ
ーク検出回路の出力信号に応答して平衡インピーダンス
の選択指示用の制御信号を発生する制御回路と、前記制
御信号に応答して平衡インピーダンスを可変設定する平
衡インピーダンス回路とを備えていることを特徴とする
ハイブリッド回路。
1. Two lines between a subscriber line and a transmission / reception circuit.
In a hybrid circuit that performs 4-wire conversion, a peak detection circuit that detects a peak value of a near-end echo that occurs due to a signal wraparound from a transmission side to a reception side of the transmission / reception circuit, and a balance in response to an output signal of the peak detection circuit. A hybrid circuit comprising: a control circuit for generating a control signal for instructing selection of impedance; and a balanced impedance circuit for variably setting the balanced impedance in response to the control signal.
JP1117713A 1989-05-10 1989-05-10 Hybrid circuit Expired - Lifetime JPH0738555B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1117713A JPH0738555B2 (en) 1989-05-10 1989-05-10 Hybrid circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1117713A JPH0738555B2 (en) 1989-05-10 1989-05-10 Hybrid circuit

Publications (2)

Publication Number Publication Date
JPH02295304A JPH02295304A (en) 1990-12-06
JPH0738555B2 true JPH0738555B2 (en) 1995-04-26

Family

ID=14718461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1117713A Expired - Lifetime JPH0738555B2 (en) 1989-05-10 1989-05-10 Hybrid circuit

Country Status (1)

Country Link
JP (1) JPH0738555B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5686913B2 (en) * 2014-02-25 2015-03-18 スパンション エルエルシー Driver circuit and driver circuit adjustment method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601929A (en) * 1983-06-17 1985-01-08 Japanese National Railways<Jnr> Method and device for reducing echo of hybrid circuit

Also Published As

Publication number Publication date
JPH02295304A (en) 1990-12-06

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