JPH0738409A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce ringing generated in an output signal by providing a 1st and a 2nd output drive circuit and operating the 2nd output drive circuit for a period till a change level in an output signal reaches a predetermined level. CONSTITUTION:When a level of an output signal changes from an L to an H level, an output terminal 32 is charged through a charging path by 1st and 2nd output drive circuits 10,20 for a period till the level reaches a prescribed level Vcc-¦VthP¦ (absolute value of a threshold voltage of a P-channel MOS transistor(TR)). Thus, an output signal rises rapidly till the level reaches the Vcc-¦VthP¦. The output terminal 32 is charged through the charging path comprising only the 1st circuit 10 after the output signal reaches the level Vcc-¦VthP¦. Since the charging current is suppressed by a resistor 11 to be a sufficiently small current, the production of ringing by an overshoot in a power wire is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit provided in a signal output stage of an analog semiconductor integrated circuit.

[0002]

2. Description of the Related Art An output circuit provided in a signal output stage of an analog semiconductor integrated circuit for audio or the like has conventionally been constructed as shown in FIG. That is, the signal input terminal 51
A P-channel MIS transistor, for example, a MOS transistor 52 and an N-channel MIS transistor, for example, both gates of a MOS transistor 53 are connected to. The sources of the MOS transistors 52 and 53 are connected to the power supply voltage Vcc on the positive side and the power supply voltage Vss on the ground side, respectively, and the drains are connected to the signal output terminal 54.

In the output circuit having such a configuration, when the input signal applied to the signal input terminal 51 is at "L" (Vss) level, the P-channel MOS transistor 52 is turned on and the N-channel MOS transistor 53 is turned on. Is turned off, and a signal of "H" (Vcc) level is output from the signal output terminal 54.

Next, when the input signal is inverted from the "L" level to the "H" level, the P-channel MOS transistor 52
Is switched from on to off, and N-channel MOS
The transistor 53 switches from off to on. As a result, the output signal switches from "H" level to "L" level.

By the way, since the time when the level of the input signal is switched is usually very short, overshoot and undershoot occur in the output waveform as shown in FIG. The reasons why the overshoot and the undershoot occur are as follows.

Generally, in a semiconductor integrated circuit, a semiconductor chip is housed in a package, and electrodes on the semiconductor chip and lead pins of the package are connected to each other via a lead frame and bonding wires. An inductance component exists in each of the lead frame and the bonding wire. When this is represented by L, if the value of the power supply current i flowing in the semiconductor chip changes, the ringing (L × (di / dt)) is generated. This is because overshoot and undershoot) occur in the power supply wiring, and this rides on the output signal. When such ringing is added to the output waveform, the circuit at the next stage receiving the signal may malfunction.

[0007]

As described above, in the conventional output circuit, there is a problem that ringing occurs in the output signal, which causes malfunction of other circuits. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide an output circuit capable of reducing ringing occurring in an output signal.

[0008]

The output circuit of the present invention comprises:
A signal input terminal and a signal output terminal, a first output drive circuit that generates a signal according to an input signal applied to the signal input terminal, and outputs the signal to the signal output terminal, and the signal output terminal is applied to the signal input terminal. Receives an input signal and an output signal output from the signal output terminal, and generates a signal according to the input signal during the period until the level reaches a predetermined level when the output signal changes, and outputs the signal to the signal output terminal. And a second output drive circuit.

[0009]

The output circuit is divided into the first and second output drive circuits,
The first output drive circuit drives the output terminal in response to the input signal, and the second output drive circuit drives the output terminal in response to the input signal until the level reaches a predetermined level when the output signal changes. After that, the output terminal is driven only by the first output drive circuit.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. 1 is a circuit diagram showing a configuration of an output circuit according to a first embodiment of the present invention. This output circuit is composed of a first output drive circuit 10 and a second output drive circuit 20.

The first output drive circuit 10 has a first resistance means, for example, a resistance 11 whose one end is connected to the power supply voltage Vcc on the positive polarity side, and a P channel whose source is connected to the other end of this resistance 11. MIS transistor, eg, MOS transistor
12, a second resistance means, one end of which is connected to the power supply voltage Vss on the ground side, for example, a resistance 13, and a source of which is connected to the other end of the resistance 13 and a drain of which is connected to the drain of the MOS transistor 12. N-channel MOS transistor 14
It consists of and.

The second output drive circuit 20 has a P-channel MIS transistor, for example, a MOS transistor 21, whose source is connected to the power source voltage Vcc, and a source which is the above-mentioned MO transistor.
A P-channel MIS transistor connected to the drain of the S transistor 21, for example, a MOS transistor 22,
N channel M whose source is connected to the power supply voltage Vss
An IS transistor, for example a MOS transistor 23, and an N-channel MIS transistor, for example M, whose source is connected to the drain of the MOS transistor 23 and whose drain is connected to the drain of the MOS transistor 22.
It is composed of an OS transistor 24.

Then, M in the first output drive circuit 10 is
The gates of the OS transistors 12 and 14 and the gates of the MOS transistors 22 and 24 in the second output drive circuit 20 are connected to the signal input terminal 31, respectively, and the first output drive circuit 10 is connected.
The drain common points of the MOS transistors 12 and 14 inside and the drain common points of the MOS transistors 22 and 24 inside the second output drive circuit 20 are connected to the signal output terminal 32, respectively.

Next, the operation of the circuit configured as described above will be described with reference to the waveform chart of FIG. First, the signal input terminal
When the input signal applied to 31 is at "H" level, the MOS transistor 12 in the first output drive circuit 10 turns off,
The MOS transistor 14 is turned on, the MOS transistors 22 and 23 are turned off in the second output drive circuit 20, and
S transistors 21 and 24 are on. Therefore, the signal output terminal 32 is discharged to the VSS side through the MOS transistor 14 and the resistor 13 in the first output drive circuit 10 in series, and the output signal is at the "L" level.

Next, the input signal starts to drop from "H" level to "L" level. When the input signal level drops,
The MOS transistor 12 in the first output drive circuit 10 switches from off to on, and the MOS transistor 14 switches from on to off. Therefore, the signal output terminal 32 is connected to the first
11 and MOS transistor 12 in the output drive circuit 10 of
Starts to be charged by Vcc through the series. Meanwhile, the second
In the output drive circuit 20, the MOS transistor 22 is switched from off to on, and the MOS transistor 24 is switched from on to off. At this time, the level of the signal output terminal 32 has not risen sufficiently, so the second output drive circuit
Within 20, the MOS transistor 21 is still on and the MOS transistor 23 is still off. Therefore, immediately after the input signal is lowered from the "H" level to the "L" level, the signal output terminal 32 starts to be charged by Vcc through the MOS transistors 21 and 22 in the second output drive circuit 20 in series. . At this time, the signal output terminal 32 is the first
Since the output drive circuit 10 and the second output drive circuit 20 are charged in parallel through the two paths, the output waveform rapidly increases as shown in the period a in FIG.

The level of the output signal is the power supply voltage V
A potential that is lower than cc by the absolute value | VthP | of the threshold voltage VthP of the P-channel MOS transistor, that is, (Vcc
-| VthP |), the second output drive circuit 20
The MOS transistor 21 therein switches from on to off, the charging operation of the signal output terminal 32 by the second output drive circuit 20 is stopped, and the signal output terminal 32 is charged only by the first output drive circuit 10. . Therefore, the period b in FIG.
As shown in, the slope of the output waveform becomes gentler than in the case of the previous period a, and then the output signal reaches Vcc (period c in FIG. 2). When the output signal exceeds the threshold voltage VthN of the N-channel MOS transistor, the MOS transistor 23 in the second output drive circuit 20 is switched from off to on, but the MOS transistor 24 is off in advance. Therefore, this second output drive circuit 20
Does not cause the discharge path of the signal output terminal 32.

In this way, when the output signal changes from the "L" level to the "H" level until the level reaches a predetermined level (Vcc- | VthP |), the first,
Since the output terminal 32 is charged by the charging path formed by the second output drive circuits 10 and 20, the output signal is at the level (Vcc
-| VthP |) rises rapidly. Then, after the output signal reaches the above level (Vcc- | VthP |), the output terminal 32 is charged by the charging path only by the first output drive circuit 10, and the value of the charging current at this time is the resistance 11. Since it can be suppressed to a sufficiently small value by
The occurrence of ringing due to overshoot in the power supply wiring as described above is reduced.

Next, the input signal starts to rise from "L" level to "H" level. When the input signal level rises,
The MOS transistor 12 in the first output drive circuit 10 switches from on to off, and the MOS transistor 14 switches from off to on. Therefore, the signal output terminal 32 is connected to the first
MOS transistor 14 and resistor 13 in the output drive circuit 10 of
Starts to be discharged toward Vss through the series. on the other hand,
In the second output drive circuit 20, the MOS transistor 22 switches from on to off, and the MOS transistor 24 switches from off to on. At this time, the signal output terminal 32
, The MOS transistor 23 is still on in the second output drive circuit 20, and the MOS transistor 21 is still off.
Therefore, immediately after the input signal is lowered from the “L” level to the “H” level, the signal output terminal 32 is connected to the V level via the MOS transistors 24 and 23 in the second output drive circuit 20 in series.
It begins to be discharged toward ss. At this time, the signal output terminal
32 is 2 of the first output drive circuit 10 and the second output drive circuit 20.
Since the discharge is performed in parallel in one path, the output waveform rapidly decreases as shown in the period d in FIG.

Then, when the level of the output signal becomes lower than the threshold voltage VthN of the N-channel MOS transistor, the MOS transistor 23 in the second output drive circuit 20 switches from ON to OFF, and the second Output drive circuit
The discharging operation of the signal output terminal 32 by 20 is stopped, and the discharging of the signal output terminal 32 is performed only by the first output drive circuit 10. Therefore, as shown in the period e in FIG. 2, the slope of the output waveform becomes gentler than in the previous period d, and then the output signal reaches VSS (period f in FIG. 2).

As described above, when the output signal changes from the "H" level to the "L" level until the level reaches a predetermined level (VthN), the first and second output drive circuits 10 and 20. Since the output terminal 32 is discharged by the discharge path due to, the output signal rapidly decreases until the level (VthN) is reached. Then, after the output signal reaches the above level (VthN), the output terminal 32 is discharged by the discharge path of only the first output drive circuit 10, and the value of the discharge current at this time is a sufficiently small value by the resistor 13. Therefore, the occurrence of ringing due to undershoot in the power supply wiring as described above is reduced.

As described above, in the above-described embodiment, the occurrence of ringing due to overshoot and undershoot in the power supply wiring is reduced, so that ringing occurring in the output waveform can also be reduced. FIG. 3 is a waveform diagram showing the result of SPICE simulation when the input signal changes in the above embodiment. As shown in the figure, ringing due to overshoot and undershoot occurring in the output waveform is significantly reduced as compared with the conventional one in FIG.

In the above embodiment, the case where the resistance element is used as the resistance means has been described, but it is also possible to use a MOS transistor or the like instead of the resistance element. Next, another embodiment of the present invention will be described.

FIG. 4 shows a second embodiment of the output circuit according to the present invention, in which only the first output drive circuit 10 is shown. Second output drive circuit in this embodiment
Since 20 is the same as in the case of the first embodiment, its explanation is omitted.

First output drive circuit 10 in this embodiment
Then, the resistors 11 and 13, the P-channel MOS transistor 12 and the N-channel MOS transistor 14 are provided, and further, the P-channel MOS transistor is provided.
15 and N-channel MOS transistor 16 are newly added. That is, the source of the P-channel MOS transistor 15 is the power supply voltage Vcc, and the drain is the M-channel.
The drains of the OS transistors 12 and 14 are connected to a common connection point, and the gate is connected to the signal input terminal 31. Also,
The source of the N-channel MOS transistor 16 is at the ground voltage Vss, and the drain is the MOS transistors 12 and 14.
Is connected to the common drain connection point of, and the gate is connected to the signal input terminal 31.

Then, the sum of the charging ability for the signal output terminal 32 in the series circuit including the resistor 12 and the MOS transistor 12 and the charging ability for the signal output terminal 32 by the newly provided MOS transistor 15 is the above-mentioned value. The resistance value of the resistor 11 and the dimensions of the MOS transistors 12 and 15 are set to be approximately the same as the charging capacity of the series circuit including the resistor 12 and the MOS transistor 12 in the first embodiment.
Especially the channel width is set. Similarly, resistors 13 and M
A discharge capacity from the signal output terminal 32 in the series circuit including the OS transistor 14 and a newly provided MOS
The sum of the discharge capability of the signal output terminal 32 by the transistor 16 is the resistance 13 and the MOS in the first embodiment.
The resistance value of the resistor 13 and the dimensions of the MOS transistors 14 and 16, particularly the channel width, are set so as to be almost the same as the discharge capacity of the series circuit including the transistor 14.

FIG. 5 shows a third embodiment of the output circuit according to the present invention, and only the first output drive circuit 10 is shown. Second output drive circuit in this embodiment
Since 20 is also the same as in the case of the first embodiment, its explanation is omitted.

First output drive circuit 10 in this embodiment
Then, a resistance means, for example, a resistor 17 is newly connected between the source of the P-channel MOS transistor 15 in the second embodiment and the power supply voltage Vcc and the N-channel of the N-channel in the second embodiment is connected. MOS transistor
A resistance means, for example, a resistance 18, is newly connected between the source of 16 and the ground voltage Vss. That is, in this embodiment, the resistance and the source of the P-channel MOS transistor are
A plurality of series circuits composed of drains are inserted in parallel between the power supply voltage Vcc and the signal output terminal (shown in FIG. 1),
Two series circuits each including a resistor and a source / drain of an N-channel MOS transistor are inserted in parallel between the ground voltage Vss and the signal output terminal (shown in FIG. 1). In this embodiment, two or more series circuits are inserted in parallel between the power supply voltage Vcc and the signal output terminal and between the ground voltage Vss and the signal output terminal (shown in FIG. 1). You may

Also in the case of this embodiment, the signal output terminal in the series circuit composed of the resistor 12 and the MOS transistor 12
Charging ability for 32, resistor 17 and MOS transistor 15
Of the resistors 11 and 17 so that the sum of the charging capability for the signal output terminal 32 in the series circuit composed of is substantially the same as the charging capability in the series circuit composed of the resistor 12 and the MOS transistor 12 in the first embodiment. Resistance value and MOS
The dimensions of the transistors 12, 15 are set, especially the channel width. Similarly, the sum of the discharging ability from the signal output terminal 32 in the series circuit including the resistor 13 and the MOS transistor 14 and the charging ability for the signal output terminal 32 in the series circuit including the resistor 18 and the MOS transistor 16 is
Resistor 13 and MOS transistor in the first embodiment
The resistance values of the resistors 13 and 18 and the MOS transistors 14 and 16 are set so as to be almost the same as the discharge capacity in the series circuit of 14.
Has been set, especially the channel width.

Here, the result of comparison of the output characteristics of the circuits of the above embodiments will be described. 6A to 6D show output waveforms in a period corresponding to the period a in FIG. 2 when the input signal is changed from the "H" level to the "L" level in each of the circuits of the embodiments. Shown respectively.

(A) is not shown in this embodiment, but is shown as a reference for comparison, and is shown as the first in the first embodiment.
Instead of the output drive circuit 10 of FIG.
This is an example when an inverter is used. In this case, period a
The output waveform rises with a constant slope from time t0 to time t1 corresponding to.

(B) is for the first embodiment,
The output drive circuit 10 of FIG.
This is the case where it is composed of S transistors 12 and 14. In this case, it starts to rise at a constant slope from time t0, and (a)
In the case of, the output waveform reaches a predetermined value at time t1 'which is earlier than time t1.

(C) is of the second embodiment, the first
The output drive circuit 10 of FIG.
This is the case where the S transistors 12, 14, 15, and 16 are used. In this case, it starts to rise at a constant slope from time t0, and after the output signal level reaches Vth (= | VthP |), it continues to rise at a slope different from the initial one, which is faster than t1 ′ in the case of (b). The output waveform reaches a predetermined value at time t1 ″.

(D) is of the third embodiment, and the first
As shown in FIG. 5, the output driving circuit 10 of the resistors 11, 13, 17,
This is the case where it is composed of 18 and MOS transistors 12, 14, 15, and 16. In this case, it starts rising at a constant slope from time t0, and is earlier than time t1 ′ in the case of (b), t
The output waveform reaches a predetermined value at time t1 "'which is later than 1".

[0034]

As described above, according to the present invention, it is possible to provide the output circuit capable of reducing the ringing generated in the output signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a waveform diagram of the first embodiment circuit.

FIG. 3 is a SPICE simulation waveform diagram of the first embodiment circuit.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a third embodiment of the present invention.

FIG. 6 is a waveform chart showing the results of comparing the output characteristics of the circuits of the examples.

FIG. 7 is a conventional circuit diagram.

FIG. 8 is a waveform diagram of a conventional circuit.

[Explanation of symbols]

10 ... First output drive circuit, 11 ... Resistor (first resistance means), 12 ... P-channel MOS transistor, 13 ... Resistor (second resistance means), 14 ... N-channel MOS transistor, 15 ... P Channel MOS transistor, 16 ... N-channel MOS transistor, 17, 18 ... Resistor, 20 ... Second
Output drive circuit, 21, 22 ... P-channel MOS transistors, 23, 24 ... N-channel MOS transistors, 31 ...
Signal input terminal, 32 ... Signal output terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical indication H03K 19/003 Z 8842-5J 19/0948 8321-5J H03K 19/094 B

Claims (5)

[Claims] 1. A signal input terminal and a signal output terminal, a first output drive circuit for generating a signal according to an input signal applied to the signal input terminal and outputting the signal to the signal output terminal, and the signal input. It receives an input signal applied to a terminal and an output signal output from the signal output terminal, and when the output signal changes, a signal corresponding to the input signal is generated during the period until the level reaches a predetermined level. An output circuit comprising a second output drive circuit for outputting to an output terminal. 2. In the second output drive circuit, a current path is serially inserted between a first power supply and the signal output terminal, and the gate is supplied with the input signal and the output signal, respectively. First channel type first and second M
A current channel is inserted in series between the IS transistor, the second power source and the signal output terminal, and the signal signal and the output signal are supplied to the respective gates of the second and third channel types. M
The output circuit according to claim 1, comprising an IS transistor. 3. The first output drive circuit comprises: a first resistance means having one end connected to the first power source; and a second output terminal between the other end of the first resistance means and the signal output terminal. A first channel type fifth MIS transistor having a current path inserted therein and having a gate connected to the signal input terminal; second resistance means having one end connected to the second power supply; A current path is inserted between the other end of the resistance means and the signal output terminal, and the second channel type sixth MIS transistor has a gate connected to the signal input terminal. The output circuit according to claim 1. 4. The first output drive circuit comprises: a first resistance means having one end connected to the first power source; and a second output terminal between the other end of the first resistance means and the signal output terminal. A first channel type fifth MIS transistor having a current path inserted therein and having a gate connected to the signal input terminal; second resistance means having one end connected to the second power supply; A second channel type sixth MIS transistor having a current path inserted between the other end of the resistance means and the signal output terminal and having a gate connected to the signal input terminal; the first power supply and the signal; A first current path is inserted between the output terminal and the gate, and the gate is connected to the signal input terminal.
A channel-type seventh MIS transistor, a second path in which a current path is inserted between the second power source and the signal output terminal, and a gate is connected to the signal input terminal.
The output circuit according to claim 1, comprising an eighth channel type MIS transistor. 5. The first output drive circuit comprises: a first resistance means having one end connected to the first power supply; and a current flowing between the other end of the first resistance means and the signal output terminal. A first channel type fifth MIS transistor having a passage inserted therein and a gate connected to the signal input terminal; a second resistance means having one end connected to the second power supply; and a second resistance means. A current path is inserted between the other end and the signal output terminal, and a plurality of circuits each including a second channel type sixth MIS transistor having a gate connected to the signal input terminal are provided. The output circuit according to claim 1.