JPH0738116A - Laminated type semiconductor substrate - Google Patents

Abstract

PURPOSE:To enhance the withstand voltage of a MOS type field effect transistor and to obtain low ON-resistance by a method wherein, on the side of an insulating film in the main body of a semiconductor substrate or in a semiconductor layer, other insulating film is buried in the state wherein it is brought into contact with the above-mentioned insulating film. CONSTITUTION:After a groove 31 has been formed on a semiconductor substrate main body 1, insulating films 30 and 2a are formed by thermal oxidation, for example. Then, an insulating film 2b, which is thinner than the insulating film 2a, is formed. On the other hand, a semiconductor substrate 3', on which an insulating film 2d is formed, is prepared and a laminated type semiconductor substrate is formed by laminating the insulating film 2b on the substrate 3'. When an MO-type semiconductor device is formed, as the laminated type semiconductor substrate is composed of two insulating films consisting of a relatively thin insulating film 2b and a thick insulating film 2d, a MOS type field effect transistor has high withstand voltage and low ON resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated semiconductor substrate suitable for manufacturing a MOS type semiconductor device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 11, a semiconductor substrate body 1 made of, for example, silicon, an insulating film 2 made of, for example, silicon oxide, and a semiconductor layer 3 made of, for example, silicon are laminated in this order. A stacked semiconductor substrate U having the above structure has been proposed.

According to such a laminated semiconductor substrate U,
Using it, in the semiconductor layer 3 as shown in FIG.
For example, an n-type source region 4, an n-type or p-type drain region 5, and a p-type channel region in contact with the source region 4 side between the source region 4 and the drain region 5 6, channel region 6 and drain region 5
An n-type offset gear extending in contact with them
A source region 8 and a drain electrode layer 9 are formed on the source region 4 and the drain region 5, respectively, and a gate insulating film 10 is formed on the channel region 6. A MOS type semiconductor device forming a MOS type field effect transistor M1 having a structure in which a gate electrode layer 11 is formed can be manufactured, and as shown in FIG. In the semiconductor layer 3 together with such a MOS field effect transistor M1,
an n-type source region 14, an n-type drain region 15,
A channel region 167 is formed between the source region 14 and the drain region 15 so as to be in contact therewith, and the source electrode layer 18 and the drain electrode are formed in the source region 14 and the drain region 15, respectively. Another MOS field effect transistor having a structure in which a layer 19 is provided and a gate electrode layer 21 is formed on the channel region 16 via a gate insulating film 20 is a MOS field effect transistor. A MOS type semiconductor device formed as a MOS type field effect transistor for controlling the transistor M1 can be manufactured.

[0004]

In the case of the conventional laminated semiconductor substrate U shown in FIG. 11, a MOS type semiconductor device having a MOS field effect transistor M1 as shown in FIG. 12 is formed by using the conventional laminated semiconductor substrate U. When manufactured, when the insulating film 2 of the laminated semiconductor substrate U has a relatively thin thickness,
When the withstand voltage of the MOS field effect transistor M1 is low and the MOS field effect transistor M1 has a relatively large thickness, it is necessary to reduce the n-type impurity concentration of the offset region 7 of the MOS field effect transistor. Has a low on-resistance, and therefore it is difficult to manufacture a MOS semiconductor device as shown in FIG. 11 in which the MOS field-effect transistor has a high breakdown voltage and a low on-resistance. Had.

Further, in the case of the conventional laminated semiconductor substrate U shown in FIG. 11, it is used to form a MOS as shown in FIG.
Forming a field effect transistor M1 and M2
When an OS type semiconductor device is manufactured, a stacked semiconductor substrate U
If the insulating film 2 has a relatively large thickness, the withstand voltage of the MOS field effect transistor M1 is high. However, in this case, the thickness of the insulating film 2 is large, so that the thickness of the MOS field effect transistor M1 is large. The length is larger than the length of the gate electrode layer 21 of the MOS field effect transistor M2 for controlling M1, and the short field effect is likely to occur in the MOS field effect transistor M2. Therefore, the MO field effect transistor M2 shown in FIG.
The S-type semiconductor device is replaced with the MOS-type field effect transistor M1.
Has a high breakdown voltage, it is difficult to manufacture the MOS field effect transistor M1 as being capable of being effectively controlled by the MOS field effect transistor M2. .

Therefore, the present invention does not have the above-mentioned drawbacks,
The purpose is to propose a novel laminated semiconductor substrate.

[0007]

A laminated semiconductor substrate according to the present invention has a semiconductor substrate body, an insulating film, and a semiconductor layer which are similar to those of the conventional laminated semiconductor substrate described in FIG. Other than the semiconductor substrate body, the insulating film, and the semiconductor layer, the semiconductor substrate body, the semiconductor layer, or the semiconductor substrate body or the semiconductor layer is embedded so as to be in contact with the insulating film on the insulating film side. It has an insulating film.

[0008]

According to the laminated semiconductor substrate of the present invention, a MOS type semiconductor device as shown in FIG. 12 is manufactured by using the laminated semiconductor substrate as in the case of the conventional laminated semiconductor substrate described above with reference to FIG. It is obvious that the semiconductor integrated circuit as shown in FIG. 13 can be manufactured. However, when the MOS type semiconductor device as shown in FIG. 13 is manufactured,
Since the laminated semiconductor substrate has a configuration including an insulating film having an insulating film portion having a relatively thin thickness of two insulating films and an insulating film portion having a relatively thick thickness, as shown in FIG. The MOS type semiconductor device can be manufactured with the MOS type field effect transistor having a high breakdown voltage and a low ON resistance.

When the MOS type semiconductor device as shown in FIG. 13 is manufactured, the MOS type field effect transistor of the MOS type semiconductor device as shown in FIG. 13 has a high breakdown voltage for the same reason. Further, the MOS field effect transistor can be manufactured so that it can be effectively controlled by another MOS field effect transistor.

[0010]

[Embodiment 1] Next, a first embodiment of a laminated semiconductor substrate according to the present invention will be described with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 11 are designated by the same reference numerals.

The laminated semiconductor substrate according to the present invention shown in FIG. 1 is the same as the conventional laminated semiconductor substrate described above with reference to FIG. 11, in which the other insulating film 30 is insulated in the semiconductor substrate body 1 on the insulating film 2 side. It has a configuration in which it is embedded so as to be in contact with the film 2. Such a laminated semiconductor substrate according to the present invention can be easily manufactured as described below with reference to FIGS.

That is, as shown in FIGS. 2A to 2D, after the groove 31 is formed in the semiconductor substrate body 1, the insulating films 30 and 2a are formed by, for example, heat participation. Forming a thin insulating film 2b, or forming an insulating film 2c and another insulating film 32 made of, for example, silicon nitride on the semiconductor substrate body 1 as shown in FIGS.
Using this as a mask, a groove 31 is formed in the semiconductor substrate body 1, the groove 31 is filled with an insulating film 40, and then the insulating film 32 is formed.
To obtain the same result as in FIG. 1, while FIG.
A semiconductor substrate 3'formed with an insulating film 2d as shown in FIG. 1 is prepared in advance, and as shown in FIG.
The laminated semiconductor substrate is manufactured with a structure in which the structure that has undergone the step of (1) and the semiconductor substrate 3'of FIG. 5 are bonded together and the substrate 3'has a smaller thickness than that.

From the above, the structure of the first embodiment of the laminated semiconductor substrate according to the present invention has been clarified.

According to the laminated semiconductor substrate of the present invention having such a structure, as shown in FIG. 12, a MOS type semiconductor device similar to that described above with reference to FIG.
As shown in FIG. 11, it is obvious that the same MOS type semiconductor device as that described above with reference to FIG. 13 can be manufactured. However, according to the laminated semiconductor substrate of the present invention, it can be used in FIG. It is obvious that the MOS type semiconductor device as shown in FIG. 12 and the semiconductor integrated circuit as shown in FIG. 13 can be manufactured as in the case of the conventional laminated semiconductor substrate described above. When the MOS semiconductor device as shown in FIG. 13 is manufactured, the laminated semiconductor substrate has an insulating film portion having a relatively thin thickness of two insulating films and an insulating film portion having a relatively thick thickness. Since the MOS type semiconductor device as shown in FIG. 12 has a structure having an insulating film, the MOS type field effect transistor has a high breakdown voltage and a low on-resistance. It can be.

Also, when the MOS type semiconductor device as shown in FIG. 13 is manufactured, for the same reason, the MOS type semiconductor device as shown in FIG. Further, the MOS field effect transistor can be manufactured so that it can be effectively controlled by another MOS field effect transistor.

[0017]

Second Embodiment Next, a second embodiment of the laminated semiconductor substrate according to the present invention will be described with reference to FIG.

In the laminated semiconductor substrate according to the present invention shown in FIG. 9, a plurality of insulating films 30 are provided in the semiconductor substrate body 1 as shown in FIG.
The laminated semiconductor substrate according to the present invention has the same structure as that of the laminated semiconductor substrate according to the present invention described above with reference to FIG.

Although detailed description will be omitted also in the case of the laminated semiconductor substrate according to the present invention having such a configuration, the same operational effect as in the case of the laminated semiconductor substrate according to the present invention shown in FIG. 1 can be obtained. it is obvious.

[0020]

Third Embodiment Next, with reference to FIG. 9, a third embodiment of the laminated semiconductor substrate according to the present invention will be described.

In the laminated semiconductor substrate according to the present invention shown in FIG. 9, the insulating film 30 is embedded in the semiconductor substrate body 1, but in the semiconductor layer 3 on the insulating film 2 side. 2 has a structure similar to that of the stacked semiconductor substrate according to the present invention described above with reference to FIG. 1 except that the structure is in contact with 2.

Although detailed description will be omitted also in the case of the laminated semiconductor substrate according to the present invention having such a structure, it is possible to obtain the same operational effect as in the case of the laminated semiconductor substrate according to the present invention shown in FIG. it is obvious.

In the above, only a few examples of the present invention are shown, and without departing from the spirit of the present invention,
Various modifications and changes could be made.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of a laminated semiconductor substrate according to the present invention.

FIG. 2 is a schematic cross-sectional view in a sequential step showing a method for manufacturing the laminated semiconductor substrate according to the present invention shown in FIG.

3A to 3D are schematic cross-sectional views in sequential steps showing a method for manufacturing the laminated semiconductor substrate according to the present invention shown in FIG.

FIG. 4 is a schematic cross-sectional view showing a method of manufacturing the laminated semiconductor substrate according to the present invention shown in FIG. 1, in successive steps following the sequential step of FIG.

5 is a schematic cross-sectional view showing a method of manufacturing the laminated semiconductor substrate according to the present invention shown in FIG.

FIG. 6 is a schematic cross-sectional view showing a method of manufacturing the laminated semiconductor substrate according to the present invention shown in FIG. 1 in a sequential step subsequent to the sequential steps of FIG. 1 or FIGS. 3 and 4 and FIG.

FIG. 7 is a schematic cross-sectional view showing a MOS semiconductor device manufactured by using the laminated semiconductor substrate according to the present invention shown in FIG. 1, for explanation.

FIG. 8 is a schematic cross-sectional view showing another MOS type semiconductor device manufactured by using the laminated semiconductor substrate according to the present invention shown in FIG.

FIG. 9 is a schematic cross-sectional view showing a second embodiment of the laminated semiconductor substrate according to the present invention.

FIG. 10 is a schematic cross-sectional view showing a third embodiment of the laminated semiconductor substrate according to the present invention.

FIG. 11 is a schematic cross-sectional view showing a conventional laminated semiconductor substrate.

12 is a schematic cross-sectional view showing a MOS semiconductor device manufactured by using the conventional laminated semiconductor substrate shown in FIG.

13 is a schematic cross-sectional view showing a MOS type semiconductor device manufactured by using the conventional laminated semiconductor substrate shown in FIG.

[Explanation of symbols] 1 semiconductor substrate body 2 insulating film 3 semiconductor layer 4 source region 5 drain region 6 channel region 7 offset region 8 gate insulating film 9 gate electrode layer 10 gate insulating film 11 gate Gate electrode layer 14 Source region 15 Drain region 16 Channel region 20 Gate insulating film 21 Gate electrode layer M1, M2 MOS type field effect transistor U Stacked semiconductor substrate

Claims (1)

[Claims] 1. A laminated semiconductor substrate having a structure in which a semiconductor substrate body, an insulating film, and a semiconductor layer are laminated in that order, wherein the insulating film side is provided in the semiconductor substrate body or in the semiconductor layer. 2. The laminated semiconductor substrate according to, wherein another insulating film is embedded so as to be in contact with the insulating film.