JPH0737978A - Wiring structure and its manufacture - Google Patents

Abstract

PURPOSE:To improve the problems of integration density, reliability and electrical resistance which are caused by a contact hole through which an upper layer wiring is connected to a contact pattern. CONSTITUTION:A contact hole 23 is formed in an insulating layer 22 formed on a contact pattern 21 and an upper layer wiring (not shown in the figure) is connected to the lower layer contact pattern 21 through the contact hole 23. The contact hole 23 is at least composed of a wide hole part 23a formed on an opening side and a tapered (such as conical or pyramid-shaped) hole part 23b which is formed on a bottom side and whose diameter is gradually linearly reduced toward the bottom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure suitable for application to electronic devices such as semiconductor devices, for example, large integrated circuit devices LSI, VLSI, ULSI, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Semiconductor devices, especially LSI, VLSI, and U
In an integrated circuit IC such as an LSI, an upper layer wiring is an element region such as an impurity-doped region or a lower layer wiring through a connection hole formed through an insulating layer such as a surface insulating layer or an interlayer insulating layer formed on a semiconductor substrate. , A multilayer wiring structure that is electrically contacted with a contacted pattern in a lower layer such as an electrode is adopted. In this structure, the opening diameter of the connection hole is miniaturized as the design rule is reduced.

FIG. 4 shows an example of a conventional process for manufacturing a semiconductor device using a gate array. In this example, as shown in FIG. 4A, for example, a semiconductor element of Si semiconductor substrate 1, in this example, an element having a so-called LOCOS structure by deep selective oxidation in an element isolation region between MOSFET (insulated gate type field effect transistor) forming portions. Forming the isolation insulating layer 2,
An element formation region 3 surrounded by the element isolation insulating layer 2
To form.

A gate insulating layer 4 such as SiO ₂ is formed in the element forming region 3, and a gate electrode 5 made of, for example, polycrystalline Si is formed on the gate insulating layer 4.

Using the gate electrode 5 and element isolation insulating layer 2 as a mask, ion implantation of impurities is performed to form a low impurity concentration source or drain region (hereinafter referred to as S / D region).
6a is formed.

[0006] comprise the sides of the gate electrode 5 entirely deposited an insulating layer such as SiO _2, as shown in Figure B and etched back by then anisotropic etching, the side surface of the gate electrode 5 A sidewall 7 is formed on the gate electrode 5, and the gate electrode 5 including the sidewall 7 and the element isolation insulating layer 2 are used as a mask to perform high-concentration impurity ion implantation to form a high-impurity concentration S / D region 6b. To do. In this manner, the S / D region 6 including both regions 6a and 6b having the low impurity concentration region 6a on the gate side is formed.

As shown in FIG. 1C, an interlayer insulating layer 8 of SiO ₂ or the like is entirely deposited by, for example, a CVD (Chemical Vapor Deposition) method. Contact hole 9 is formed by selective etching by photolithography on a predetermined portion of the contacted pattern in the lower layer for making a selective contact, that is, on the S / D region 6 in the element region in the illustrated example.
To drill.

An underlayer 10 of Ti and TiN is formed in the connection hole 9, a W (tungsten) plug 11 is buried on the underlayer 10, and the underlayer 1 made of Ti and TiON is further formed on the underlayer 10.
2 and the Al-Si wiring layer 13 are formed by sputtering, and the wiring layer 13 and its underlying layer 12 are pattern-etched by photolithography to form an upper wiring 14 which is in ohmic contact with the lower S / D region 6. To do.

In a large-scale integrated circuit or the like using such a gate array, a large number of connecting holes 9 are formed in one cell. The connecting holes 9 are generally vertical with their inner peripheral walls being vertical. It is a hole.

These connection holes 9 are formed by anisotropic etching using photolithography. In this case, the underlying layer is taken into consideration in consideration of errors in pattern exposure and development in forming the openings for the photoresist in the photolithography. It is necessary to consider at least the width of the contact pattern forming portion of the contact pattern. In the example described with reference to FIG. 4, the contact pattern of the lower layer which makes ohmic contact with the upper wiring 14 is S of the element region.
Although the case of the / D region 6 has been described, in order to facilitate understanding, for example, the contact pattern in the lower layer is Al.
Explaining the case of the lower layer wiring 15 such as wiring,
As shown in FIG. 5, for example, the width W _{0 of the} lower layer wiring is 0.5 μ.
In the case of m, at least in the portion where the connection hole 9 is formed, it is 0.25 × 2 μm in comparison with the target width W of the connection hole 9.
Width W ₁ = 0.5 μm + 0.5 μm =
If the distance is 1.0 μm, the distance d between adjacent wirings is 0.5 μm.
If about m is required, the pitch P between the wirings is
The limit is 1.25 μm, which hinders the improvement of the integration density.

This problem is not limited to the case where the contact pattern of the lower layer is the lower layer wiring, but also in the above-mentioned element region, for example, the S / D region, the contact hole 9 is formed thereon.
In order to surely form the film, it is required to form the film with a width that allows for the above-mentioned tolerance.

Therefore, in order to improve the integration density, the width (diameter) of the connection hole is required to be as small as possible. In that case, the reliability of embedding the plug in the connection hole is improved. The problem arises, that is, the electric resistance of the plug itself.

[0013]

SUMMARY OF THE INVENTION According to the present invention, there are problems of integration density, reliability, and electrical resistance due to the connection holes of the upper layer wiring with respect to the contact pattern of the lower layer element region or the lower layer wiring. The present invention provides a wiring structure and a method for manufacturing the same that are intended to solve the problems.

[0014]

As shown in FIG. 1 which is a cross-sectional view of a main part of the present invention, the present invention provides a contact pattern of a lower layer such as an element region, a lower layer wiring, an electrode to which an upper layer wiring is contacted. A connection hole 23 is formed in the insulating layer 22 formed on the wiring 21, and an upper layer wiring (not shown) is brought into contact with the contact pattern 21 in the lower layer through the connection hole 23.

In the first aspect of the present invention, the connection hole 23 has a wide hole 23a formed at least on the opening side.
And a conical or pyramidal conical hole 23b that is formed on the bottom side and gradually narrows toward the bottom surface, that is, the vertical cross-sectional shape has a direct taper.

According to a second aspect of the present invention, in the above structure, the connection hole 23 has a wide hole 23a formed on the opening side,
The wide hole 23a is formed by a vertical wide hole only by the weight hole 23b formed on the bottom side and gradually narrowed linearly toward the bottom surface.

In the third aspect of the present invention, a connection hole 23 is formed in the insulating layer 22 formed on the lower contact pattern 21 to which the upper wiring is contacted, and the lower contact pattern 21 of the lower layer is formed through this connection hole 23. In the method of manufacturing the wiring structure in which the upper layer wiring is in contact with the contact hole 23, the connection hole 23 is formed by dry etching for controlling the plasma generation source and the ion energy directed to the insulating layer 22.
A wide hole 23a at least on the opening side and a conical hole 2 which is gradually narrowed linearly toward the bottom surface on the bottom side.
Drill as 3b.

In the fourth aspect of the present invention, in the dry etching for forming the connection hole 23, the ion energy for forming the conical hole 23b is selected to be smaller than the ion energy for forming the wide hole 23a. To do.

In the fifth aspect of the present invention, a connection hole 23 is formed in the insulating layer 22 formed on the lower contact pattern 21 to which the upper wiring is contacted, and the lower contact pattern 21 of the lower layer is formed through this connection hole 23. In the method of manufacturing the wiring structure in which the upper wiring is contacted with the connection hole 23
In the dry etching for drilling, the generation of reaction products is selected to be larger when the conical hole 23b is drilled than when the wide hole 23a on the opening side is drilled.

[0020]

According to the structure of the present invention, the conical hole 23b is provided on the bottom surface side of the connection hole 23, that is, on the lower contact pattern 21 side.
Since the contact pattern 21 of the lower layer is a lower layer wiring as shown in the schematic cross-sectional view of FIG. Since the bottom portion of the connection hole 23 formed on the lower contact pattern 21 is a narrow hole formed by the conical hole 23b, it is possible to avoid widening the lower layer wiring in the connection hole forming portion. Also here, for example, the width W of the lower wiring of the lower contact pattern 21
_Since the width W can be selected to be approximately the same as ₀ , this width W = W
_{If 0} = 0.5 μm, the pitch P between the wirings is
Can be reduced to 1.0 μm, which is a 20% reduction compared to, for example, 1.25 μm in the case described with reference to FIG.

Further, according to the configuration of the present invention, the connection hole 2 is provided.
The opening side of 3 has a wide hole 23a, and by making the wide hole 23a a vertical hole, the cross-sectional area of the plug or upper layer wiring embedded in this connection hole can be increased, thereby increasing the resistance. Can be effectively suppressed.

Further, in the method of the present invention, since the connection hole 23 according to the present invention is constituted by the wide hole 23a and the conical hole 23b, it is formed by simply selecting the ion energy of dry etching. 23
Can be easily and efficiently drilled.

Incidentally, for example, the opening disclosed in Japanese Laid-Open Patent Publication No. 64-59940 has a plurality of steps, so that the etching is performed twice twice independently, so that the forming process becomes extremely complicated.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a wiring structure and a manufacturing method thereof according to the present invention will be described with reference to FIG. This example is applied to a semiconductor integrated circuit using a gate array, and only one element is shown in FIG. In this example, the lower layer contact pattern 21 for connecting the upper layer wiring
In the S / D region of the MOSFET.

Also in this example, as shown in FIG. 3A,
As described with reference to FIGS. 4A and 4B, for example, in the semiconductor element of the Si semiconductor substrate 1, that is, in this example, the element isolation insulating layer 2 having a so-called LOCOS structure is formed by deep selective oxidation in the element isolation region between the MOSFET formation portions. An element forming region 3 surrounded by the element isolation insulating layer 2 is formed.

A gate insulating layer 4 such as SiO ₂ is formed in the element forming region 3, and a gate electrode 5 made of polycrystalline Si is formed thereon.

Using the gate electrode 5 and the element isolation insulating layer 2 as a mask, ion implantation of impurities is performed to form a source or drain region (S / D region) 6a having a low impurity concentration.

[0028] comprise the sides of the gate electrode 5 entirely deposited an insulating layer of SiO ₂ or the like, and then forming a sidewall 7 on the side surfaces of the gate electrode 5 by performing an etch back by anisotropic etching.

S for forming the side wall 7
The io ₂ insulating layer has a substrate temperature of 420 ° C.
₄ , O ₂ and N ₂ are added at 250 sccm, 250 sccm and 1 respectively
It is supplied at 00 sccm, and the film thickness is 0.1 at a pressure of 13.3 Pa.
It is formed to 25 μm.

The etching back for forming the side wall 7 is performed by using, for example, an etching gas C ₄ F ₈ of 50.
Supply sccm, radio frequency (RF) power 1200W, pressure 2
RIE (Reactive Ion Etching) at Pa.

Using the gate electrode 5 including the side wall 7 and the element isolation insulating layer 2 as a mask, impurity ion implantation is carried out at a high concentration to form a high impurity concentration S / D region 6b.
To form. This ion implantation is performed in the formation of an n-type S / D region with an implantation energy of As ions of 20 keV with a dose of 5 × 10 ¹⁵ cm ⁻² , and in the formation of a p-type S / D region. , BF _{2 20} ke
It can be performed with a dose amount of 3 × 10 ¹⁵ cm ⁻² with an implantation energy of V ² .

In this way, the S / D region 6 including both regions 6a and 6b having the low impurity concentration region 6a on the gate side is formed.

Then, as shown in FIG. 3B, an insulating layer 22 in which a SiO ₂ layer and boron phosphorus silicate glass (BPSG) are laminated, in this example, an interlayer insulating layer is formed. The SiO ₂ layer of the insulating layer 22 has a substrate temperature of 720 ° C., for example, and TEOS (tetra ethyl ortho silicate).
Is supplied at 50 sccm and the film thickness is 500 with pressure of 40 Pa.
nm. Then, on this, for example, the substrate temperature 4
At 00 ° C., SiH ₄ , PH ₃ , B ₂ H ₆ , O ₂ and N ₂ were added at 80 sccm, 7 sccm, 7 sccm, 1000 sccm and 3 respectively.
The film is supplied at 2000 sccm, and BPSG is formed by CVD at a pressure of 10132 Pa.

Next, as shown in FIG. 3C, this insulating layer 2
2 is provided with a connection hole 23. The connection hole 23 is provided in the lower layer contact pattern 21 for connecting an upper layer wiring described later.
Are formed on the S / D region 6 as.

The connection hole 23 can be formed in an opening pattern of various shapes such as a circular pattern, a square shape such as a square or a rectangle, and a wide hole 23a on the opening side and a pyramid shape on the bottom side in the depth direction. The shape has a hole 23b.

After that, S / for making good ohmic contact with the surface of the semiconductor substrate through the connection hole 23.
Ion implantation of impurities of the same conductivity type as the D region 6 is performed. In this ion implantation, for example, in the case of n type, 20 As ions are added.
5 × 10 ¹⁵ cm with a driving energy of keV
The dose amount is ⁻² , and the p-type S / D region is formed with a dose amount of 3 × 10 ¹⁵ cm ⁻² with BF ₂ implantation energy of 20 keV. Then 11
Annealing is performed at 00 ° C. for 10 seconds.

As shown in FIG. 3D, the underlayer 10 is formed in the connection hole 23. The underlayer 10 includes, for example, a magnetron sputtered Ti film, which makes good ohmic contact with the S / D region 6, and a TiN film, which serves as an adhesion layer for obtaining adhesion with a W plug layer, which will be described later. A laminated structure formed by the device can be used.

For sputtering Ti, for example, a power of 4 is used.
kW, the substrate temperature is 150 ° C., Ar gas is flown at 100 sccm, and the pressure is 0.47 Pa to form a film having a thickness of, for example, 70 nm. For TiN sputtering, for example, a substrate temperature of 1
Ar and N ₂ are flown at 50 ° C. at 40 sccm and 70 sccm, respectively, and the pressure is 4.6 Pa to form a film thickness of 50 nm.

A W plug 11 is embedded on the underlayer 10. The W plug 11 can be formed by forming W on the entire surface by CVD and etching back by anisotropic etching. In this W CVD, for example, the substrate temperature is 450 ° C., and WF ₆ and H ₂ are 40 sccm each.
And 70 sccm, pressure is 10640 Pa and film thickness is 400
nm film is formed. Then, for example, an etching gas SF ₆ is supplied to the W film at 50 sccm, and R of microwave power 850 W, RF power 150 W, and pressure 1.33 Pa is applied.
IE is performed to leave W in the connection hole 23 and remove the other portion by etching.

After that, an underlayer 12 and an Al--Si (1%) wiring layer 13 having a laminated structure of Ti, TiON, and Ti are sequentially formed over the entire surface by, for example, a magnetron sputtering apparatus.

The sputtering of each Ti film can be performed under the same conditions as the formation of the Ti film in the underlayer 10 described above, and the film thickness is formed to 70 nm, for example. Moreover, the sputtering of the TiON film is performed, for example, at a substrate temperature of
At 50 ° C., Ar and N ₂ -6% O ₂ are added at 40 sccm and 70, respectively.
Flowing at sccm, power 5 kW, pressure 0.47 Pa to form a film thickness of 70 nm.

Further, the sputtering of the Al-Si (1%) wiring layer 13 is carried out, for example, at a substrate temperature of 150 ° C. and Ar of 40.
Flowing at sccm, power 22.5 kW, pressure 0.47 Pa to form a film thickness of 500 nm.

Then, the wiring layer 13 and its underlying layer 12
Pattern etching by photolithography,
The upper wiring 14 which is ohmic-contacted with the S / D region 6 of the lower contact pattern 21 is formed.

This pattern etching is selective etching by photolithography, for example, etching gas B.
Cl ₃ and Cl ₂ are supplied at 60 sccm and 90 sccm respectively, microwave power 1000 W, RF power 50 W,
Performed by RIE at a pressure of 0.016 Pa.

In this manner, the upper wiring 14 is ohmic-contacted with the predetermined portion of the contacted pattern 21 in the lower layer, which is the S / D region 6 in this example, through the connection hole 23.

In the above-described wiring structure and the manufacturing method thereof, the wide hole 23a of the connection hole 23 is a vertical hole, that is, the inner peripheral wall thereof is a surface substantially perpendicular to the surface of the contacted pattern 21 in the lower layer. And this vertical wide hole 2
A cone-shaped hole 23b having a conical shape, a pyramid shape, or the like is formed continuously from the edge portion on the bottom side of 3a, that is, the lower edge without generating a step.

In the method 1 of the present invention, the connection hole 2
3 is formed, a wide hole 23a and a conical hole 23b are formed and formed by dry etching that controls the plasma generation source and the ion energy toward the insulating layer 22.

In the dry etching for forming the connection hole 23, the ion energy for forming the conical hole 23b is selected to be small compared to the ion energy for forming the wide hole 23a.

That is, the connection hole 23 is dry-etched, in particular, the ion energy can be controlled, for example, EC.
It is formed by an R (electron cyclotron resonance) type etching device and a helicon type plasma etching device.

An example of the method of the present invention will be described.

Example 1 The first ECR device continuously
Then, the second etching is performed to form the connection hole 23.
By the first etching, the depth Da shown in FIG. 1 is formed, that is, the vertical wide hole 23a is formed, and then the second etching is performed and the remaining depth Db is formed to form the conical hole 23b. I do. The depth Da is Da ≧ (1/2), where D is the total depth of the connection hole 23.
Let be D. The first and second etchings are performed only by changing the etching conditions in the chamber of the same ECR apparatus under the following conditions. First etching condition: Gas system and its flow rate C ₄ F ₈ 30 sccm RF power 6.0 W / cm ² Microwave power 400 W Pressure 0.25 Pa Second etching condition: Gas system and its flow rate C ₄ F ₈ 30 sccm RF power 4.0 W / cm ² microwave power 400 W pressure 0.25 Pa

According to this etching, the inner wall surface is vertically etched in the first etching, and the RF power is changed in the second etching to reduce the ion implantation energy of the vertically incident component, thereby increasing the etching rate. The etching is performed so that the cross-section that narrows toward the bottom has a linear taper.

In another method of the present invention, when the connection hole 23 having the above-mentioned wide hole 23a and the conical hole 23b is bored, the reaction product is generated in the dry etching by the wide hole 23a on the opening side. It is made larger when the conical hole 23b is drilled than when drilled. Specifically, since the formation of the connection hole 23 is performed by photolithography as described above, the decomposition by-product of the photoresist used as an etching resist at this time has a cone shape larger than that at the time of forming the wide hole 23a. The hole 23b is made large at the time of drilling.

Next, an example of the case of the method of the present invention will be described as a second embodiment. Example 2 In this case as well, the ECR apparatus continuously performs the first and second etchings to form the connection hole 23. That is, the first etching is performed to the depth Da shown in FIG. 1, that is, the vertical wide hole 23a is formed, and then the second etching is performed.
Etching is performed to etch the remaining depth Db to form the conical hole 23b. The depth Da is the connection hole 23.
Let D be the total depth of, then Da ≧ (1/2) D. The same EC is used for the first and second etching under the following conditions.
It is performed only by changing the etching conditions in the chamber of the R apparatus. First etching condition: Gas system and its flow rate C ₄ F ₈ 30 sccm RF power 6.0 W / cm ² Microwave power 400 W Pressure 0.25 Pa Second etching condition: Gas system and its flow rate C ₄ F ₈ 30 sccm CH ₂ F ₂ 50sccm RF power 6.0W / cm ² Microwave power 400W Pressure 0.25Pa

According to this etching, the inner wall surface is vertically etched by the first etching, and the cross section narrowing toward the bottom has a linear taper by the second etching. This is because the gas containing hydrogen atoms was mixed in the second etching.
By using the extraction reaction of the F atom that becomes the Si etchant of iO ₂ and making carbon that is a reaction product excessive, the shape of the connection hole 23 is tapered, that is, a taper that becomes narrower on the bottom side is generated.

That is, in the first etching reaction system, C ₄ F ₈ → 4C + 8, F + Si → SiF ↑, C + O ₂ → CO ₂ ↑ SiO ₂ are decomposed by the reaction with F.

On the other hand, in the second etching reaction system, F is combined with hydrogen by the presence of hydrogen, and H + F
→ The reaction of HF ↑ causes the amount of decomposition of SiO ₂ to decrease, and at the same time, the amount of supply of oxygen, which is a decomposition component with SiO ₂ , decreases, so that carbon C does not volatilize and adheres to the side wall of the etching hole. Then, by functioning as a protective film for etching, the tapered conical hole 23b is formed. In this way, also according to the second embodiment, the connection hole 23 in the structure of the present invention can be formed.

In the above example, the contact pattern 2 is applied to an integrated circuit having a MOSFET as a circuit element.
1 is the S / D region 6 of the element region, but the present invention is not limited to the above-described example, and can be applied to various semiconductor devices, and the contacted pattern is limited to the case of the element region. Instead, it can be applied to the case of lower layer wiring, electrodes, etc., and various changes can be made.

[0059]

According to the structure of the present invention, since the bottom surface side of the connection hole 23, that is, the lower contacted pattern 21 side is formed by the conical hole 23b to be narrower than the opening side, for example, the lower layer Since it is not necessary to consider or reduce the margin for alignment with the contacted pattern 21, it is possible to increase the density of the pattern and thus the integration density.

Further, according to the structure of the present invention, the connection hole 2 is provided.
The opening side of 3 has a wide hole 23a, and by making the wide hole 23a a vertical hole, the cross-sectional area of the plug or upper layer wiring embedded in this connection hole can be increased, thereby increasing the resistance. Can be effectively suppressed.

Further, in the method of the present invention, since the connection hole 23 according to the present invention is constituted by the wide hole 23a and the conical hole 23b, the reaction product is simply formed by dry etching, for example, by controlling ion energy and gas. The connection hole 23 can be easily and efficiently formed.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a connection hole of an example of a structure of the present invention.

FIG. 2 is a schematic plan view of an example of the structure of the present invention.

FIG. 3 is a manufacturing process diagram of an example of the method of the present invention.

FIG. 4 is a manufacturing process diagram of a conventional method.

FIG. 5 is a schematic plan view of a conventional structure.

[Explanation of symbols]

 21 Contact Pattern 22 Insulating Layer 23 Connection Hole 23a Wide Hole 23b Conical Hole

Claims (5)

[Claims] 1. A wiring in which a connection hole is formed in an insulating layer formed on a lower contact pattern to be contacted with an upper wiring, and the upper wiring is brought into contact with the lower contact pattern through the connection hole. It has a structure, and the connection hole comprises at least a wide hole formed on the opening side and a conical hole formed on the bottom side and gradually narrowed linearly toward the bottom surface. Wiring structure. 2. The connecting hole comprises only a wide hole formed on the opening side and a conical hole formed on the bottom side and gradually narrowed linearly toward the bottom surface. The wiring structure according to claim 1, wherein the wiring structure comprises a vertical wide hole. 3. A wiring in which a connection hole is formed in an insulating layer formed on a lower-layer contacted pattern with which the upper-layer wiring is contacted, and the upper-layer wiring is contacted with the lower-layer contacted pattern through the connection hole. In the method of manufacturing a structure, the connection hole is made wider at least on the opening side and gradually narrowed linearly toward the bottom surface on the bottom side by dry etching for controlling the plasma generation source and the ion energy directed to the insulating layer. A method for manufacturing a wiring structure, characterized in that the wiring structure is formed as a conical hole. 4. The dry etching for forming the connection hole is characterized in that the ion energy at the time of forming the conical hole is selected to be smaller than the ion energy at the time of forming the wide hole. The method for manufacturing the wiring structure according to claim 3. 5. A wiring in which a connection hole is formed in an insulating layer formed on a lower contact pattern to be contacted with the upper wiring, and the upper wiring is brought into contact with the lower contact pattern through the connection hole. In the method of manufacturing a structure, the generation of a reaction product in dry etching for forming the connection hole is larger when the conical hole is formed than when the wide hole on the opening side is formed. The method for manufacturing a wiring structure according to claim 3.