CN112864116A

CN112864116A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN112864116A
Application number: CN201911182387.6A
Authority: CN
Inventors: 李书铭; 刘嘉鸿; 欧阳自明
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-11-27
Filing date: 2019-11-27
Publication date: 2021-05-28

Abstract

The embodiment of the invention provides a semiconductor element and a manufacturing method thereof. The semiconductor device includes a substrate having a plurality of active regions, at least one dielectric layer formed on the substrate, and a plurality of contact windows in the dielectric layer and connected to the active regions. The contact is a barrel-shaped structure (barrel-shaped structure) having a middle section (middle section), a top section (head section) having a smaller circumference than the middle section, and a bottom section (end section) having a smaller circumference than the middle section.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to semiconductor technology, and more particularly, to a semiconductor device having a contact with a specific structure and a method for fabricating the same.

Background

With the scaling of the new semiconductor process, the size of each component of the semiconductor device is relatively reduced, such as the contact windows of the semiconductor device are not only reduced, but also the distance between the contact windows is reduced. Therefore, in order to break through the limitation of the light source resolution in the photolithography process, a Self Alignment Double Patterning (SADP) process is currently used to achieve the reduction of the contact window.

However, in either the conventional photolithography and etching process or the self-aligned double patterning process, the contact area between the contact window and the substrate or other members may be reduced due to the alignment error caused by the initial photolithography process, thereby affecting the device performance.

Disclosure of Invention

The invention provides a semiconductor device and a method for manufacturing the same, which has a contact window with a specific structure and can increase the contact area between the contact window and an active region and thereby improve the electrical property of the device.

The semiconductor element comprises a substrate with a plurality of active regions, at least one dielectric layer and a plurality of contact windows. The dielectric layer is formed on the substrate, and the contact window is positioned in the dielectric layer and connected to the active region. Each contact is a barrel-shaped structure having a middle section (middle section), a top section (head section) having a smaller circumference than the middle section, and a bottom section (end section) having a smaller circumference than the middle section.

Another method for manufacturing a semiconductor device of the present invention includes defining a plurality of active regions in a substrate, forming at least one dielectric layer on the substrate, and forming a plurality of openings in the dielectric layer to expose the active regions. And introducing the first oxygen plasma and the first fluorine plasma to remove by-products in the opening and oxidize the inner surface of the opening. And introducing a second oxygen plasma and a second fluorine plasma to remove the oxidized inner surface to enlarge the opening and repair the active region. Introducing third oxygen plasma to oxidize the inner surface of the enlarged opening to form an oxide layer. And then removing the oxide layer to form a plurality of contact holes, wherein the cross-sectional structure of two adjacent contact holes comprises a stud head (Capital), a stud Base (Base) and a stud shaft (flush) between the stud head and the stud Base, and the width of the stud shaft is smaller than that of the stud Base, and the width of the stud shaft is also smaller than that of the stud head. Depositing conductor material on the substrate and filling the contact hole, and then flattening the conductor material to form a plurality of contact windows in the contact hole.

Based on the above, the method of the present invention can form a plurality of contacts having a specific structure, each contact is slightly barrel-shaped, and the distance between two adjacent contacts is closer than the distance between contacts formed by the general photolithography etching process or the self-aligned double patterning process, which means that the contact area between each contact and the substrate is larger, thereby improving the electrical property of the device. Moreover, even if the contact window and the active area have slight alignment difference, the electrical connection is not affected.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the invention;

FIG. 2A is a schematic cross-sectional view taken along line I-I of FIG. 1;

FIG. 2B is a schematic cross-sectional view taken along line II-II of FIG. 1;

fig. 3A to fig. 3G are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the invention.

Description of the reference numerals

100: substrate

102: active region

104. 130, 130: dielectric layer

106: contact window

108: middle section part

108 a: location of a body part

110: top part

112: bottom part

114: stepped profile

114 a: step bottom

114 b: side wall

116: isolation structure

118: embedded word line

120: bit line

122. 126: cover layer

124: spacer wall

128: insulating layer

300: protective layer

302: opening of the container

302 a: inner face

304: oxide layer

306: contact hole

308: column cap

310: column base

312: column body

d1, d 2: pore diameter

D1: a first direction

D2: second direction

D3: third direction

w1, w2, w3, w4, w 5: width of

Detailed Description

The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. Furthermore, "first," "second," "third," etc. are used herein to describe various regions, layers and/or regions of a process or structure at various stages, wherein sequential meanings are possible in terms of process, but such terms are used only to distinguish one region, layer or region from another region, layer or region in a structure. Relative dimensions and positioning of layers, regions and/or features may be exaggerated or minimized for clarity. In addition, the same or similar reference numerals denote the same or similar elements, and the following paragraphs will not be repeated.

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the invention, with parts of the components, such as a dielectric layer, omitted for clarity. Fig. 2A is a schematic cross-sectional view taken along line I-I of fig. 1. Fig. 2B is a schematic cross-sectional view taken along line II-II of fig. 1.

Referring to fig. 1 and 2A, a semiconductor device 10 of the present embodiment includes a substrate 100 having a plurality of active regions 102, at least one dielectric layer 104, and a plurality of contacts 106. The dielectric layer 104 is formed on the substrate 100, the contact hole 106 is located in the dielectric layer 104 and connected to the active region 102, and a capacitor structure (not shown) is subsequently formed over the contact hole 106 and connected thereto. Each contact 106 is a barrel structure having a middle section 108, a top section 110, and a bottom section 112, and the bottom section 112 may be in direct contact with the active region 102, wherein the top section 110 has a smaller circumference than the middle section 108, the bottom section 112 has a smaller circumference than the middle section 108, and the top section 110 may have a circumference greater than or equal to the bottom section 112. The term "circumference" as used herein generally refers to the circumference of the widest region. In addition, a portion 108a of the middle section 108 near the top 110 may have a width that tapers toward the top 110. For example, the width reduction ratio of the portion 108a of the middle section 108 near the top 110 (i.e., the difference between the width w1 of the middle section 108 and the width w2 of the portion 108a divided by the width w1 of the middle section 108) is about 10% to 25%, preferably about 12% to 16%. Moreover, the middle section 108 of the present embodiment may have a step-shaped cross section 114 at a position close to the bottom 112, wherein the step-shaped cross section 114 includes a bottom 114a and a sidewall 114b, and the sidewall 114b connects the bottom 114a and the bottom 112 of the barrel structure 108. In some embodiments, the maximum width w3 of the stepped profile 114 is less than 2.5 times, and preferably less than 1.66 times, the width w2 of the top portion 110. In some embodiments, the material of the contact window 106 is, for example, doped or undoped polysilicon, titanium nitride, tungsten, the like, or a combination thereof.

Next, referring to fig. 1, fig. 2A and fig. 2B, in an embodiment of the memory device, the semiconductor device 10 may further include an isolation structure 116 defining an active region 102 in the substrate 100, a plurality of buried word lines 118 extending along the first direction D1 and arranged along the third direction D3, and a plurality of bit lines 120 extending along the third direction D3 and arranged along the first direction D1. The isolation structure 116 may be a Shallow Trench Isolation (STI) or a Deep Trench Isolation (DTI). And the first direction D1 is staggered from the third direction D3. For example, the first direction D1 may be substantially orthogonal to the third direction D3. On the other hand, the active region 102 extends in the second direction D2. The second direction D2 is staggered from the first direction D1 and the third direction D3. In one embodiment, the second direction D2 and the third direction D3 form an angle of 30 ° to 45 °.

In fig. 2A, the buried word line 118 penetrates through a portion of the isolation structure 116 and a cap layer (cover layer)122 is disposed on top of the buried word line 118 for blocking the buried word line 118 from the structure above the buried word line. In addition, a gate dielectric layer (not shown) may be disposed between the buried word line 118 and the isolation structure 116. The material of the buried word line 118 is, for example, doped or undoped polysilicon, tungsten, the like, or a combination thereof.

In fig. 2B, the contact 106 is located between two bit lines 120, and the sidewalls of the bit lines 120 are formed with spacers 124 and the tops of the bit lines 120 are formed with caps 126, which are used to protect the bit lines 120 and isolate the contact 106, and the side surfaces of the contact 106 are not shown in fig. 2A because the adjacent bit lines 120 have a small pitch; however, if the pitch of the adjacent bit lines 120 is large enough, the side surfaces of the contact windows 106 also have a width that tapers toward the top as shown in fig. 2A. In addition, film layers such as an insulating layer 128 and a dielectric layer 130 may be disposed between the substrate 100 and the bit line 120, but the invention is not limited thereto. The material of the bit line 120 is, for example, doped or undoped polysilicon, tungsten, the like, or combinations thereof.

In some embodiments, the substrate 100 may be a semiconductor substrate or a Semiconductor On Insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or the SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. The elemental semiconductor may comprise Si or Ge, for example. The alloy semiconductor may include SiGe, SiC, SiGeC, and the like. The compound semiconductor may comprise a group III-V semiconductor material or a group II-VI semiconductor material. In some embodiments, the substrate 100 may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be N-type and the second conductivity type can be P-type. In some embodiments, the material of the isolation structure 116 in the substrate 100 is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof.

The dielectric layer 104 on the substrate 100 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof. In some embodiments, the dielectric layer 104 may be a single layer, and the material of the single layer may include silicon oxide or other low-k dielectric material (e.g., dielectric material with a dielectric constant lower than 4). In alternative embodiments, the dielectric layer 104 may be a multi-layer structure, such as a multi-layer structure composed of silicon oxide, silicon nitride, or other dielectric materials. Furthermore, in other embodiments, the dielectric layer 104 may have an air gap (air gap) therein.

Fig. 3A to 3G are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, wherein the same reference numerals as in the previous embodiment are used to represent the same or similar components, and some technical descriptions, such as positions, sizes, materials, and the like of various layers or regions, can refer to the content of the previous embodiment, and thus are not repeated herein.

Referring to fig. 3A, a plurality of active regions 102 are defined in a substrate 100, such as an isolation structure 116 formed in the substrate 100 to define the active regions 102. For example, in the case of a memory device, the formation of the embedded word lines 118 may be continued, and a protection layer 300 may be formed on the substrate 100 to protect the surface of the substrate 100 from the etching process performed in the previous process for forming the isolation structures 116 and to serve as a stop layer for the subsequent etching process. Next, at least one dielectric layer 104 is formed on the substrate 100, and a plurality of openings 302 are formed in the dielectric layer 104. In one embodiment, each opening 302 has substantially the same aperture. The opening 302 may be formed by a photolithography process or a self-aligned dual patterning (SADP) process.

Next, referring to fig. 3B, the protection layer 300 on the surface of the substrate 100 is removed to expose the active region 102, and the protection layer 300 is removed by, for example, wet etching or dry etching. If the passivation layer 300 is not provided or if the passivation layer 300 has been removed in the previous step, this step is not required.

Then, referring to fig. 3C, if the dielectric layer 104 is silicon nitride, the first oxygen plasma and the first fluorine plasma are introduced to remove the by-products in the opening 302 and oxidize the inner surface 302a of the opening 302. In some embodiments, the first oxygen plasma generating gas comprises oxygen at a flow rate of 1000sccm to 3000sccm and the first fluorine plasma generating gas comprises oxygen at a flow rate of 10sccm to 50sccmsccm of CF₄Gas, the process pressure is 10 mT-1000 mT and the power is 500W-2000W.

Subsequently, referring to fig. 3D, a second oxygen plasma and a second fluorine plasma are introduced to remove the oxidized inner surface (302 a of fig. 3C) and expand the opening 302 while repairing the active region 102, wherein the gas flow rate for generating the second fluorine plasma may be greater than the gas flow rate for generating the first fluorine plasma. In some embodiments, the gas generating the second oxygen plasma comprises oxygen gas at a flow rate of 1000sccm to 3000sccm and the gas generating the second fluorine plasma comprises CF at a flow rate of 50sccm to 200sccm₄Gas, the process pressure is 10 mT-1000 mT and the power is 500W-2000W.

Then, referring to fig. 3E, a third plasma is introduced to oxidize the inner surface of the enlarged opening 302 to form an oxide layer 304. In some embodiments, the third oxygen plasma generating gas comprises oxygen at a flow rate of 50sccm to 3000sccm, a process pressure of 10mT to 1000mT, and a power of 500W to 2000W.

The conditions of the first oxygen plasma and the first fluorine plasma, the second oxygen plasma and the second fluorine plasma, and the third oxygen plasma are not limited to the embodiments of the present invention, for example, other gases such as NF can be selected as the gas for generating the second fluorine plasma₃、CH₂F₂And the like. In principle, if the same gas is used, the flow rate of the gas generating the first oxygen plasma is close to or substantially equal to the flow rate of the gas generating the second oxygen plasma, and the flow rate of the gas generating the second fluorine plasma is greater than the flow rate of the gas generating the first fluorine plasma.

Then, referring to fig. 3F, the oxide layer (304 of fig. 3E) is removed to form a plurality of contact holes 306, and the oxide layer is removed by a method such as wet etching. The cross-sectional structure of two adjacent contact windows 306 includes a stud head (Capital)308, a stud Base (Base)310 and a stud shaft (craft) 312 between the stud head 308 and the stud Base 310, and the width w4 of the stud shaft 312 is smaller than the width w5 of the stud Base 310, and the width w4 of the stud shaft 312 is also smaller than the width w6 of the stud head 308. In some embodiments, the aperture d2 of each contact hole 306 is, for example, 1.05 times to 2 times (i.e., 1+ [ (d2-d1)/d1]) the aperture of each opening (d 1 of fig. 3B). The term "pore size" as used herein generally refers to the pore size at the widest point. Furthermore, each contact hole 306 has a stepped profile 114 between the pillar base 310 and the pillar body 312, wherein the sidewall 114b of the stepped profile 114 may be a tapered sidewall due to the wet process described above. Since the contact hole 306 is larger than the opening formed by the photolithography process or the self-aligned double patterning process, even if there is a slight alignment error in the foregoing processes, the contact area between the subsequently formed contact and the active region 102 is not affected.

Next, referring to fig. 3G, a conductive material is deposited on the substrate 100 and fills the contact holes 306, and then the conductive material is planarized to form a plurality of contacts 106 in the contact holes 306. In some embodiments, the conductor material comprises doped or undoped polysilicon, titanium nitride, tungsten, the like, or combinations thereof. And planarizing the conductive material by, for example, Chemical Mechanical Polishing (CMP).

In summary, the present invention utilizes a series of specific processes to break through the limitations of the current process and form the contact window with the barrel structure, thereby increasing the contact area between the contact window and the active region and further improving the electrical characteristics of the device.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A semiconductor element, comprising:

a substrate having a plurality of active regions;

at least one dielectric layer formed on the substrate; and

a plurality of contact windows in the dielectric layer and connected to the plurality of active regions, wherein each contact window is a barrel structure having a middle section, a top portion and a bottom portion, wherein the top portion has a circumference smaller than a circumference of the middle section, and the bottom portion has a circumference smaller than the circumference of the middle section.

2. The semiconductor device as claimed in claim 1, wherein a portion of the middle section near the top portion has a width tapered toward the top portion.

3. The semiconductor device according to claim 2, wherein a width reduction ratio of the portion of the middle section near the top portion is between 10% and 25%.

4. The semiconductor device as claimed in claim 1, wherein a portion of the middle section near the bottom has a step-shaped cross section.

5. The semiconductor element according to claim 1, wherein a circumference of the top portion is greater than or equal to a circumference of the bottom portion.

6. The semiconductor device of claim 4, wherein the stepped profile comprises a step bottom and sidewalls connecting the step bottom and the bottom of the barrel structure.

7. The semiconductor component of claim 6, wherein the sidewalls of the stepped profile are tapered sidewalls.

8. A method of manufacturing a semiconductor element, the method comprising:

defining a plurality of active regions in a substrate;

forming at least one dielectric layer on the substrate;

forming a plurality of openings in the at least one dielectric layer and exposing the plurality of active regions;

introducing a first oxygen plasma and a first fluorine plasma to remove by-products in the plurality of openings and oxidize inner surfaces of the plurality of openings;

introducing second oxygen plasma and second fluorine plasma to remove the oxidized inner surface to expand the plurality of openings and repair the active region;

introducing third oxygen plasma to oxidize the inner surfaces of the plurality of enlarged openings to form an oxide layer;

removing the oxide layer to form a plurality of contact holes, wherein the cross-sectional structure of two adjacent contact holes comprises a column head, a column seat and a column shaft between the column head and the column seat, and the width of the column shaft is smaller than the width of the column seat and smaller than the width of the column head;

depositing a conductor material on the substrate and filling the plurality of contact holes; and

and flattening the conductor material to form a plurality of contact windows in the plurality of contact window holes.

9. The method as claimed in claim 8, wherein an aperture diameter of each of the contact holes is 1.05 times to 2 times larger than the aperture diameter of each of the openings.

10. The method for manufacturing a semiconductor element, according to claim 8, wherein a gas flow rate at which the second fluorine plasma is generated is larger than a gas flow rate at which the first fluorine plasma is generated.

11. The method as claimed in claim 8, wherein each of the contact holes has a step-shaped cross section between the pillar base and the pillar body.