JPH0736615B2 - Photoelectric conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention controls the potential of a control electrode region of a semiconductor transistor via a capacitor to accumulate a carrier excited by light in the control electrode region, The present invention relates to a photoelectric conversion device of a type in which the output of a semiconductor transistor is controlled by this accumulated voltage.

[Prior art]

FIG. 6 (A) shows Japanese Patent Application Laid-Open No. 60-12759 to Japanese Patent Application Laid-Open No. 60-127.
6 is a plan view of the photoelectric conversion device disclosed in Japanese Patent Publication No. 65
FIG. 6B is a sectional view taken along the line I-I, and FIG. 6C is an equivalent circuit diagram thereof.

In each figure, photoelectric conversion cells are formed and arranged on an n-silicon substrate 101, and each photoelectric conversion cell is composed of SiO ₂ , Si.
It is electrically insulated from an adjacent photoelectric conversion cell by an element isolation region 102 made of ₃ N ₄ or polysilicon.

Each photoelectric conversion cell has the following configuration. N-region 103 having a low impurity concentration formed by an epitaxial technique or the like
The p region is formed by doping p-type impurities on the top.
104 is formed, and an n ⁺ region 105 is formed in the p region 104 by an impurity diffusion technique or an ion implantation technique. p
Region 104 and n ⁺ region 105 respectively form the base and the emitter of the bipolar transistor.

An oxide film is formed on the n ⁻ region 103 in which each region is formed in this manner.
106 is formed, and a capacitor electrode 107 having a predetermined area is formed on the oxide film 106. The capacitor electrode 107 faces the p region 104 with the oxide film 106 interposed therebetween, and the capacitor C ₀ x
To form. By applying the pulse voltage of the capacitor electrode 107, the potential of the p region 104 in the floating state is controlled.

In addition, the emitter electrode 108 connected to the n ⁺ region 105,
A wiring 109 for reading a signal from the emitter electrode 108 to the outside, a wiring 110 connected to the capacitor electrode 107, an n ⁺ region 111 having a high impurity concentration on the back surface of the substrate 101, and an electrode 112 for applying a potential to the collector of the bipolar transistor. Are formed respectively.

Next, the basic operation will be described. First, it is assumed that the p region 104, which is the base of the bipolar transistor, is in a negative potential initial state. The light 113 of the p region 104 enters, and carriers corresponding to the amount of light are accumulated in the p region 104 (accumulation operation). The base potential changes due to the accumulated charges, and the current between the emitter and the collector is controlled by the potential change, and the electrical signal corresponding to the incident light amount is read from the floating emitter electrode 108 (reading operation). Also, p region
In order to remove the carrier accumulated in 104, the emitter electrode 108 is grounded and the positive voltage pulse for refresh is applied to the capacitor electrode 107. By applying this positive voltage, p
Region 104 is forward biased with respect to n ⁺ region 105,
Accumulated carriers are removed. When the refresh pulse falls, the p region 104 returns to the initial state of negative potential (reflecting operation). Thereafter, the above-mentioned operations of accumulating, reading, and refreshing are repeated.

In short, the method proposed here accumulates carriers generated by light incidence in the p region 104 which is the base, and controls the current flowing between the emitter electrode 108 and the collector electrode 112 by the accumulated charge amount. It is a thing. Therefore, the accumulated carriers are read after being subjected to charge amplification by the amplification function of each cell, and high output, high sensitivity, and low noise can be achieved.

In addition, the potential Vp generated in the base by the carrier accumulated in the base by photoexcitation is given by Q / C. Here, Q is the charge amount of the carrier accumulated in the base, and C is the capacity connected to the base. As is clear from this equation, in the case of high integration, the cell size decreases and Q
It means that both C and C become small, and the potential Vp generated by photoexcitation is kept almost constant. Therefore, it can be said that the method proposed here is advantageous for future high resolution.

Next, FIG. 7 shows a circuit configuration diagram of a conventional photoelectric conversion device in which the basic photosensor cell structure is two-dimensionally arranged in 3 × 3.

Basic optical sensor cell 130 surrounded by the dotted line described above
(The collector of each bipolar transistor is connected to the substrate and substrate electrode). Horizontal lines 131, 131 ', 13 for applying read-out and refresh pulses
1 ″, vertical shift register 132 for generating read pulse, vertical shift register 132 and horizontal lines 131, 13
Buffer MOS transistor 133,133 ', 13 between 1', 131 "
3 ″, a terminal 134 for applying a pulse φ _R to the gates of the buffer MOS transistors 133, 133 ′, 133 ″, a buffer MOS transistor 135, ₁ for applying a refresh pulse.
35 ', 135 ", a terminal 136 for applying the pulse φ _F of its gate, a vertical shift register 137 for generating a reflection pulse, a vertical line 138,138' for reading the accumulated voltage from the basic photosensor cell 130. , 138 ″, a horizontal shift register 139 for generating a pulse for selecting each vertical line, MOS transistors 140, 140 ′, 140 ″ for gates for opening / closing each vertical line, an output for reading an accumulated voltage to an amplifier section line 141, after reading, reflation Tsu Shiyu pulse phi _HC charges accumulated in the output line to the MOS transistor 142, MOS transistor 142 for Rifuretsushiyu
143 for applying a voltage, a transistor 144 such as a bipolar, MOS, FET or J-FET for amplifying an output signal,
A load resistor 145, a terminal 146 for connecting the transistor 144 to the power supply, an output terminal 147 of the transistor, and MOS transistors 148, 148 ', 148 "for refreshing the charges accumulated in the vertical lines 138, 138', 138" in the read operation.
Also, this photoelectric conversion device is constituted by a terminal 149 for applying a pulse φ _VC to the gates of the MOS transistors 148, 148 ', 148 ".

The operation of this photoelectric conversion device will be described with reference to the pulse timing diagrams shown in FIGS. 7 and 8.

First, the collector potential of the photosensor cell section is kept at a positive voltage thereafter.

First, it is assumed that the accumulation operation is performed by time t ₁ and holes corresponding to the amount of incident light are accumulated in the p base regions in each photoelectric conversion cell 130.

At time t ₁ , the pulse signal φ _R rises to turn on the transistors 133, 133 ′ and 133 ″, and subsequently the pulse φ _{V 1} is output from the vertical shift register 132 and the positive voltage for reading is applied to the horizontal line 131. The photoelectric conversion cells 130 in the first row start a read operation, and the read signals of the photoelectric change cells in the first row appear on the vertical lines 138, 138 ', 138 ", respectively. When the read operation is completed, the pulse signal φ _HC turns on the transistor 142.
Then, the residual charge on the output line 141 is once refreshed.

After that, at time t ₂ , the pulse signal φ _H1 is output from the horizontal shift register 139 and the transistor 140 is turned on. As a result, the signal of the photoelectric conversion cell in the first row and the first column, which has been read out on the vertical line 138, is input to the transistor 144 via the transistor 140 and the output line 141, amplified, and output from the terminal 147. When this output operation ends, the pulse φ _HC rises and the output line 141 is refreshed. Subsequently, the pulse signals φ _H2 and φ _H3 are sequentially output from the horizontal shift register 139, and similarly, the signals of the photoelectric conversion cells in the first row, second column and the first row, third column are sequentially output from the terminal 147, each time the output line 141. Is refreshed.

Next, at time t ₃ , the pulse signals φ _F and φ _VC rise,
Further, the pulse signal φ _C1 is output from the vertical shift register 137, and the transistor 135 and the transistors 148, 148 ', 14
8 ″ is turned on, a positive voltage pulse for refresh is applied to the horizontal line 131, and the refresh operation is performed as described above.

Such first line similar reading and Rifuretsushiyu operation, from the time t ₄ of the second line, is performed for each of the photoelectric conversion cells 130 from the time t ₅ the third line. That is, at time t ₄ , the pulse signals φ _R and φ _V2 rise, and after the signals of this row are read out, φ _VC , φ _F, and φ _C2 sequentially rise, so that the photoelectric conversion cell 130 in the second row is selected. Then, the read and refresh operations are performed. Then, at time t ₅ , the photoelectric conversion cells in the second row start the accumulation operation, and at the same time, pulse signals φ _R , φ _V3 , φ _VC , φ _F and φ
_The photoelectric conversion cells 130 in the third row are sequentially selected after _{C3 and the} like have sequentially risen, and the above operations are similarly performed. When the third row enters the accumulation operation, the first row is selected and the same is repeated thereafter.

In this way, the read signal corresponding to the amount of incident light of all photoelectric conversion cells 130 is serially output from the terminal 147. Note that the photoelectric conversion cells 130 in each row have a constant time for performing the accumulation operation, and thus can be applied to, for example, a television video camera.

[Problems to be solved by the invention]

By the way, when the above conventional example is applied to a television video camera or the like, the following problems occur.

In the accumulation operation state, when strong light is irradiated, holes are accumulated in the base of the photoelectric conversion cell 130, and when the base potential is sequentially biased with respect to the emitter potential, the photoelectric light receiving strong light is irradiated. The potential of the vertical line connected to the emitter electrode of the conversion cell rises,
A so-called blooming phenomenon will occur. As a measure against this, the vertical line reset transistors 148, 148 ', 148 "are turned on during the period other than the read operation, and the vertical line 13
An example of the operation of refreshing the electric charge overflowing to the vertical line by setting 8,138 ', 138 "to the ground state is described in the conventional example. However, the vertical line reset transistors 148,148', 148" are turned on. Can be set only between times t _{3 and} t ₄ , and in a television video camera, only a horizontal scanning blanking period of about 10 μs is possible. Furthermore, during horizontal scanning (about 52.5 μs for TV video cameras), transistors 148 and 14
Since 8 ', 148 "must be turned off,
During this time, the blooming phenomenon still occurs due to the electric charge overflowing into the vertical line.

Further, in the conventional example, since the image signal is once stored in the vertical line by the reading operation and then sequentially output by the horizontal scanning, a false signal, that is, a so-called smear phenomenon occurs while the signal is stored in the vertical line. Also has the problem of.

Further, when applied to a television video camera, in the conventional example, the period during which the refresh operation can be performed is within the horizontal blanking period of about 10 μs, and the refresh period is short, so that the refresh operation cannot be performed sufficiently and an afterimage occurs. I also have.

Further, when the conventional example is used as a single-plate solid-state image sensor of a color television video camera, color filters are arranged on pixels by vapor deposition or adhesion, and for example, according to an arrangement method such as Bayer arrangement, R, G, B In the case of adopting the method of providing the vertical line for each color, at least two vertical lines are required for one column of pixels. At this time, since the vertical line portion does not serve as a photosensitive portion, arranging two vertical lines causes a problem of reduction in light receiving area, that is, reduction in aperture ratio.

An object of the present invention is to solve the above-mentioned problems of the prior art, specifically, without increasing the number of signal readout lines in the column direction, and thus without decreasing the aperture ratio of the photoelectric conversion cell in the photoelectric conversion region, It is to obtain a photoelectric conversion device capable of simultaneously reading a plurality of signals in the row direction.

[Means for solving problems]

In order to achieve the above object, the photoelectric conversion device of the present invention comprises a plurality of photoelectric conversion cells (130) arranged in rows and columns.
And a plurality of column-direction signal read lines (5, 5) provided in the column direction for reading the signals of the plurality of photoelectric conversion cells, respectively.
5 ′, 5 ″) and each column direction signal read line for selectively accumulating a first signal read from the plurality of photoelectric conversion cells via the plurality of column direction signal read lines. A first plurality of capacitors (7-1, 7-1 ', 7-1 ") and a second signal read from the plurality of photoelectric conversion cells via the plurality of column-direction signal read lines are selectively used. A second plurality of capacitors (7-2, 7-2 ′, 7-2 ″) connected to each column-direction signal read line for storage in a plurality of column-direction signal read lines and the plurality of column-direction signal read lines. A plurality of first switches (6-1, 6-1 ', 6-1 ") for connecting to the first capacitor at a predetermined first timing.
And a plurality of second switches (6−) for connecting the plurality of column-direction signal read lines and the plurality of second capacitors at a second timing different from the first timing.
2, 6-2 ′, 6-2 ″), a first row-direction read-out line (9-1) for reading out signals of the plurality of first capacitors, and signals of the plurality of second capacitors A second row-direction read-out line (9-2) for reading out, and a plurality of third switches (9) sequentially and selectively connecting the signals of the plurality of first capacitors to the first row-direction read-out line ( 8-1, 8-1 ', 8-1 ") and a plurality of fourth switches (8-) for sequentially and selectively connecting the signals of the plurality of second capacitors to the second row-direction read line. 2, 8-2 ', 8-2 ") and a plurality of third and fourth switches, each pair of which are simultaneously operated, while sequentially operating different pairs of third and fourth switches. The row-direction shift register (16) for increasing the number of column-direction read lines by having And the first plurality of row signals without, characterized in that it possible simultaneously read from the second row read line.

[Action]

By providing multiple capacitors that selectively accumulate the signals read out via the signal readout line, it is possible to shorten the time that the image signal appears on the vertical line, which causes blooming and smearing. Can be kept sufficiently low. Further, since the pixels can be separated from the capacitors after the image signals are stored in the capacitors, the refresh operation period can be extended and the afterimage phenomenon can be suppressed to a low level. Further, even when applied to a color video camera, if the number of capacitors corresponding to the number of color signals of column pixels is provided, only one vertical line is required, and eventually the aperture ratio can be increased.

Furthermore, since signals in a plurality of row directions can be read simultaneously from the first and second row direction read lines, it is possible to easily process signals in a plurality of rows at the same time, and even in that case. Since the number of column-direction read lines in the photosensitive region does not increase, the aperture ratio of the photoelectric conversion cell is not reduced.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a 4 × 4 matrix of the photoelectric conversion device according to the present invention.

The basic photosensor cell 130 (the collector of the bipolar transistor is connected to the substrate and the substrate electrode) surrounded by the dotted line described above, the horizontal line 1 as the horizontal read line for applying the read pulse and the refresh pulse 1,
1 ′, 1 ″, 1, vertical shift register 2 for generating a read pulse, vertical shift register 2 and horizontal line 1,1 ′,
Buffer MOS transistor between 1 ″, 1 3,3 ′, 3 ″, 3
, The terminal 4 for applying the pulse φ _R to the drains of the buffer MOS transistors 3, 3 ', 3 ", 3, the vertical shift register 16 for generating the refresh pulse, the vertical shift register 16 and the horizontal lines 1, 1 Buffer MOS between ′, 1 ″, 1
Transistors 17, 17 ', 17 ", 17, buffer MOS transistors 17, 17', 17", terminals for applying pulses to the drains of 17, 17 and vertical read lines for reading signal charges from the basic photosensor cell 130 Vertical lines as 5,5 ′, 5 ″, 5
, Capacitors 7-1, 7-2, 7- for accumulating signal charges
1 ', 7-2', 7-1 ", 7-2", 7-1,7-2, each capacitor 7-1,7-2,7-1 ', 7-2', 7-1 " , 7−
Transfer MOS transistors 6-1, 6-2, 6- between 2 ", 7-1, 7-2 and each vertical line 5, 5 ', 5", 5
1 ', 6-2', 6-1 ", 6-2", 6-1,6-2, horizontal shift register 16 for generating a pulse for selecting each storage capacitor, for opening / closing each storage capacitor Gate MOS transistors 8-1,8-2,8-1 ', 8-2', 8-
1 ″, 8-2 ″, 8-1, 8-2 output lines 9-1, 9-2 for reading the stored voltage to the amplifier section, MOS transistor 10− for refreshing the charge stored in the read line 1,1
0-2, terminal 11 for applying a refresh pulse to MOS transistors 10-1, 10-2, transistors 12-1, 12 such as bipolar, MOS-FET, J-FET for increasing the output signal −
2, MOS transistors 14, 14 'for reflecting the charges accumulated in the output terminals 13-1, 13-2 of the transistors 12-1, 12-2, the vertical lines 5, 5', 5 ", 5 This photoelectric conversion device is constituted by 14 ", 14 and a terminal 15 for applying a pulse to the gates of the MOS transistors 14, 14 ', 14", 14.

The operation of this photoelectric conversion device will be described with reference to the pulse timing charts shown in FIGS.

First, it is assumed that the collector potential of the photosensor cell section is kept at a positive potential thereafter.

First, it is assumed that the accumulation operation is performed by time t ₁ and holes corresponding to the amount of incident light are accumulated in the P base region in each photoelectric conversion cell 130.

At time t ₁ , the pulse signal φ _VC has already risen and the transistors 14, 14 ′, 14 ″, 14 are already in the ON state, and the pulse signal φ _T1 rises, and the transistors 6-1 and 6−
1 ', 6-1 ", 6-1 is in the ON state and the storage capacitor 7
The charges in -1, 7-1 ', 7-1 ", 7-1 are refreshed. Further, the pulse signal φ _HC rises and the transistor 10
-1, 10-2 are turned on, and the residual charges on the output lines 9-1, 9-2 are refreshed. Then, the pulse signal φ _VC falls, the transistors 14, 14 ′, 14 ″, 14 are turned off, and the vertical lines 5, 5 ′, 5 ″, 5 and the capacitors 7-1, 7
−1 ′, 7-1 ″, 7-1 becomes a floating state. Next, after the pulse signal φ _V1 is output from the vertical shift register 2 and the transistor 3 is turned on, the read pulse signal φ
_{When R} is applied to the terminal 4 and applied to the horizontal line 1 via the transistor 3, the photoelectric conversion cell 130 in the first row starts the read operation. By this read operation, the read signals of the photoelectric conversion cells in the first row are changed to the vertical lines 5, 5 ′, 5 ″, 5
And storage capacitors 7-1, 7-1 ', 7-1 ", 7-1
Appear in. When the read operation is completed, the pulse signal φ _T1 falls and the transistors 6-1, 6-1 ′, 6-1 ″, 6-1 turn off.
However, after the capacitors 7-1, 7-1 ', 7-1 ", 7-1 and the vertical lines 5, 5', 5", 5 are separated, the pulse signal φ _VC rises again and the vertical lines 5, 5 The residual charge of ′, 5 ″, 5 is refreshed.

At time t ₂ , the pulse signal φ _T2 rises, the transistors 6-2, 6-2 ′, 6-2 ″, 6-2 are turned on, and the storage capacitors 7-2, 7-2 ′, 7-2 ″, The charge in 7-2 is refreshed. Then, the pulse signal φ _VC falls, the transistors 14, 14 ′, 14 ″, 14 are turned off,
Next, when the pulse signal φ _V2 is output from the vertical shift register 2 and the read pulse signal φ _R is applied to the horizontal line 1 ′ through the terminal 4 after the transistor 3 ′ is turned on, the second line The photoelectric conversion cell 130 starts the read operation. By this read operation, the photoelectric conversion cells 13 in the second row
A read signal of 0 appears on the vertical lines 5,5 ', 5 ", 5 and the storage capacitors 7-2,7-2', 7-2", 7-2. When the read operation of the second row is completed, the pulse signal φ _T2 falls and the transistors 6-2, 6-2 ', 6-2 ", 6-2 are turned off.
Then, the capacitor 7-2,7-2 ', 7-2 ", 7-2 and the line 5,5', 5", 5 are disconnected, and then the pulse signal φ
_VC rises and the residual charge on the vertical lines 5, 5 ', 5 ", 5 is refreshed.

Next, at time t ₃ , the pulse signal φ _HC first falls, the transistors 10-1 and 10-2 are turned off, and subsequently the pulse signal φ _H1 is output from the horizontal shift register 16 and the transistors 8-1 and 10-2 are output. 8-2 is turned on. As a result, the charges accumulated in the capacitors 7-1 and 7-2 are transferred to the transistors 12-1 and 12 via the transistors 8-1 and 8-2 and the output lines 9-1 and 9-2.
It is amplified at -2 and output from terminals 13-1 and 13-2. When this output operation is completed, the pulse φ _HC rises and the output lines 9-1, 9-2 are refreshed. Subsequently, pulse signals φ _H2 and φ _H3 are sequentially output from the horizontal shift register 16, and similarly, signals of photoelectric conversion cells in the first row, second column, second row, second column, first row, third column, and second row, third column. Is the terminal 13-
It is output from 1,13-2, and output lines 9-1,9-
2 is refreshed.

At time t ₄ , the pulse signal φ from the vertical shift register
_C1 is output, the transistors 17 and 17 'are turned on, the pulse signal φ _F is applied to the terminal 18, the refresh pulse is applied to the horizontal lines 1 and 1'through the transistors 17 and 17', and the first and second rows are applied. The refresh operation is performed on the photoelectric conversion cell 130.

The operations similar to those in the first and second rows are performed on the photoelectric conversion cells 130 in the third and fourth rows from time t ₅ and again at time t ₆ in the first and second rows. It is selected, and the same operation is repeated thereafter.

In such an operation, when the signal charge appears on the vertical line, for example, if attention is paid to the output of the photoelectric conversion cell 130 in one row and one column, the pulse signal φ _R rises from the time t ₁ to t ₂ until φ _T1 rises. Only until the time of the descent. There is obviously some freedom in this time interval. In the conventional example, when applied to a television video camera, a signal charge is stored in the vertical line selected at the end of horizontal scanning for about 52.5 μs. Therefore, for example, if the above-mentioned time interval from turning ON of φ _R to falling of φ _T1 is set to 0.5 μs, the blooming phenomenon and the smear phenomenon will be reduced to about 10 times more than the conventional example.
It will be improved by 5 times (40 dB).

Further, since the storage capacitor is provided, the signal charge is once stored in the storage capacitor, and then the transistors 6-1 and 6-
2,6-1 ', 6-2', 6-1 ", 6-2", 6-1,6-2
If is turned off, the photoelectric conversion cell and the storage capacitor can be separated, so that the refresh operation of the photoelectric conversion cell 130 can be sufficiently performed thereafter. For example, time t
Since it can be applied to the refresh period during one horizontal scanning period from ₃ to time t ₅ , the afterimage phenomenon can be reduced as compared with the conventional example.

Further, when the present embodiment is applied to a color television video camera and the color filters are arranged on the sensor cells, if the storage capacitors are provided only for the types of colors arranged in the column direction and the same operation is performed, vertical lines are always formed. Only one line is required per row, and the aperture ratio of the sensor cell is not reduced. For example, as shown in FIG. 1, when the color filters RGB are arranged in a Bayer array and operated at the above pulse timing shown in FIG. 2, the capacitors 7-1 and 7-1 ″ have B
Signal is stored in 7-2, 7-1 ', 7-2 ", 7-1, and G signal is stored in 7-2' and 7-2.

In the present embodiment, an example of reading two lines in the vertical direction at the same time has been described, but of course, two lines or more may be read. In this case, it is sufficient to provide as many storage capacitors as there are vertical pixels to be read simultaneously.

3 is a diagram showing a second embodiment of the present invention. A decoder 19 is provided between the vertical shift register 2 and the horizontal lines 1, 1 ', 1 ", 1 to operate at the pulse timing shown in FIG. It was made to let.

In this embodiment, the function of the vertical register 16 for refreshing each photoelectric conversion cell is shared by the decoder 19 as compared with the first embodiment shown in FIG. 1, so that the configuration can be simplified. There is.

That is, to explain with reference to the timing chart of FIG. 4, first, t
_The accumulation operation is performed up to _1, and holes corresponding to the amount of incident light are accumulated in each photoelectric conversion cell 130 in the P base region.

At time t ₁ , the pulse signal φ _VC has already risen, and the pulse signal φ _T1 rises in a state where each vertical line has fallen to the ground, and capacitors 7-1, 7-1 ', 7-1 ", 7-
The charge of 1 is refreshed. After that, pulse signal φ
_A pulse φ _D1 is output from the decoder 19 after each vertical line and the capacitor are brought into a floating state by falling _VC .

As a result, the signals of the photoelectric conversion cells 130 in the first row are transmitted to the vertical lines and capacitors 7-1, 7-1 ', 7-1 ", 7-1.
Appears in. After this reading, the pulse signal φ _T1 falls and after separating each capacitor 7-1, 7-1 ', 7-1 ", 7-1 and each vertical line, φ _VC rises again and each vertical line After that, φ _T2 rises and after refusing capacitors 7-2, 7-2 ′, 7-2 ″, 7-2, φ _VC falls, and this time φ _D2 rises, the second
The signal from the photoelectric conversion cell in the row is the vertical line and the capacitor 7
-2,7-2 ', 7-2', are taken into 7-2. Then phi to Rifuretsushiyu vertical line rises to phi _VC and _T2 after lowering stand. First row of signal in this state Kiyapashita 7
-1,7-1 ', 7-1 ", 7-1, the signal of the second row is 7-2,7
-2 ', 7-2 ", 7-2.

After that, this signal is sequentially read out from t _{3 to} t ₅ as in the first embodiment. At this time, φ _D1 and φ _D2 are at high level from time t ₄ to immediately before time t ₅ , and during this period φ _VC is at high level. Therefore, the photoelectric conversion cells 130 in the first and second rows are refreshed.

The readout and refresh of the photoelectric conversion cells in the third and fourth rows are performed in the same manner.

As described above, according to this embodiment, the common vertical shift register is used for the refreshing and the reading of the photoelectric conversion cells in each row, so that the configuration can be extremely simplified.

Further, in this embodiment, the case where the number of output lines is two has been described, but of course, the number of output lines may be two or more. For example, if four output lines are provided for each color of the color filter as shown in the third embodiment shown in FIG. 5, the wiring capacity of the output line can be reduced to half that in the case of two output lines, which is large. The output can be obtained and the image processing circuit can be simplified.

In FIG. 5, the difference from the configuration shown in FIG. 1 is that 9-3 and 9-4 are provided as output lines, and instead of connecting the transistors 8-1 ′ and 8-1 to 9-1, they are connected to 9-3. 9-4 instead of connecting transistors 8-2 'and 8-2 to 9-2
The output line 9-3 and 9-4 are connected to the transistor 10-1 and 10-2, and the transistors 10-3 and 10-4 with the gates connected in common are provided to reflex the output lines 9-3 and 9-4. 9
-3, the output terminal 13-3 of the transistor 12-3 for outputting the signal, and the transistor 12-4 and the output terminal 13-4 for outputting the signal of the output line 9-4 are provided.

The same reference numerals as those in FIG. 1 indicate the same elements.

〔effect〕

As described in detail above, the photoelectric conversion device according to the present invention has a plurality of photoelectric conversion cells (13
0) and a plurality of column-direction signal read lines (5, 5) provided in the column direction for reading signals of the plurality of photoelectric conversion cells, respectively.
5 ′, 5 ″) and each column direction signal read line for selectively accumulating a first signal read from the plurality of photoelectric conversion cells via the plurality of column direction signal read lines. A first plurality of capacitors (7-1, 7-1 ', 7-1 ") and a second signal read from the plurality of photoelectric conversion cells via the plurality of column-direction signal read lines are selectively used. A second plurality of capacitors (7-2, 7-2 ′, 7-2 ″) connected to each column-direction signal read line for storage in a plurality of column-direction signal read lines and the plurality of column-direction signal read lines. A plurality of first switches (6-1, 6-1 ', 6-1 ") for connecting to the first capacitor at a predetermined first timing.
And a plurality of second switches (6−) for connecting the plurality of column-direction signal read lines and the plurality of second capacitors at a second timing different from the first timing.
2, 6-2 ′, 6-2 ″), a first row-direction read-out line (9-1) for reading out signals of the plurality of first capacitors, and signals of the plurality of second capacitors A second row-direction read-out line (9-2) for reading out, and a plurality of third switches (9) sequentially and selectively connecting the signals of the plurality of first capacitors to the first row-direction read-out line ( 8-1, 8-1 ', 8-1 ") and a plurality of fourth switches (8-) for sequentially and selectively connecting the signals of the plurality of second capacitors to the second row-direction read line. 2, 8-2 ', 8-2 ") and one pair of the plurality of third and fourth switches are simultaneously operated, while sequentially operating different pairs of third and fourth switches. And a row-direction shift register (16) for enabling a plurality of row-direction signals to be output to the first and the first signals. It becomes possible to read out simultaneously from the row-direction read-out lines, and it is possible to easily process the signals of a plurality of rows at the same time, and even in that case, it is necessary to increase the number of column-direction read-out lines in the photosensitive area together with the photoelectric conversion cells. Therefore, there is an effect that the aperture ratio of the photoelectric conversion cell is not lowered and the sensitivity is not impaired.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a photoelectric conversion device according to a first embodiment of the present invention,
2 is a timing chart thereof, FIG. 3 is a block diagram of a photoelectric conversion device of the second embodiment, FIG. 4 is a timing chart thereof, and FIG. 5 is a configuration diagram of a photoelectric conversion device of the third embodiment of the present invention. , FIG. 6 (A) is a plan view of a conventional photoelectric conversion device, FIG. 6 (B) is a sectional view taken along the line I-I, FIG. 6 (C) is its equivalent circuit diagram, and FIG. FIG. 8 is a timing chart of a circuit configuration diagram of a conventional photoelectric conversion device arranged in a matrix. 130 ... Photoelectric conversion cell, 5,5 ', 5 ", 5 ... Vertical line as signal readout line, 7-1,7-1', 7-1", 7-1
, 7-2,7-2 ', 7-2 ", 7-2 ...

Claims (1)

[Claims] 1. A plurality of photoelectric conversion cells (130) arranged in rows and columns, and a plurality of column direction signal read lines (rows) provided in the column direction to read out signals of the plurality of photoelectric conversion cells, respectively. 5,
5 ′, 5 ″) and each column direction signal read line for selectively accumulating a first signal read from the plurality of photoelectric conversion cells via the plurality of column direction signal read lines. A first plurality of capacitors (7-1, 7-1 ', 7-1 ") and a second signal read from the plurality of photoelectric conversion cells via the plurality of column-direction signal read lines are selectively used. A second plurality of capacitors (7-2, 7-2 ′, 7-2 ″) connected to each column-direction signal read line for storage in a plurality of column-direction signal read lines and the plurality of column-direction signal read lines. A plurality of first switches (6-1, 6-1 ', 6-1 ") for connecting to the first capacitor at a predetermined first timing.
And a plurality of second switches (6−) for connecting the plurality of column-direction signal read lines and the plurality of second capacitors at a second timing different from the first timing.
2, 6-2 ′, 6-2 ″), a first row-direction read-out line (9-1) for reading out signals of the plurality of first capacitors, and signals of the plurality of second capacitors A second row-direction read-out line (9-2) for reading out, and a plurality of third switches (9) sequentially and selectively connecting the signals of the plurality of first capacitors to the first row-direction read-out line ( 8-1, 8-1 ', 8-1 ") and a plurality of fourth switches (8-) for sequentially and selectively connecting the signals of the plurality of second capacitors to the second row-direction read line. 2, 8-2 ', 8-2 ") and one pair of the plurality of third and fourth switches are simultaneously operated, while sequentially operating different pairs of third and fourth switches. The row-direction shift register (16) for increasing the number of column-direction read lines by having And no more in the row direction of the signal first photoelectric conversion device characterized by being capable simultaneously read from the second row read line.