JPH0736574B2 - Communication control device - Google Patents

Description

The present invention relates to a communication control device for data communication.

In particular, the present invention relates to a communication control device in which a clock is flexibly changed according to a busy condition in busy control.

〔Overview〕

According to the present invention, in a communication control device for data communication, the number of X-OFF frames transmitted from a partner terminal device according to a busy condition is counted for a predetermined time, and when the count value exceeds a specified number, a transmission clock is automatically generated. By reducing the speed in stages, the overhead for X-ON frame and X-OFF frame reception processing is reduced, and the overall processing capacity including the application program of the host interface is prevented from decreasing. Is.

[Conventional technology]

Conventionally, a non-procedural communication control device performs flow control of transmission data by receiving an X-ON frame and an X-OFF frame from a partner terminal device during data transmission. That is, when an X-OFF frame is received, if it is being transmitted at that time, the communication control device stops the next data transmission after the end of transmission, and releases the terminal busy by receiving the X-ON frame from the partner terminal device, I was trying to continue sending data.

[Problems to be solved by the invention]

However, in such a conventional frame synchronization non-procedure communication control device, the flow control of the transmission data is performed by receiving the X-ON frame and the X-OFF frame from the partner terminal device. When the processing capacity becomes excessive due to the terminal device itself and the environment, that is, when the X-FF frames are frequently transmitted, the overhead for receiving the X-ON frame and the X-OFF frame increases, and There was a drawback that the overall processing capacity including the interface application program was reduced.

The present invention solves the above-mentioned drawbacks by reducing the overhead for the X-ON frame and X-OFF frame reception processing and preventing the deterioration of the overall processing capacity including the application program of the upper interface. An object of the present invention is to provide a communication control device capable of performing the communication.

[Means for solving problems]

The present invention enables the X-ON frame and the X-OFF from a terminal device.
In a communication control device having a line connection unit including a reception control circuit for receiving a frame and a transmission data control circuit for transmitting transmission data to the terminal device at a transmission clock, the line connection unit detects the X-OFF frame. Counting means for counting each time, timer means for counting from the start of reception of the reception control circuit and outputting a timeout signal after a lapse of a predetermined time, and comparing for comparing the output of the counting means with a specified value according to the timeout signal. Means and
Setting means for setting the speed of the transmission clock based on the result of the comparing means.

[Action]

The counting means counts each time an X-OFF frame is detected. The timer means counts the time from the start of the receiving operation, and outputs a time-out signal after a lapse of a predetermined time. The comparing means compares the output of the counting means with the specified value. If the output of the counting means is greater than or equal to the specified value,
The speed of the transmission clock is reduced, otherwise it is left unchanged, and after the comparison operation by the comparison means is completed, the count value of the count means is set to the initial value. By the above operation, the overhead for the X-ON frame and X-OFF frame reception processing can be reduced, and the deterioration of the overall processing capability including the application program of the upper interface can be prevented.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention. In FIG. 1, a microprocessor 31 for performing communication control in the communication control device 30, a memory 32 for storing a data buffer and a program for communication control, and a central processing unit via an input / output channel 200. An input / output channel adapter 33 that performs an interface is connected to the bus 100.

Here, the feature of the present invention is the line interface portion surrounded by the alternate long and short dash line. That is, the bus 100 is connected to the line connection unit 34 ₁ to 34N, the line connection unit 34 ₁ to 34N is connected to the destination terminal apparatus outside each view through the line interface lines 201 ₁ ~201n. The line connection units 34 _{1 to} 34 n interface with each other terminal device, count X-OFF frames from the other terminal device, compare the count value within a predetermined time with a specified value, and compare the results. The transmission clock speed is automatically set to the optimum value based on.

FIG. 2 is a block diagram of a line connection unit of the communication control device of the present invention.

In FIG. 2, 1 is an X-OFF frame reception detection circuit,
Reference numeral 2 is a counter circuit for counting the number of X-OFF receptions by "+1", 3 is a timer circuit for knowing the elapse of a predetermined time from the start of the reception operation, and 4 is a preset value and counter circuit which is preset and held internally. A comparison circuit that compares the counter value in 2 and outputs the result, 5 is a transmission clock selection register that selects a transmission clock, 6 is a transmission clock generation circuit that generates 8 types of transmission clocks, and 7 is 8 types A transmission clock multiplexer for selecting a transmission clock, 8 a transmission data control circuit for controlling transmission data, 9 a reception data control circuit for controlling reception data, 10 and 11 line drivers, 12 and 13 line receivers, 100 a bus , 101 is the fastest transmission clock A line of the eight types, 102 is the second fastest transmission clock B line of the eight types, and 103 is the third fastest transmission clock C of the eight types. , 104 is the fourth fastest transmission clock D line of the eight types, 105 is the fifth fastest transmission clock E line of the eight types, 106 is the sixth fastest transmission clock F line of the eight types, 107 Is the 7th fastest transmission clock G line of 8 types, 108 is the slowest transmission clock H line of 8 types, 109 is the transmission clock line, 1
Reference numeral 10 is a transmission data line, 111 is a reception clock line, 112 is a reception data line, and 113 is a counter value in the counter circuit 2 and a timer value in the timer circuit 3 as initial values (all “0”) after the comparison operation is completed. Reset line to reset to, 11
Reference numeral 4 is a timer activation line indicating that the reception data control circuit 9 has notified that the reception operation start state has been reached, and 115 is a comparison activation line indicating that the timer value in the timer circuit 3 has reached a predetermined value. . When further captured, a circuit for checking an error in the received data, a circuit for adding an error detection code to the transmitted data, a control line and a control circuit for controlling a line interface other than the transmitted / received data are omitted for simplicity. ing.

FIG. 3 is a block diagram of a data communication device including the communication control device of the present invention. In FIG. 3, reference numeral 40 denotes a central processing unit and 41 denotes an input / output channel controller, and the same portions as those in FIG. 1 are designated by the same reference numerals.

The operation of the communication control device having such a configuration will be described. In FIG. 2, the transmission clock is selected from the values set in the transmission clock selection register 5 before starting the transmission / reception operation. The transmission clock selection register 5 has a 3-bit length. When it is binary "000", the transmission clock A line is used. When it is "001", the transmission clock B line is used.
The transmission clock C line is "010", the transmission clock D line is "011", the transmission clock E line is "100", the transmission clock F line is "101", and "110". The transmission clock multiplexer 7 is instructed to select the transmission clock G line in the case of, and the transmission clock H line in the case of “111”. The transmission clock selection register 5 can be arbitrarily set, but is normally set at the highest speed of "000".

The transmission data is transmitted bit-serially on the transmission data line 110 in synchronization with the transmission clock. The reception data is sent out on the reception data line 112 bit-serially in synchronization with the reception clock from the terminal. The send / receive data frame is a flag format of high level data link control procedure,
The control field distinguishes between an X-OFF frame and a general data frame. When an X-OFF frame is received, the X-OFF frame reception detection circuit 1 causes X-O
The FF frame is detected, and the count value in the counter circuit 2 is set to "+1". The timer circuit 3 is activated by the timer activation line 114, and activates the comparison activation line 115 when a specified time has elapsed. The time interval in the timer circuit 3 can be set to an arbitrary value. The count comparison value in the comparison circuit 4 also has a flexible mechanism that can be set to an arbitrary value. When the comparison circuit 4 is activated by the comparison activation line 115, the comparison circuit 4 compares the current count value of the counter circuit 2 with the count comparison value in the comparison circuit 4. If the current count value of the counter circuit 2 is greater than or equal to the count comparison value in the comparison circuit 4, the contents of the transmission clock selection register 5 are set to "001" in binary and the transmission clock A
The transmission clock B line 102 is selected from the line 101. In this way, when the X-OFF frame exceeds the specified value within the specified time or is equal to the specified number, the speed is made slower than the current transmission clock to reduce the busy state due to the load of the terminal device as much as possible, The amount of transmission data transmitted from the communication control device is controlled according to the processing capacity of the device itself. If the current count value of the counter circuit 2 is smaller than the specified value in the comparison circuit 4, the contents of the transmission clock selection register 5 are left unchanged. Therefore, the transmission clock A line 101 is selected as it is, and the speed of the transmission clock remains unchanged. When the comparison operation by the comparison circuit 4 is completed, the count value in the counter circuit 2 is reset to an initial value, that is, all “0” in binary by the reset line 113, and is again set to an arbitrary value. Timer circuit 3
Stops the timer operation until it is activated again by the timer activation line 114. The contents of the transmission clock selection register 5 are "000" to "111" in binary, and when it becomes "111" in binary, a slower transmission clock below that cannot be specified.

By repeatedly executing the X-OFF frame reception detection and comparison operation as described above, the transmission data is transmitted to the terminal by selecting the optimum transmission clock according to the load, busy condition and processing capacity of the terminal device. ing.

The transmission / reception data is stored in the transmission / reception data buffer in the memory 32, and then transmitted via the input / output channel 200 to the central processing unit 4.
Although it is exchanged with 0, the detailed operation is omitted here.

〔The invention's effect〕

As described above, the present invention counts the number of X-OFF frames transmitted according to the environment of the partner terminal device, that is, the number of X-OFF frames transmitted according to the busy condition for a predetermined time in the communication control device, and the value is equal to or more than a specified value. In this case, since the transmission clock speed of the communication control device is gradually reduced, the transmission clock speed can be flexibly changed according to the processing capacity, environment and busy condition of the partner terminal device. Also, the overhead for X-OFF frame reception processing can be reduced, the overall processing capacity including the application program can be prevented from decreasing, and the transmission clock speed can be automatically set according to the partner terminal device without initial setting. There is an excellent effect that can be set to the optimum value.

[Brief description of drawings]

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention. FIG. 2 is a block configuration diagram of a line connection unit of the communication control device of the present invention. FIG. 3 is a block configuration diagram of a data communication device including a communication control device of the present invention. 1 ... X-OFF frame reception detection circuit, 2 ... counter circuit, 3 ... timer circuit, 4 ... comparison circuit, 5 ... transmission clock selection register, 6 ... transmission clock generation circuit,
7 ... Transmission clock multiplexer, 8 ... Transmission data control circuit, 9 ... Reception data control circuit, 10, 11 ... Line driver, 12, 13 ... Line receiver, 30 ... Communication control device, 31 ... Micro Processor, 32 …… Memory, 33 ……
I / O channel adapter, 34 _{1 to} 34n …… Line connection, 40
...... Central processing unit, 41 ...... Input / output channel controller, 100 ...... Bus, 101 ...... Transmission clock A line, 102 ......
Transmission clock B line, 103 ... Transmission clock C line, 104 ...
Transmission clock D line, 105 ... Transmission clock E line, 106 ...
Transmission clock F line, 107 ... Transmission clock G line, 108 ...
Transmission clock H line, 109 ... transmission clock line, 110 ... transmission data line, 111 ... reception clock line, 112 ... reception data line, 113 ... reset line, 114 ... timer start line, 115
…… Comparison start line, 200 …… I / O channel, 201 _{1 to} 201n
...... Line interface line.

Claims (1)

[Claims] 1. An X-ON frame and an X-OF from a terminal device.
In a communication control device comprising a line control unit including a reception control circuit for receiving an F frame and a transmission data control circuit for transmitting transmission data to the terminal device at a transmission clock, the line connection unit transmits the X-OFF frame. Counting means for counting each time it is detected, timer means for counting from the reception start of the reception control circuit and outputting a time-out signal after a lapse of a predetermined time, and comparing the output of the counting means with a specified value according to the time-out signal. Comparing means and clock setting means for setting the transmission clock speed by selecting the next slower clock speed than the currently set clock speed when the output of the counting means exceeds the specified value. And a communication control device.