JPH0736429U - Chip type 3 terminal capacitor - Google Patents

Abstract

(57) [Summary] [Structure] The thin film layer 16a having a predetermined shape and having a lower dielectric constant than the ceramic single plate 11 is used as the ceramic single plate 1.
A chip-type three-terminal capacitor formed between the capacitor 1 and the capacitance forming electrode 12a. [Effects] Small capacitors are connected in series in the vicinity of the formation location of the thin film layer 16a. Therefore, by changing the relative permittivity, shape, and formation location of the thin film layer 16a, the capacitance forming electrodes 12a, 13a and the ground are formed. The overall combined capacitance can be adjusted to a predetermined size without setting the shapes of the connection electrodes 15a and 15b to be small, and the noise removal effect is enhanced, and the current capacity, the soldering strength, etc. It is possible to prevent the performance deterioration of.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a chip-type three-terminal capacitor, more specifically, an end electrode and a counter electrode are formed, and is used as an electronic component for noise prevention such as a filter in OA equipment, digital equipment, electronic equipment for automobiles, etc. The present invention relates to a chip type three terminal capacitor.

[0002]

[Prior art]

 2. Description of the Related Art In recent years, in order to reduce the size, weight and density of electronic equipment, miniaturization of electronic components such as capacitors has been promoted. On the other hand, as digitalization of electronic circuits in microcomputers progresses, malfunction due to noise becomes a problem, and electronic components for EMI (Electro Magnetic Interference) countermeasures are becoming more and more important.

Conventionally, a chip-type multilayer capacitor is known as a chip-type capacitor that can be surface-mounted on an IC substrate or the like. This chip type multilayer capacitor is constructed by embedding internal electrodes in layers between dielectric ceramics to form a laminated body and further forming external electrodes at both ends of this laminated body. The capacitor constructed in this way is used as a two-terminal capacitor in noise elimination components such as filters.

However, when the two-terminal capacitor is used as a noise removing component in OA equipment, digital equipment, automobile electronic equipment, etc., there is a problem that the effect of removing high frequency noise and unnecessary radiation is insufficient. Three-terminal capacitors are excellent for dealing with such problems.

FIG. 6 is a front sectional view schematically showing a conventional comb-shaped three-terminal capacitor, and in the figure, reference numeral 61 denotes a dielectric ceramic substrate formed in a substantially disc shape. Opposing electrodes 62 and 63 are formed on both surfaces of the dielectric ceramic substrate 61, respectively, and a terminal 62a is connected to the counter electrode 62 on the front side and terminals 63a and 63b are connected to the counter electrode 63 on the back side. Has been done. A resin layer 64 covering the dielectric ceramic substrate 61 is formed, and the dielectric ceramic substrate 61, the counter electrodes 62 and 63, the terminals 62a, 63a and 63b, and the like form a comb-shaped three-terminal capacitor 60.

[0006]

[Problems to be solved by the device]

 In the above-described conventional comb-type three-terminal capacitor 60, when it is manufactured, it is troublesome to cut out the disk-shaped dielectric ceramic substrate 61 from the substrate material and form the counter electrodes 62 and 63 individually. Therefore, it is difficult to mass-produce it, and the manufacturing cost is high.

Further, the comb-shaped three-terminal capacitor 60 is mounted on an IC substrate or the like by a plug-in method instead of surface mounting, and in the case of the plug-in mounting, holes for insertion of the terminals 62a, 63a, 63b are provided on the IC board side. Since a forming process is required, there is a problem that mounting is time-consuming and the cost of the electronic device as a product is high.

The present invention has been made in view of the above problems, and can improve the noise removal effect, can be surface-mounted on an IC substrate or the like, and can be mass-produced and reduced in cost. Its purpose is to provide a chip-type 3-terminal capacitor that can ensure high reliability.

[0009]

[Means for Solving the Problems]

 In order to achieve the above object, a chip type three-terminal capacitor according to the present invention has at least one capacitor-forming electrode formed on each of both main surfaces of a ceramic single plate, and the capacitor is formed on the one main surface. At least two end electrodes connected to both ends of the capacitance forming electrode are formed on one set of end faces, and at least one ground connected to the capacitance forming electrode formed on the other main surface. The connecting electrodes are formed on one side or both sides of the other set of end faces, and a thin film layer of a predetermined shape having a dielectric constant lower than that of the ceramic veneer is formed on at least one of the ceramic veneer and the ceramic veneer. It is characterized in that it is formed between the capacitance forming electrode and / or the earth connection electrode (1).

In the chip-type three-terminal capacitor (1) described above, an insulating layer is formed on at least one surface excluding the set of end surfaces on which the end electrodes are formed, except for the ground connection electrode portion. It is characterized by (2).

[0011]

[Action]

 Generally, in order to take measures against noise, it is necessary for the capacitor to have a capacitance of 22 to 2200 pF (pico Farad) or more based on the frequency range of noise. However, it is technically and production-efficient to change the electrostatic capacity to a desired value within the above-mentioned large range only by setting the relative permittivity of the ceramic single plate. It is difficult to adjust the capacitance over a wide area only by the size of the area. Further, in order to adjust the capacitance to 100 pF or less, in the case of a chip type three-terminal capacitor in which the shape of the electrodes is set relatively thin, the current capacity of the capacitance forming electrodes connected to the end electrodes is Will be reduced. In addition, with respect to the capacitance forming electrode to which the ground connection electrode is connected, an inductance component is generated on the ground side, which reduces noise removal performance. It becomes difficult to secure the soldering strength.

On the other hand, a thin film layer having a predetermined shape having a dielectric constant lower than that of the ceramic single plate is provided between the ceramic single plate and at least one of the capacitance forming electrode and / or the earth connecting electrode. In the case of the chip-type three-terminal capacitor formed in, the structure is such that small capacitors are connected in series in the vicinity of the location where the thin film layer is formed. Therefore, by changing the dielectric constant, the shape, and the formation location of the thin film layer, it is possible to set the combined electrostatic capacitance as a whole without setting the shapes of the capacitance forming electrode and the ground connection electrode to be thin. Can be adjusted to the size of. Therefore, the performance deterioration such as the noise removal, the current capacity, the soldering strength, etc. can be prevented.

According to the chip-type three-terminal capacitor (1) described above, it is possible to form a capacitance between the capacitance-forming electrodes or between the capacitance-forming electrode and the ground-forming electrode, Although it has a three-terminal structure, it can be made into a chip, and a simple structure suitable for mass production can be realized, and the manufacturing cost can be reduced. In addition, since it is possible to mount on the surface of an IC substrate and the like, and because the step of forming a terminal insertion hole in the component to be mounted is not required, the labor for mounting is saved and the product is The cost of electronic devices will be reduced. Further, since the capacitance forming electrode, the end electrode and the ground connection electrode can be formed afterwards, there is no need to perform simultaneous sintering, and the melting point of the electrode material is relatively low and relatively inexpensive. It is possible to use various Ag and the like, and the manufacturing cost can be reduced.

Further, since it is possible to increase the number of connection portions of the ground connection electrode and the end electrode, the connection between them is made reliable, the connection failure rate is reduced, and high reliability is secured. You will get it.

In the chip-type three-terminal capacitor (1) described above, an insulating layer is formed on at least one surface excluding the set of end surfaces on which the end electrodes are formed, excluding the ground connection electrode portion. In this case, an action similar to that of the chip-type three-terminal capacitor (1) can be obtained, and moisture and the like can be prevented from entering the capacitance forming electrode, so that oxidation and corrosion of the capacitance forming electrode can be prevented. It becomes possible, and it becomes possible to secure high reliability. Moreover, since the end electrode and the ground connection electrode are exposed without being covered by the insulating layer, when the surface mounting is performed on an IC substrate or the like, the end electrode and the ground electrode are not hindered by the insulating layer. It is possible to connect the electrode for earth connection.

[0016]

【Example】

An embodiment of a chip type three-terminal capacitor according to the present invention will be described below with reference to the drawings. 1 is a schematic view showing a first embodiment of a chip type three-terminal capacitor according to the present invention, (a) is a perspective view, (b) is a plan view and (c) is a bottom view. One capacitance forming electrode 12a having a predetermined width is formed on one main surface 11a of the ceramic single plate 11 formed in a substantially rectangular parallelepiped shape, and one capacitance type electrode having a predetermined width is formed on the other main surface 11b. The formation electrode 13a is formed so as to intersect with the capacitance forming electrode 12a. On one set of end faces 11c, 11d of the ceramic single plate 11, two end electrodes 14a, 14b connected to both ends of the capacitance forming electrode 12a are formed over substantially the entire surface, and another set of end faces is formed. On the electrodes 11e and 11f, two ground connection electrodes 15a and 15b having a predetermined width are formed which are connected to both ends of the capacitance forming electrode 13a. The capacitance forming electrode 12a and the end electrodes 14a and 14b are not in contact with the capacitance forming electrode 13a and the ground connection electrodes 15a and 15b. A thin film layer 16a having a predetermined area is formed at a predetermined position between the capacitance forming electrode 12a and the ceramic single plate 11, and the thin film layer 16a has a relative dielectric constant (approximately 10 ⁴ to 10 ^{5) of the} ceramic single plate 11. 2) has a predetermined dielectric constant (approximately 6 to 7) lower than that of A chip-type three-terminal capacitor 10 is configured by including the ceramic single plate 11, the capacitance forming electrodes 12a and 13a, the end electrodes 14a and 14b, the ground connection electrodes 15a and 15b, and the thin film layer 16a.

When the chip-type three-terminal capacitor 10 having the above-described structure is manufactured, first, SrTiO ₃ powder is used as a main raw material, and a valence control agent for semiconducting the raw material with respect to 100 moles of the main raw material. 0.1 to 0.5 mol of Nb ₂ O ₅ and CuO as a sintering aid that contributes to improvement and stabilization of porcelain characteristics are compounded at a ratio of about 0.2 mol. Next, these raw materials are mixed and kneaded together with a binder, water and a dispersant, and then a substantially sheet-shaped ceramic raw substrate is formed by, for example, an extrusion molding method. Next, after slitting the ceramic raw substrate so that the chip type three-terminal capacitor 10 has a predetermined shape, baking is performed at a temperature of 1450 to 1500 ° C. for about 2 in a reducing atmosphere containing a few% of hydrogen. It is carried out for 6 hours to form a semiconductor into a sintered body. Next, a grain boundary insulating paste made of a mixture of Bi ₂ O ₃ , CuO and the like is applied to this sintered body, and then heat treatment is performed in air at 1100 to 1300 ° C. Then, by this heat treatment, the grain boundary insulating component diffuses between the crystal grains of the sintered body, and the crystal grain boundaries are insulated.

The grain boundary insulating type semiconductor ceramic substrate thus formed is used as a ceramic single plate 11 and a glass having a dielectric constant lower than that of the ceramic single plate 11 is provided at a predetermined position on the one main surface 11a. Apply the paste by screen printing to a predetermined shape. Then, a baking process at a temperature of 600 to 850 ° C. is performed to form the thin film layer 16a. Next, an electrode paste containing one of Ag, Al, Zn, and Ni is screen-printed at a predetermined location on one main surface 11a including the thin film layer 16a and a predetermined location on the other main surface 11b. After applying each to a predetermined shape, a baking treatment is performed at a temperature of 600 to 850 ° C. to form the capacitance forming electrodes 12a and 13a. After that, the slit processing part is cut into a chip shape. Next, an electrode paste such as Ag is applied to one set of the end faces 11c and 11d of the ceramic single plate 11 and the other set of the end faces 11e and 11f by screen printing or dip treatment in a predetermined shape. A baking process is performed at a temperature of 500 to 700 ° C. to form the end electrodes 14a and 14b and the ground connection electrodes 15a and 15b. If necessary, Ni and Sn or solder is used to perform electrode plating on the capacitance forming electrodes 12a and 13a, the end electrodes 14a and 14b, and the ground connection electrodes 15a and 15b.

In the chip-type three-terminal capacitor 10 configured as described above, a capacitance is formed by the capacitance forming electrodes 12a and 13a and the ground connecting electrodes 15a and 15b, and the end connected to the capacitance forming electrode 12a. The partial electrodes 14a and 14b have three terminals serving as two external terminals. When the chip type three-terminal capacitor 10 is connected to a printed circuit board or the like, the end electrodes 14a and 14b are connected to the signal line and the ground connection electrodes 15a and 15b are connected to the ground line by soldering or the like.

As is apparent from the above description, in the chip-type three-terminal capacitor 10 according to the first embodiment, a capacitance can be formed between the capacitance forming electrodes 12a and 13a and the ground connecting electrodes 15a and 15b, Although it has a three-terminal structure, it can be made into a chip, and by forming the thin film layer 16a, desired capacitance can be obtained without thinning the shape of the capacitance forming electrodes 12a and 13a and the ground connection electrodes 15a and 15b. Obtainable. As a result, noise can be effectively removed, and performance deterioration such as current capacity and soldering strength can be prevented. In addition, the structure can be simple and suitable for mass production, and the manufacturing cost can be reduced. Moreover, since it can be surface-mounted on an IC substrate and the like, and the step of forming a terminal insertion hole in the component on the side to be mounted can be eliminated, the labor for mounting can be saved, and the electronic product The cost of equipment can be reduced. Further, since the capacity forming electrodes 12a and 12b, the end electrodes 14a and 14b, and the ground connection electrodes 15a and 15b can be formed afterwards, it is not necessary to perform simultaneous sintering with the ceramic single plate 11, and the electrode material is used. As such, relatively inexpensive Ag or the like having a low melting point can be used, and the manufacturing cost can be reduced. Further, since the grain boundary insulating semiconductor porcelain substrate is used for the ceramic single plate 11, a large capacitance can be obtained.

In the first embodiment, the case where the end electrodes 14a and 14b connected to the capacitance forming electrodes 12a and 13a are formed over substantially the entire surface of the pair of end faces 11c and 11d has been described. In the embodiment, it may be formed on a part of the end faces 11c and 11d.

Further, although the case where the ground connection electrodes 15a and 15b are formed is shown in the first embodiment, in another embodiment, either of the ground connection electrodes 15a and 15b is formed. May be.

FIG. 2 is a schematic diagram showing a chip type three-terminal capacitor according to a second embodiment, (a) is a perspective view, (b) is a plan view, and (c) is a bottom view. Unlike the one shown in FIG. 1, a thin film layer 16b having a predetermined area is formed at a predetermined position between the earth connection electrode 15a and the ceramic single plate 11, and the thin film layer 16a (FIG. 1) is formed. It has not been. A chip-type three-terminal capacitor 20 is configured by including the ceramic single plate 11, the capacitance forming electrodes 12a and 13a, the end electrodes 14a and 14b, the ground connection electrodes 15a and 15b, and the thin film layer 16b. When manufacturing the chip type three-terminal capacitor 20, a glass paste having a lower relative dielectric constant than the ceramic single plate 11 is applied to a predetermined shape on the end face 11e of the ceramic single plate 11 in a predetermined shape by screen printing. Thus, the thin film layer 16b is formed, and the glass paste is not applied to the one main surface 11a. The other structure and manufacturing method are the same as in the case of the chip type three-terminal capacitor 10, and therefore detailed description thereof is omitted here.

In the chip-type three-terminal capacitor 20 according to the second embodiment, a capacity can be formed by the capacity-forming electrodes 12a and 13a and the ground connection electrodes 15a and 15b. By forming the thin film layer 16b, a desired capacitance can be obtained without thinning the shape of the capacitance forming electrodes 12a and 13a and the ground connection electrodes 15a and 15b. As a result, it is possible to obtain substantially the same effect as that of the first embodiment.

Although the thin film layer 16b is formed on the ground connection electrode 15a side in the second embodiment, it may be formed on the ground connection electrode 15b side in another embodiment. Good.

In the second embodiment, the case where the two ground connection electrodes 15a and 15b are formed has been described, but in another embodiment, the ground connection electrode 15b may be omitted. Good.

FIG. 3 is a schematic view showing a chip type three-terminal capacitor according to a third embodiment, (a) is a perspective view, (b) is a plan view, and (c) is a bottom view. Unlike the one shown in FIG. 1, a thin film layer 16b having a predetermined area is also formed at a predetermined position between the ground connection electrode 15a and the ceramic single plate 11. Further, two end electrodes 14c and 14d connected to one end of the capacitance forming electrode 12a are formed on the end face 11c with a predetermined width. These ceramic single plate 11, capacitance forming electrodes 12a and 13a, The chip-type three-terminal capacitor 30 is configured to include the terminal electrodes 14b, 14c, 14d, the ground connection electrodes 15a, 15b, and the thin film layers 16a, 16b. When manufacturing the chip-type three-terminal capacitor 30, a glass paste having a lower relative dielectric constant than the ceramic single plate 11 is also screen-printed to a predetermined shape on the end face 11e of the ceramic single plate 11 at a predetermined position. The thin film layer 16b is formed by coating. The rest of the configuration and manufacturing method are the same as those of the chip-type three-terminal capacitor 10, so a detailed description thereof will be omitted here.

In the chip-type three-terminal capacitor 30 according to the third embodiment, it is possible to form a capacity between the capacity forming electrodes 12a and 13a and the ground connection electrodes 15a and 15b. By forming the thin film layers 16a and 16b, desired capacitance can be obtained without thinning the shape of the capacitance forming electrodes 12a and 13a and the ground connection electrodes 15a and 15b. As a result, substantially the same effect as that of the first embodiment can be obtained. In addition, since the end electrodes 14b, 14c, and 14d can be connected to the capacitance forming electrode 12a at three places, these connections can be secured and the connection failure rate can be reduced. It is possible to secure high reliability.

In the third embodiment, the case where the two end electrodes 14c and 14d connected to the capacitance forming electrode 12a are formed on the end face 11c has been described, but in another embodiment, the capacitance forming is performed. Two end electrodes connected to the working electrode 12a are formed on the end surface 11d, or two ground connection electrodes connected to the capacitance forming electrode 13a are formed on the end surface 11e and / or the end surface 11f. It may be formed.

Although the thin film layer 16b is formed on the ground connection electrode 15a side in the third embodiment, it may be formed on the ground connection electrode 15b side in another embodiment. Good.

Further, in the third embodiment, the case where the two ground connection electrodes 15a and 15b are formed is shown, but in another embodiment, the ground connection electrode 15b may be omitted. Good.

FIG. 4 is a schematic view showing a chip type three-terminal capacitor according to a fourth embodiment, (a) is a perspective view, (b) is a plan view, and (c) is a bottom view. Unlike the one shown in FIG. 1, two capacitor forming electrodes 12a and 12b having a predetermined width are formed on one main surface 11a of the ceramic single plate 11, and the earth connecting electrode 15a and the ceramic single plate 11a are formed. A thin film layer 16b having a predetermined area is formed at a predetermined location between the plate 11 and the thin film layer 16a (FIG. 1) is not formed. A chip type three-terminal capacitor 40 is constituted by including the ceramic single plate 11, the capacitance forming electrodes 12a, 12b and 13a, the end electrodes 14a and 14b, the ground connecting electrodes 15a and 15b, and the thin film layer 16b. When manufacturing the chip-type three-terminal capacitor 40, a glass paste having a lower relative dielectric constant than the ceramic single plate 11 is applied to a predetermined shape by screen printing at a predetermined position on the end face 11e of the ceramic single plate 11. The thin film layer 16b is formed as a result, and the glass paste is not applied to the one main surface 11a. Further, an electrode paste containing one of Ag, Al, Zn, and Ni is applied to two predetermined locations on the one main surface 11a in a predetermined shape by screen printing to form the capacitance forming electrodes 12a and 12b. To form. The rest of the configuration and manufacturing method are the same as those of the chip-type three-terminal capacitor 10, so a detailed description thereof will be omitted here.

In the chip-type three-terminal capacitor 40 according to the fourth embodiment, a capacity can be formed between the capacity forming electrodes 12a, 12b and 13a and the ground connection electrodes 15a and 15b, and the chip type three-terminal capacitor 40 is used. By forming the thin film layer 16b, a desired capacitance can be obtained without thinning the shape of the capacitance forming electrodes 12a, 12b, 13a and the ground connection electrodes 15a, 15b. . As a result, it is possible to obtain substantially the same effect as that of the first embodiment.

Although the thin film layer 16b is formed on the side of the ground connection electrode 15a in the fourth embodiment, it may be formed on the side of the ground connection electrode 15b in another embodiment. Good.

Although the thin film layer 16b is formed on the side of the ground connection electrode 15a in the fourth embodiment, the thin film layer is formed as the capacitance forming electrode 12a and / or the capacitance forming electrode in another embodiment. It may be formed on the side of 12b.

Further, in the above-described fourth embodiment, the case where the two ground connection electrodes 15a and 15b are formed is shown, but in another embodiment, the ground connection electrode 15b may be omitted. Good.

FIG. 5 is a schematic diagram showing a chip type three-terminal capacitor according to a fifth embodiment. (A) is a perspective view, (b) is a plan view, and (c) is a bottom view. An insulating layer 51a is formed on one main surface 11a including the capacitance forming electrode 12a of the chip type three-terminal capacitor 20 shown in FIG. 2, and an insulating layer 51a is formed on the other main surface 11b including the capacitance forming electrode 13a. The layer 51 b is formed, and these ceramic single plate 11, capacitance forming electrodes 12 a and 13 a, end electrodes 14 a and 14 b, ground connecting electrodes 15 a and 15 b, thin film layer 16 b, and insulating layers 51 a and 51 b are formed. The chip-type three-terminal capacitor 50 is configured to include it. When manufacturing the chip type three-terminal capacitor 50, after forming the capacitance forming electrodes 12a and 13a in the manufacturing process of the chip type three terminal capacitor 10 shown in FIG. 1, the capacitance forming electrodes 12a and 13a are formed. A glass paste is applied in a predetermined shape by screen printing on the main surfaces 11a and 11b including the glass paste. After that, baking treatment is performed at a temperature of 600 to 850 ° C. to form the insulating layers 51a and 51b. The other configurations are the same as those of the chip-type three-terminal capacitor 20, and the manufacturing method is the same as that of the chip-type three-terminal capacitor 10, and therefore detailed description thereof is omitted here.

In the chip-type three-terminal capacitor 50 according to the fifth embodiment, substantially the same effect as that of the second embodiment can be obtained, and at the same time, the entry of moisture or the like into the capacitance forming electrodes 12a and 13a can be prevented. Therefore, it is possible to prevent oxidation and corrosion of the capacitance forming electrodes 12a and 13a and to ensure high reliability. Moreover, since the end electrodes 14a, 14b and the ground connection electrodes 15a, 15b are exposed without being covered by the insulating layers 51a, 51b, when the surface mounting is performed on the IC substrate or the like, the end electrodes 14a, 14b, ground It is possible to prevent the connection between the connection electrodes 15a and 15b from being hindered by the insulating layers 51a and 51b.

In yet another embodiment, an insulating layer 51a, 51b is formed on the main surfaces 11a, 11b including the capacitance forming electrodes 12a, 12b, 13a in any of the above embodiments. be able to.

In each of the above-described embodiments, the case where a grain boundary insulating semiconductor ceramic substrate having good temperature characteristics and a large capacity is used for the ceramic single plate 11 has been described. The same can be applied when a porcelain substrate is used.

[0041]

[Effect of device]

 As described above in detail, in the chip-type three-terminal capacitor (1) according to the present invention, it is possible to form a capacitance between the capacitance forming electrodes or between the capacitance forming electrode and the ground connection electrode. Although it has a three-terminal structure, it can be made into a chip, and by forming a thin film layer, a desired capacitance can be obtained without making the shape of the capacitance forming electrode or the ground connection electrode thin. it can. As a result, noise can be effectively removed, and performance deterioration such as current capacity and soldering strength can be prevented. In addition, the structure can be simple and suitable for mass production, and the manufacturing cost can be reduced. In addition, it can be surface-mounted on an IC board, etc., and the step of forming a terminal insertion hole in the component on the side to be mounted can be eliminated. Can reduce the cost of electronic devices. Further, since the capacitance forming electrode, the end electrode, and the earth connection electrode can be formed afterwards, there is no need to perform simultaneous firing with the ceramic single plate, and the melting point of the electrode material is relatively low. Inexpensive Ag or the like can be used, and the manufacturing cost can be reduced.

Further, since the number of connecting portions of the ground connection electrode and the end electrode can be increased, the connection between them can be ensured, and the connection failure rate can be reduced, which is high. The reliability can be secured.

In the chip-type three-terminal capacitor (1) described above, an insulating layer is formed on at least one surface excluding the set of end surfaces on which the end electrodes are formed, except for the ground connection electrode portion. In this case, it is possible to obtain the same effect as that of the chip-type three-terminal capacitor (1), prevent moisture from entering the capacitance forming electrode, and oxidize or corrode the capacitance forming electrode. Can be prevented and high reliability can be secured. Moreover, since the end electrode and the ground connection electrode are exposed without being covered by the insulating layer, the end portion is not hindered by the insulating layer when surface-mounted on an IC substrate or the like, and the end portion is not covered. It is possible to connect an electrode and the earth connection electrode.

[Brief description of drawings]

FIG. 1 is a schematic view showing a first embodiment of a chip-type three-terminal capacitor according to the present invention, (a) is a perspective view, (b) is a plan view, and (c) is a bottom view.

2A and 2B are schematic diagrams showing a chip-type three-terminal capacitor according to a second embodiment, in which FIG. 2A is a perspective view and FIG.
(C) is a bottom view.

3A and 3B are schematic views showing a chip-type three-terminal capacitor according to Embodiment 3, where FIG. 3A is a perspective view and FIG. 3B is a plan view.
(C) is a bottom view.

4A and 4B are schematic views showing a chip-type three-terminal capacitor according to Embodiment 4, where FIG. 4A is a perspective view and FIG. 4B is a plan view.
(C) is a bottom view.

5A and 5B are schematic views showing a chip-type three-terminal capacitor according to a fifth embodiment, in which FIG. 5A is a perspective view and FIG.
(C) is a bottom view.

FIG. 6 is a front sectional view schematically showing a conventional comb-shaped three-terminal capacitor.

[Explanation of symbols]

 10 Chip Type 3 Terminal Capacitor 11 Ceramic Single Plate 11a, 11b Main Surface 11c, 11d, 11e, 11f End Face 12a, 13a Capacitance Forming Electrode 14a, 14b End Electrode 15a, 15b Ground Connection Electrode 16a Thin Film Layer

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location // H01G 4/255

Claims (2)

[Scope of utility model registration request] 1. At least one capacitance-forming electrode is formed on each of both main surfaces of a ceramic single plate, and at least two capacitance-forming electrodes connected to both ends of the capacitance-forming electrode formed on the one main surface. End electrodes are formed on one set of end faces, and at least one ground connection electrode connected to the capacitance forming electrode formed on the other main face is provided on one or both sides of the other set of end faces. A thin film layer having a predetermined shape and having a lower dielectric constant than that of the ceramic single plate is formed between the ceramic single plate and at least one capacitance forming electrode and / or the earth connecting electrode. A chip-type three-terminal capacitor characterized by being formed. 2. The chip type 3 according to claim 1, wherein an insulating layer is formed on at least one surface excluding the set of end surfaces on which the end electrodes are formed, excluding a ground connection electrode portion. Terminal capacitor.