JPH0736408A - Method for driving plasma display panel - Google Patents

Method for driving plasma display panel

Info

Publication number
JPH0736408A
JPH0736408A JP17840893A JP17840893A JPH0736408A JP H0736408 A JPH0736408 A JP H0736408A JP 17840893 A JP17840893 A JP 17840893A JP 17840893 A JP17840893 A JP 17840893A JP H0736408 A JPH0736408 A JP H0736408A
Authority
JP
Japan
Prior art keywords
pulse
erase
erase pulse
plasma display
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17840893A
Other languages
Japanese (ja)
Other versions
JP2616663B2 (en
Inventor
Yukiteru Izeki
幸輝 伊関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5178408A priority Critical patent/JP2616663B2/en
Publication of JPH0736408A publication Critical patent/JPH0736408A/en
Application granted granted Critical
Publication of JP2616663B2 publication Critical patent/JP2616663B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To stabilize erase operation by the driving of a plasma display panel. CONSTITUTION:In a method for driving a dot matrix display type AC plasma display panel having a memory function, an erase pulse for ending emission is constituted of a first part 7a of the erase pulse and a second part 7b of the erase pulse. The first part 7a of the erase pulse applies a pulse voltage having a pulse width narrower than that of the second part 7b of the erase pulse and high voltage so that weak discharge are surely started in all cells in the panel. The voltage of a discharge maintaining voltage or below is applied to the next second part 7b of the erase pulse.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、近年進展が著しいパー
ソナルコンピュータやオフィスワークステーション、な
いしは将来の発展が期待されている壁掛けテレビ等に用
いられる、いわゆるドットマトリクスタイプのメモリー
型ACプラズマディスプレイパネルの駆動装置の消去方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called dot matrix type memory type AC plasma display panel for use in personal computers, office workstations, wall-mounted televisions, etc., which are expected to grow in recent years. The present invention relates to a method of erasing a drive device.

【0002】[0002]

【従来の技術】従来のAC型プラズマディスプレイパネ
ルとしては図5に示す構造のものがある。図5におい
て、(A)は平面図、(B)は(A)のx−x’断面図
である。このプラズマディスプレイパネルは、ガラスよ
りなる第1絶縁基板11、同じくガラスよりなる第2絶
縁基板12、行電極13、列電極14、He,Xe等の
放電ガスが充填される放電ガス空間15、放電ガス空間
を確保するとともに画素を区切る隔壁16、放電ガスの
放電により発生する紫外光を可視光に変換する蛍光体1
7、行電極を覆う絶縁層18a、列電極を覆う絶縁層1
8b、絶縁体を放電より保護するMgO等よりなる保護
層19で構成されている。なお、図5(A)において、
参照番号20は画素を示している。蛍光体17を画素毎
に3色に塗り分ければ、カラー表示可能なプラズマディ
スプレイを得ることが出来る。
2. Description of the Related Art A conventional AC type plasma display panel has a structure shown in FIG. In FIG. 5, (A) is a plan view and (B) is a sectional view taken along line xx ′ of (A). This plasma display panel includes a first insulating substrate 11 made of glass, a second insulating substrate 12 also made of glass, a row electrode 13, a column electrode 14, a discharge gas space 15 filled with a discharge gas such as He and Xe, and a discharge. A partition wall 16 that secures a gas space and divides pixels, and a phosphor 1 that converts ultraviolet light generated by discharge of a discharge gas into visible light
7. Insulating layer 18a covering row electrodes, insulating layer 1 covering column electrodes
8b, a protective layer 19 made of MgO or the like for protecting the insulator from discharge. In addition, in FIG.
Reference numeral 20 indicates a pixel. A plasma display capable of color display can be obtained by separately applying the phosphor 17 to each pixel in three colors.

【0003】次に、プラズマディスプレイパネルの電極
のみに着目したものを図6に示す。図6において、21
はプラズマディスプレイパネル、22は第1絶縁基板1
1と第2絶縁基板12を張り合わせ、内部に放電ガスを
封入し気密にシールするシール部、Su 1 ,Su 2 ,・
・・、Su m - 1 ,Su m は維持電極、Sc 1
c2 ,・・・、Sc m - 1 ,Sc m は走査電極、これ
らを交互に合わせたものが行電極13である。また、D
1 ,D2 ,・・・、Dn - 1 ,Dn は列電極を示してい
る。
Next, FIG. 6 shows one in which only the electrodes of the plasma display panel are focused. In FIG. 6, 21
Is a plasma display panel, 22 is the first insulating substrate 1
A sealing part for bonding the first and second insulating substrates 12 together, sealing the discharge gas inside and hermetically sealing, S u 1 , S u 2 ,.
.., S um -1 , and S um are sustain electrodes, S c 1 ,
S c2 , ..., S cm -1 , S cm are scanning electrodes, and the row electrodes 13 are obtained by alternately combining these. Also, D
1 , D 2 , ..., D n -1 , D n represent column electrodes.

【0004】図7は、図5、図6に示したプラズマディ
スプレイパネルの駆動電圧波形、及び発光波形の一例を
示す図である。図7において、波形(A)は、維持電極
u 1 ,Su 2 ,・・・,Su m - 1 ,Su m に印加す
る電圧波形、波形(B)は、走査電極Sc 1 に印加する
電圧波形、波形(C)は、走査電極Sc 2 に印加する電
圧波形、波形(D)は、走査電極Sc m - 1 に印加する
電圧波形、波形(E)は、走査電極Sc m に印加する電
圧波形、波形(F)は、列電極Dj に印加する電圧波
形、波形(G)は、走査電極Sc 1 につながる画素の発
光波形、波形(H)は、走査電極Sc m につながる画素
の発光波形、を示している。維持電極Su 1 ,Su 2
・・・,Su m - 1 ,Su m には、維持パルス1を印加
する。また、走査電極Sc 1 ,Sc 2 ,・・・、S
c m - 1 ,Sc m には、これらの電極に共通した維持パ
ルス2のほかに、各走査電極に独立したタイミングで走
査パルス3と消去パスル4を線順次に印加している。各
列電極Djには、発光データがある場合は,データパル
ス5を走査パルス3に同期して印加する。
FIG. 7 is a diagram showing an example of drive voltage waveforms and light emission waveforms of the plasma display panel shown in FIGS. In FIG. 7, a waveform (A) is a voltage waveform applied to the sustain electrodes S u 1 , S u 2 , ..., S um −1 , S um , and a waveform (B) is applied to the scan electrode S c 1 . Waveform waveform (C) is a voltage waveform applied to scan electrode S c 2 , waveform (D) is a voltage waveform applied to scan electrode S cm −1 , and waveform (E) is a scan electrode S cm . The applied voltage waveform, waveform (F) is the voltage waveform applied to the column electrode D j , waveform (G) is the light emission waveform of the pixel connected to the scan electrode S c 1 , and waveform (H) is the scan electrode S cm . The light emission waveforms of connected pixels are shown. Sustain electrodes S u 1 , S u 2 ,
The sustain pulse 1 is applied to S um −1 and S um . Further, the scan electrodes S c 1 , S c 2 , ..., S
cm - 1 In, S cm, are applied in addition to the sustain pulse 2 common to these electrodes, the erase Pasuru 4 and scan pulse 3 line-sequentially in a separate timing to each scanning electrode. If there is light emission data, the data pulse 5 is applied to each column electrode Dj in synchronization with the scanning pulse 3.

【0005】図5、図6に示した構成のプラズマディス
プレイパネルにおいて、走査電極と列電極の間に同じタ
イミングで走査パルスとデータパルスを印加して書き込
み放電を行わせると、その後は隣あう維持電極と走査電
極の間で、維持パルス1と維持パルス2により維持放電
が持続される。このような機能はメモリー機能と呼ばれ
る。また、走査電極に印加される消去パルスは図8に示
すような細幅消去パルス、太線消去パルス(「プラズマ
ディスプレイ」、大脇健一、吉田良教編著、共立出版株
式会社:1983年11月15日初版1刷発行、90頁
に述べられている。)があり、必要において使い分けて
いる。
In the plasma display panel having the structure shown in FIGS. 5 and 6, when the scan pulse and the data pulse are applied between the scan electrode and the column electrode at the same timing to perform the write discharge, the adjacent discharge is maintained thereafter. The sustain discharge is sustained by sustain pulse 1 and sustain pulse 2 between the electrode and the scan electrode. Such a function is called a memory function. Further, the erase pulse applied to the scan electrodes is a narrow erase pulse and a thick line erase pulse as shown in FIG. The first edition, 1st edition, is described on page 90).

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図8に
示す消去パルスはそれぞれ欠点がある。図8(a)に示
す細幅消去パルス4aは固定した負荷に対する消去動作
マージンは大きいが、パルス形状及び電圧の変動には弱
い。例えば大画面化が進むと、表示画像によって消去す
るべきセル数が大きく変化する。この様な大きな負荷変
動は、印加パルス波形を大きく歪ませてしまう。特にパ
ルス幅を狭く制御して印加する必要のある細幅消去パル
スでは、波形歪の影響を受け易く、大画面パネルを表示
画面状態によらず均一に消去を行うことは困難であっ
た。また、図8(b)に示す太幅消去パルス4bは、低
電圧の幅広い印加パルスにより弱い放電を発生させるこ
とにより壁電荷を弱体化していくため、大画面化に伴う
消去すべきセル数の変動には影響を受けにくい。しか
し、太幅消去パルスは消去動作マージンが狭いため、大
画面でのセル間のバラツキによる消去電圧の変動には弱
く、消去動作マージン内の動作が困難となっていた。
However, each of the erase pulses shown in FIG. 8 has its drawbacks. The narrow erase pulse 4a shown in FIG. 8A has a large erase operation margin with respect to a fixed load, but is weak against variations in pulse shape and voltage. For example, as the screen size increases, the number of cells to be erased changes greatly depending on the displayed image. Such a large load fluctuation distorts the applied pulse waveform greatly. In particular, a narrow erase pulse that needs to be controlled with a narrow pulse width and is applied is easily affected by waveform distortion, and it is difficult to uniformly erase a large screen panel regardless of the display screen state. Further, the thick erase pulse 4b shown in FIG. 8B weakens the wall charges by generating weak discharge by a wide application pulse of low voltage. Less susceptible to fluctuations. However, since the wide erase pulse has a narrow erase operation margin, it is vulnerable to fluctuations in the erase voltage due to cell-to-cell variations in a large screen, making it difficult to operate within the erase operation margin.

【0007】[0007]

【課題を解決するための手段】本発明によれば、メモリ
ー機能を有するドットマトリクス表示型ACプラズマデ
ィスプレイパネルの駆動方法において、発光を終了する
ための消去パルスが少なくとも第1の部分、及び放電維
持電圧以下のパルス電圧波形からなる第2の部分からな
り、前記第1の部分が前記第2の部分より幅が狭く且つ
電圧の高いパルス電圧波形からなることを特徴とするプ
ラズマディスプレイパネルの駆動方法が得られる。
According to the present invention, in a method of driving a dot matrix display type AC plasma display panel having a memory function, at least a first portion of an erase pulse for ending light emission and sustaining of discharge are provided. A method for driving a plasma display panel, comprising a second portion having a pulse voltage waveform equal to or lower than a voltage, the first portion having a pulse voltage waveform having a narrower width and a higher voltage than the second portion. Is obtained.

【0008】[0008]

【実施例】プラズマディスプレイパネルとして、図5、
図6に示したものを用い、封入ガスにはHe−Xeを使
用した。また駆動波形は、消去パルス以外は図7に示し
た従来と同じ駆動波形を用いた。
EXAMPLE As a plasma display panel, as shown in FIG.
6 was used, and He-Xe was used as the filling gas. The drive waveform used was the same as the conventional drive waveform shown in FIG. 7, except for the erase pulse.

【0009】図1が本発明による消去パルスの第1の実
施例である。消去パルス7は消去パルスの第1の部分7
aと、消去パルスの第2の部分7bよりなる。消去パル
スの第1の部分7aは、パネル内の全セルが確実に弱放
電を開始できるようにするため、低電圧パルス7bの電
圧以外(150V)とした。しかし、パルス幅は100
〜500nsと狭いため、壁電荷を形成することはほと
んどない。
FIG. 1 shows a first embodiment of the erase pulse according to the present invention. The erase pulse 7 is the first part 7 of the erase pulse.
a and the second portion 7b of the erase pulse. The first portion 7a of the erase pulse was set to a voltage (150 V) other than the voltage of the low voltage pulse 7b in order to ensure that all cells in the panel can start weak discharge. However, the pulse width is 100
Since it is as narrow as ~ 500 ns, wall charges are hardly formed.

【0010】その後消去パルスの第1の部分7aが基準
電位に戻る前に、放電維持電圧以下の電圧(100V)
で、パルス幅を3μsとした消去パルスの第2の部分7
bを印加して、弱放電により壁電荷及び空間電荷の弱体
化を行い、消去放電とした。ここで示す消去パルスの第
2の部分のパルス幅については、300ns以上で消去
マージンが得られ実用に用いることができた。
After that, before the first portion 7a of the erase pulse returns to the reference potential, a voltage (100V) which is lower than the sustaining voltage.
Then, the second portion 7 of the erase pulse having a pulse width of 3 μs
By applying b, weakening of the wall charges and space charges by weak discharge was performed, resulting in erasing discharge. Regarding the pulse width of the second portion of the erase pulse shown here, an erase margin was obtained when it was 300 ns or more, and it could be used for practical purposes.

【0011】このように消去パルスの第1の部分7aと
消去パルスの第2の部分7bを連続して印加する駆動方
法により、消去パルスの第1の部分7aでは全セルにお
いて放電に寄与する活性粒子を数多く生成でき、消去パ
ルスの第2の部分7bにより消去のための弱放電を確実
に発生できた。従って、消去動作マージンが非常に向上
した。しかも、大画面パネルにおいても主となる消去放
電が消去パルスの第2の部分7bによる一種の太幅消去
であるため、負荷変動に強い。以上より安定な表示画像
を提供できるようになった。
By the driving method in which the first portion 7a of the erase pulse and the second portion 7b of the erase pulse are continuously applied in this way, in the first portion 7a of the erase pulse, the activity that contributes to discharge in all cells is activated. A large number of particles could be generated, and a weak discharge for erase could be reliably generated by the second portion 7b of the erase pulse. Therefore, the erase operation margin is greatly improved. Moreover, even in a large-screen panel, the main erasing discharge is a kind of wide-width erasing by the second portion 7b of the erasing pulse, so it is resistant to load fluctuations. As described above, a stable display image can be provided.

【0012】また、図2に本発明の消去パルスの第2の
実施例を示す。図2に示すように消去パルスの第1の部
分8aの終了後、これとは逆極性の消去パルスの第2の
部分8bを印加した。図1の実施例と同じく、消去パル
スの第1の部分8aでは全セルにおいて放電に寄与する
活性粒子を数多く生成でき、消去パルスの第2の部分8
bの弱放電を確実に発生できるので、消去動作マージン
が非常に向上した。
FIG. 2 shows a second embodiment of the erase pulse of the present invention. As shown in FIG. 2, after the end of the first portion 8a of the erase pulse, the second portion 8b of the erase pulse having the opposite polarity was applied. Similar to the embodiment of FIG. 1, the first portion 8a of the erase pulse can generate a large number of active particles that contribute to discharge in all cells, and the second portion 8 of the erase pulse can be generated.
Since the weak discharge of b can be reliably generated, the erase operation margin is significantly improved.

【0013】また、図3に本発明の消去パルスの第3の
実施例を示す。図1に示した消去パルスの第1の部分7
aと同じ消去パルスの第1の部分9a、消去パルスの第
2の部分7bと同じ消去パルスの第2の部分9bをまず
印加する。これに続いて、消去パルスの第2の部分9b
とともに消去パルスの第2の部分を構成する消去パルス
の第2の部分9cを印加した。消去パルス9cは、放電
開始電圧以下の電圧でパルス幅は300nsとした。こ
のように、消去パルスの第2の部分として、逆極性を持
つ電圧の低いパルスを組み合わせたことにより、消去パ
ルスの第2の部分9bで消去できなかった電荷を、消去
パルスの第2の部分9cにより再度弱放電させ弱体でき
た。これにより大きな負荷変動に対しても消去動作マー
ジンの安定度がされに増し、表示画像を安定に提供でき
るようになった。
FIG. 3 shows a third embodiment of the erase pulse of the present invention. The first part 7 of the erase pulse shown in FIG.
First, the first portion 9a of the same erase pulse as a and the second portion 9b of the same erase pulse as the second portion 7b of the erase pulse are applied. This is followed by a second part 9b of the erase pulse.
At the same time, the second portion 9c of the erase pulse, which constitutes the second portion of the erase pulse, was applied. The erase pulse 9c had a voltage equal to or lower than the discharge start voltage and a pulse width of 300 ns. As described above, by combining the pulse having the low polarity with the low voltage as the second portion of the erase pulse, the charges that cannot be erased in the second portion 9b of the erase pulse are transferred to the second portion of the erase pulse. With 9c, weak discharge was performed again, and weakened. As a result, the stability of the erasing operation margin is increased even with a large load change, and a display image can be stably provided.

【0014】また、図4に本発明の消去パルスの第4の
実施例を示す。図4は図1の場合と異なり、消去パルス
の第1の部分10aの終了後、一瞬基準電位に戻る。そ
の後、消去パルスの第1の部分10aによる放電での活
性粒子及び空間電荷が依存している状態の間に消去パル
スの第2の部分10bを印加した。消去機構としては図
1に示す実施例1と同様である。このように、消去パル
スの第2の部分の低電圧パルスに対するトリガー効果が
あれば、必ずしもトリガーパルスとなる消去パルスの第
1の部分と、低電圧消去パルスである消去パルスの第2
の部分が完全に連続していなくても良い。
FIG. 4 shows a fourth embodiment of the erase pulse of the present invention. Unlike FIG. 1, FIG. 4 returns to the reference potential momentarily after the end of the first portion 10a of the erase pulse. Then, the second portion 10b of the erase pulse was applied while the active particles and the space charge in the discharge by the first portion 10a of the erase pulse depended. The erasing mechanism is the same as that of the first embodiment shown in FIG. As described above, if there is a trigger effect for the low voltage pulse of the second portion of the erase pulse, the first portion of the erase pulse that is always the trigger pulse and the second portion of the erase pulse that is the low voltage erase pulse.
The part does not have to be completely continuous.

【0015】以上の実施例では、消去パルスを1組のみ
印加の場合を記述したが、消去パルスは複数組印加して
もよい。これにより大きな負荷変動に対する消去動作マ
ージンをより一層拡大できる。
In the above embodiments, the case where only one set of erase pulses is applied has been described, but a plurality of sets of erase pulses may be applied. As a result, the erase operation margin for large load fluctuations can be further expanded.

【0016】また、以上の実施例では、走査消去に本発
明の消去パルスを適用した例を述べたが、これに限ら
ず、本発明の消去パルスはパネル全面を一斉に消去する
ような場合にも適用できる。
Further, in the above embodiments, the example in which the erase pulse of the present invention is applied to the scan erase has been described, but the present invention is not limited to this, and the erase pulse of the present invention erases the entire panel all at once. Can also be applied.

【0017】また、以上の実施例では、図5、図6に示
した構造を持つAC面放電メモリー型プラズマディスプ
レイパネルを駆動した場合について述べたが、本発明
は、これに限らず、AC面放電型プラズマディスプレイ
パネルであれば適用できる。
In the above embodiments, the case where the AC surface discharge memory type plasma display panel having the structure shown in FIGS. 5 and 6 is driven has been described. However, the present invention is not limited to this, and the AC surface is not limited thereto. Any discharge type plasma display panel can be applied.

【0018】[0018]

【発明の効果】以上に述べたように、メモリー型ACプ
ラズマディスプレイパネルを駆動する場合、本発明の消
去パルスの第1の部分の導入によって消去放電のトリガ
となる弱放電を確実に発生させ、消去パルスの第2の部
分により消去動作を確実に行うことができるようになっ
た。従って、動画表示のように負荷変動が激しい場合
も、パネル全面に渡って安定に消去動作を行うことがで
きるため、表示品位が著しく向上した。
As described above, when the memory type AC plasma display panel is driven, the introduction of the first portion of the erase pulse of the present invention surely causes the weak discharge which triggers the erase discharge, The second portion of the erase pulse makes it possible to reliably perform the erase operation. Therefore, even in the case of a large load fluctuation such as a moving image display, the erase operation can be stably performed over the entire panel, and the display quality is remarkably improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の駆動方法の第1の実施例を示す消去パ
ルス波形である。
FIG. 1 is an erase pulse waveform showing a first embodiment of a driving method of the present invention.

【図2】本発明の駆動方法の第2の実施例を示す消去パ
ルス波形である。
FIG. 2 is an erase pulse waveform showing a second embodiment of the driving method of the present invention.

【図3】本発明の駆動方法の第3の実施例を示す消去パ
ルス波形である。
FIG. 3 is an erase pulse waveform showing a third embodiment of the driving method of the present invention.

【図4】本発明の駆動方法の第4の実施例を示す消去パ
スル波形である。
FIG. 4 is an erase pulse waveform showing a fourth embodiment of the driving method of the present invention.

【図5】プラズマディスプレイパネルの平面図と断面図
である。
FIG. 5 is a plan view and a sectional view of a plasma display panel.

【図6】電極配置に注目したプラズマディスプレイパネ
ルの構成図である。
FIG. 6 is a configuration diagram of a plasma display panel focusing on the electrode arrangement.

【図7】プラズマディスプレイパネルの駆動電圧波形、
及び発光波形を示す図である。
FIG. 7 is a driving voltage waveform of a plasma display panel,
It is a figure which shows and a light emission waveform.

【図8】プラズマディスプレイパネルにおける線幅消去
パルス、太幅消去パルスの説明図である。
FIG. 8 is an explanatory diagram of a line width erasing pulse and a wide width erasing pulse in the plasma display panel.

【符号の説明】[Explanation of symbols]

1、2 維持パルス 3 走査パスル 4、7〜10 消去パルス 4a 細幅消去パルス 4b 太幅消去パルス 5 データパルス 6 発光波形 11 第1絶縁基板 12 第2絶縁基板 13 行電極 14 列電極 15 放電ガス空間 16 隔壁 17 蛍光体 18a,18b 絶縁層 19 保護層 20 画素 21 プラズマディスプレイパネル 22 シール部 D1 ,D2 ,・・・,Dn - 1 ,Dn 列電極 Su 1 ,Sc 1 ,・・・,Su m ,Sc m 行電極 Su 1 ,Su 2 ,・・・,Su m - 1 ,Su m 維持電
極 Sc 1 ,Sc 2 ,・・・,Sc m - 1 ,Sc m 走査電
1, 2 Sustain pulse 3 Scan pulse 4, 7 to 10 Erase pulse 4a Narrow erase pulse 4b Wide erase pulse 5 Data pulse 6 Light emission waveform 11 First insulating substrate 12 Second insulating substrate 13 Row electrode 14 Column electrode 15 Discharge gas space 16 partition 17 phosphor 18a, 18b insulating layer 19 protective layer 20 pixel 21 plasma display panel 22 seal portion D 1, D 2, ···, D n - 1, D n column electrodes S u 1, S c 1, ..., S um , S cm row electrodes S u 1 , S u 2 , ..., S um -1 , S um sustain electrodes S c 1 , S c 2 , ..., S cm -1 , S cm scan electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 メモリー機能を有するドットマトリクス
表示型ACプラズマディスプレイパネルの駆動方法にお
いて、発光を終了するための消去パルスが少なくとも第
1の部分、及び放電維持電圧以下のパルス電圧波形から
なる第2の部分からなり、前記第1の部分が前記第2の
部分より幅が狭く且つ電圧の高いパルス電圧波形からな
ることを特徴とするプラズマディスプレイパネルの駆動
方法。
1. A method of driving a dot matrix display type AC plasma display panel having a memory function, wherein an erasing pulse for terminating light emission comprises at least a first portion and a pulse voltage waveform equal to or lower than a discharge sustaining voltage. The method for driving a plasma display panel according to claim 1, wherein the first portion has a pulse voltage waveform having a narrower width and a higher voltage than the second portion.
JP5178408A 1993-07-20 1993-07-20 Driving method of plasma display panel Expired - Fee Related JP2616663B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5178408A JP2616663B2 (en) 1993-07-20 1993-07-20 Driving method of plasma display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5178408A JP2616663B2 (en) 1993-07-20 1993-07-20 Driving method of plasma display panel

Publications (2)

Publication Number Publication Date
JPH0736408A true JPH0736408A (en) 1995-02-07
JP2616663B2 JP2616663B2 (en) 1997-06-04

Family

ID=16047972

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2616663B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6124849A (en) * 1997-01-28 2000-09-26 Nec Corporation Method of controlling alternating current plasma display panel for improving data write-in characteristics without sacrifice of durability
US6653993B1 (en) 1998-09-04 2003-11-25 Matsushita Electric Industrial Co., Ltd. Plasma display panel driving method and plasma display panel apparatus capable of displaying high-quality images with high luminous efficiency

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53101235A (en) * 1977-02-16 1978-09-04 Sharp Corp Memory erasion method for 3-layer structure thin film el element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53101235A (en) * 1977-02-16 1978-09-04 Sharp Corp Memory erasion method for 3-layer structure thin film el element

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US6653993B1 (en) 1998-09-04 2003-11-25 Matsushita Electric Industrial Co., Ltd. Plasma display panel driving method and plasma display panel apparatus capable of displaying high-quality images with high luminous efficiency
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