JPH0735880A - Time display employing display tube - Google Patents

Abstract

PURPOSE:To decrease the circuit area of a time display employing display tubes. CONSTITUTION:Counters 21-24 count the time and minute from the clock signal CK pulses inputted to the counter 21. The counts are outputted selectively from gates 41, 42 in response to control signals s5, s6 and decoded by segment decoders 43, 44. The segment decoders 43, 44 are driven by segment drivers 45, 46 to deliver the outputs to a display section 10. Light is emitted from the segments in the display section 10 in response to the outputs from the decoders 43, 44 and a time or a minute is displayed at the display section 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which is used in a digital timepiece for automobiles and the like and which displays a time using a display tube.

[0002]

2. Description of the Related Art FIG. 2 is a configuration block diagram showing a conventional display device. This display device is a display device of a 12-hour digital clock for an automobile, which displays a time with a 4-digit number using a display tube.
VFD) is used, and a drive unit 20 that counts the number of pulses of the clock signal CK and displays the time on the display tube based on the counted value. The display unit 10 includes a display area 11 for displaying the minutes of the time in two-digit numbers and a display area 12 for displaying the hours in the two-digit numbers.
The external appearance of the display unit 10 is shown in FIG. The display area 11 is a number di that displays the number of the 1st place.
The display area 12 has g1 and a digit dig2 for displaying the tenth digit, and the display area 12 has a digit dig3 for displaying the first digit of the hour and a digit dig4 for displaying the tenth digit. Each dig1 to dig3 is composed of seven segments a, b, c, d, e, f, g for representing individual numbers, and each of these segments is formed by VFD. di
g4 is composed of two segments b and c for representing numbers, and these segments b and c are formed of VFD.

The drive unit 20 includes a first decimal counter 21 that counts the pulses of the clock signal CK that is input every 60 seconds, a hexadecimal counter 22 that counts the carry signal of the counter 21, and a counter 22. It has a second decimal counter 23 for counting the carry signal and a binary counter 24 for counting the carry signal of the counter 23. Drive unit 2
0 also decodes the count values of the counters 21 to 23 to segment dig1 to segments a, b, c, d,
e, f, g emission signals sa, sb, sc, sd, s
Seven (7) segment decoders (hereinafter referred to as 7-segment decoders) that generate e, sf, and sg respectively 2
5, 26, 27 and the light emission signals sa of the 7-segment decoders 25, 26, 27 according to the control signals s1 to s3.
Gates 28, 29, 30 for turning on and off sg respectively
And a gate 31 for turning on and off the output signal of the counter 24 by the control signal s4. In the drive unit 20, the output terminals of the gates 28 to 31 are the gate 32
Is connected to the drive segment driver 33 via. The signal driven by the segment driver 33 is supplied to each of the numbers dig1 to dig4 on the display unit 10.
The gates 28 to 30 are composed of, for example, seven 2-input AND gates. The light emitting signals sa to s from the 7-segment decoder are connected to one input terminal of each AND gate.
Any one of g is input and the other input terminal is
Any one of the control signals s2 to s4 is input. The gate 31 has, for example, two AND gates, and each AND gate has one input terminal connected to the output of the counter 24 and the control signal s1 input to the other input terminal. The gate 32 has seven ORs
Each OR gate is composed of segments a to g.
7 segment decoder 25-
27 and the counter 24 respectively input.

Next, the operation of the display device shown in FIG. 2 will be described.
When the power is turned on, the power-on reset signal POR is input to the counters 21 to 24, and the counters 21 to 24 are input.
Is reset. The counter 21 counts the pulses of the clock signal CK input at a cycle of 60 seconds, and the count value is output from the four output terminals QA, QB, QC and QD. The signals output from the output terminals QA, QB, QC, and QD each have a bit weight, and the bit weights are respectively "H" if the signals from the terminals QA, QB, QC, and QD are in the "H" state. 1 ”“ 2 ”“ 4 ”
It represents "8" minutes. When the pulse of the carry signal is generated from the counter 21, the counter 22 counts the carry signal. The counter 22 operates similarly to the counter 21 and outputs the counting result for the tenth place. Similarly, the counters 23 and 24 perform the counting operation with respect to time.
For example, when the state is 1:00, the counters 21 and 21 are
The outputs of 2 and 24 are all "L", and only the output of the output terminal QA of the counter 23 is "H". When a pulse of the clock signal CK input at a cycle of 60 seconds is input to the counter 21, an output terminal Q of the counter 21 that counts minutes
The output signal from A becomes "H" and is output to the 7-segment decoder 25. Similarly, the counting results from the counters 22 and 23 are decoded by the 7-segment decoders 26 and 27, respectively, and the seven light emission signals sa, sb, and s are output.
c, sd, se, sf, sg are generated.

Light emission signal s from each 7-segment decoder
The output signals of a to sg and the counter 24 are supplied to the gate 28.
To 31. The gates 28 to 31 are opened and closed by the control signals s1, s2, s3, and s4 respectively inputted, and when the control signals s1 to s4 become "H", the signals sa to sg are transmitted via the gate 32 to the segment driver. It is output to 33. In the control signals s1 to s4, if the timings of "H" are sequentially deviated, the output signals of the 7-segment decoders 25, 26, 27 and the counter 24 are sequentially input to the segment driver 33. For example, when the control signal s1 is "H", the counter 2
The count value of 4 is transmitted to the segment driver 33.
When the control signal s2 is “H”, the count value of the counter 23 is transmitted to the segment decoder 33 via the 7-segment decoder 27. When the control signal s3 is "H",
The count value of the counter 22 is transmitted to the segment decoder via the 7-segment decoder 26. Control signal s4
Is “H”, the count value of the counter 21 is transmitted to the segment decoder 33 via the 7-segment decoder 25. The segment driver 33 drives the input signal and outputs it to the display 10, and the segments a, b, c, d, e, f, and g corresponding to the input signal emit light. The time is displayed on the display unit 10 by the above operation.

[0006]

However, the conventional display device has the following problems. As shown in FIG. 2, the 7-segment decoders 25 to 27 and the gate 2
The number of 8 to 32 is large, and for example, when integrated, the chip area of the drive unit 20 is large. This not only reduces the chip yield but also hinders the cost reduction of the semiconductor integrated circuit. SUMMARY OF THE INVENTION The present invention provides a display device that solves the problem that the above-mentioned conventional technique has, in that the circuit area of the integrated driving unit cannot be reduced.

[0007]

In order to solve the above-mentioned problems, the first invention is divided into i (where i is a positive integer) display areas, and each segment is a display tube for time display. In a display device configured with a display unit configured with, and a drive unit that counts the number of pulses of a clock signal and displays the time on the display tube of each segment based on the count value,
The driving unit counts the number of pulses of the clock signal, and the carry generated in the lower digit is sequentially propagated to the upper digit.
(Where j is a positive integer) counters are provided. Further, the display device includes i gates that select the output of a common radix counter among the j counters based on a control signal, and i segment decoders that decode the output of each gate. I segment drivers for driving the output of each segment decoder to display the display tubes of each segment. A second invention is the display device in the display device of the first invention, wherein the display section displays the segment of the display tube and the two-digit number for the minute display while displaying the two-digit number for the hour display. It consists of a tube segment, the j counters are a first decimal counter and a hexadecimal counter for counting minutes and a second counter for counting clocks.
It is composed of a decimal counter and a binary counter.
Further, the i gates in the display device include a first gate that selects an output of one of the first and second decimal counters based on the control signal, and the hexadecimal base based on the control signal. A second gate that selects the output of either the counter or the binary counter, and the i segment decoders include first and second decoders that decode the outputs of the first and second gates, respectively.
The segment decoder of FIG. 1 and the first and second segment drivers for driving the outputs of the i first and second segment decoders to display the display tubes of the respective segments.

[0008]

According to the first aspect of the invention, since the display device is configured as described above, the lower digit counter of the j counters counts the number of pulses of the input clock signal. The carry generated in the lower digit counter by the counting operation is sequentially propagated to the upper digit counter. The above operation is performed by each counter, and the number of pulses of the clock signal is counted by j counters. Among the j counters, the count value in the common radix counter is selected by the i gates based on the control signal and output. i
Segment decoders respectively decode the outputs from the i gates, and the signals generated as a result of the decoding are driven by the i segment drivers.
The output of the i segment drivers is transmitted to each segment of the display area to display the time. According to the second invention, the first decimal counter counts the pulses of the input clock signal. The hexadecimal counter counts the carry occurring in the first decimal counter of the lower digits, and the second decimal counter and the binary counter respectively count the lower digits of the hexadecimal counter and the second decimal counter. Count the carry of the decimal counter. The count values of the first and second decimal counters are selected by the first gate based on the control signal, and one of the count values is output from the first gate. The count value of the hexadecimal counter binary counter is selected by the second gate based on the control signal, and one of the count values is output from the second gate. First
The outputs of the first and second segment decoders are decoded by the first and second segment decoders, respectively, and the outputs of the first and second segment decoders are driven by the first and second segment drivers. The outputs of the first and second segment drivers are transmitted to the hour display segment or the minute display segment of the display section, and the display section displays the hour with a two-digit number or the minute display with a two-digit number. Therefore, the above problem can be solved.

[0009]

FIG. 1 is a block diagram showing the configuration of a display device according to an embodiment of the present invention. This display device is a display device of a 12-hour system digital timepiece for an automobile, which displays a time with a 4-digit number by using a display tube. The display unit 10 uses a VFD as a display tube and a clock signal CK. Drive unit 40 which counts the number of pulses and displays the time on the display tube of each segment based on the counted value. The display unit 10 includes a display area 11 for displaying the minutes of the time in two-digit numbers and a display area 1 for displaying the hours of the time in two-digit numbers.
It is composed of two. Similar to the conventional FIG. 3, the display area 1
2 has a digit dig1 that displays the number of the first place and a number dig2 that displays the number of the tenth place, and the display area 12 has a number 1
It has a number dig3 that displays the number of places and a number dig4 that displays the number of ten places. Each digit dig1 to di
g3 is the seven segments a, b, and
c, d, e, f, g, and each of these segments is formed by VFD. The number dig4 is composed of two segments b and c for representing numbers, and each of these segments is formed of VFD. Drive unit 40
Is similar to the conventional display device shown in FIG. 2, and is the first 10 for counting the pulses of the clock signal CK input at a period of 60 seconds.
A binary counter 21, a hexadecimal counter 22 for counting the carry signal of the counter 21, a second decimal counter 23 for counting the carry signal of the counter 22, and a binary counter for counting the carry signal of the counter 23. 24 and.
The counter 21 and the counter 22 compose a counter for displaying the minutes in the hexadecimal notation, and the counter 23 and the counter 24 constitute 12 counters.
It constitutes a counter for displaying the time of the progression. Minute and hour 1
The output terminals QA, QB, QC, QD of the counter 21 and the counter 23 for counting the number of orders are connected to the first gate 41, and the counter 2 for counting the number of tenths of minutes and hours.
2 and output terminals QA, QB, QC, Q of the counter 24
D are connected to the second gate 42, respectively. Control signals s5 and s6 for selection are further input to the first and second gates 41 and 42.

The driving unit 40 further includes first and second 7-segment decoders 43 and 44 for decoding the counting results input from the first and second gates, and first and second 7-segment decoders thereof. There are provided first and second segment drivers 45 and 46 for driving the outputs of 43 and 44 and outputting them to the segments of the display unit 10. The first gate 41 includes four multiplexers 41A, 41B, 41.
C and 41D respectively, and each multiplexer 41A,
41B, 41C, 41D are two 2-input ANs on the input side.
It has a D gate and one OR gate on the output side. The output signal from the output terminal QA of the counter 21 and the control signal s5 are input to the input side AND gate 41A-1 of the multiplexer 41A, and the output from the output terminal QA of the counter 23 is input to the input side AND gate 41A-2. The signal and the control signal s6 are input. AND gates 41A-1 and A
The output of the ND gate 41A-2 is the OR gate 41A-3.
And the multiplexer 41A selects and outputs the output of the counter 21 or the counter 23 according to the control signals s5 and s6. Multiplexer 41
41B- of the input side AND gates of B, 41C and 41D-
1, 41C-1 and 41D-1 have respective output signals from the output terminals QB, QC and QD of the counter 21 and a control signal s5.
41B- of the input side AND gate
2, 41C-2 and 41D-2 have output signals from the output terminals QB, QC and QD of the counter 23 and a control signal s6.
Is entered. The second gate 42 has the same structure as the first gate, and selects the outputs of the counter 22 and the counter 24 according to the control signals s5 and s6 and outputs them to the 7-segment decoder 44.

Next, the operation of the display device shown in FIG. 1 will be described.
FIG. 4 is a diagram for explaining the operation of the display device of FIG. 1. Time display, output waveforms of the counters 21 to 24, control signals s5 and s6, clock signal CK, and 7-segment decoders 43 and 44 are shown. The output waveform is shown. The counter 21 counts the pulses of the clock signal CK input at a cycle of 60 seconds, and the count value is four output terminals QA, Q.
It is output from B, QC and QD. Output terminals QA, QB,
The signals output from QC and QD have bit weights, and the bit weights are the terminals QA, QB, and
If the signals from QC and QD are in the "H" state, they represent "1", "2", "4", and "8", respectively. Counter 21
When a pulse of the carry signal is generated from the counter, the counter 22 counts the carry signal. The counter 22 operates similarly to the counter 21 and outputs the counting result for the tenth place. Similarly, the counters 23 and 24 perform the counting operation with respect to time. For example, when the state is 1:00,
As shown in FIG. 4, the outputs of the counters 21, 22, 24 are all "L", and only the output of the output terminal QA of the counter 23 is "H". When the counter 21 inputs a pulse of the clock signal CK issued in a cycle of 60 seconds while the time is displayed at 1:00, the waveform at the output terminal QA of the counter 21 becomes "H". At this time, the other output terminals QB, QC, QD of the counter 21 are in the "L" state, and the counters 22 to 24 maintain the previous state. The output signals of the counters 21 to 24 are supplied to the gate 41,
42 is transmitted.

When the control signal s5 input to the gates 41 and 42 is "H" and the control signal s6 is "L", the gates 41 and 42 select the output signals from the minute display counters 21 and 22. And output. 7 segment decoder 4
3 decodes the count value corresponding to the first digit of the minute display input from the counter 21, and displays the number di in the display unit 10.
The signals sa to sg for causing the segment for g1 to emit light are generated, and the 7-segment decoder 44 decodes the count value corresponding to the tenth digit of the minute display input from the counter 22, and the digit dig2 in the display unit 10 is displayed. The signals sa to sg for causing the light emitting segments to emit light are generated. The segment drivers 45 and 46 drive the light emission signals sa to sg from the 7 segment decoders 43 and 44 and output them to the display unit 10. When the control signal s6 is "H" and the control signal s5 is "L", the gates 41 and 42 are used for the hour display counter 2
The output signals from 3 and 24 are selected and output. The 7-segment decoder 43 decodes the count value corresponding to the first digit of the display when input from the counter 23, and the display unit 1
Signal s for emitting the segment for digit dig3 in 0
The signals a to sg are generated, the 7-segment decoder 44 decodes the count value corresponding to the tenth digit of the display when input from the counter 24, and the signal sa for making the segment for the digit dig4 in the display unit 10 emit light. Generate ~ sg. The light emission signals sa to sg of the 7-segment decoders 43 and 44 are driven by the segment drivers 45 and 46 and output to the display unit 10.

By repeating the above operation, that is, by repeating "L" and "H" of the control signals s5 and s6, the display device of FIG.
The hour and minute displays are alternately selected and displayed with 1/2 duty. By making the repetition operation of "L" and "H" of the control signals s5 and s6 faster, it seems that both hours and minutes are visually displayed. As described above, in the present embodiment, the outputs of the counters 21, 22, 23, 24 are directly input to the gates 41, 42 and the output of the counter is selected. The number of segment decoders and the number of gates can be reduced. Furthermore, since the outputs of the common-base number counters 21 and 23 are connected to the same gate 41 and selected, all the multiplexers in the gate 41 operate effectively. Therefore, the total number of multiplexers can be small. In addition,
The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) Each segment a, b, c, d for time display is V
Although the FD is used, the same action and effect can be obtained by using other display means such as a display discharge tube. (2) A 12-hour digital clock has a binary counter 24
It is also possible to make a 24-hour digital clock by using a ternary counter. (3) The number of stages of the counter may be increased to add a second display, am / pm display, or day display.

[0014]

As described in detail above, according to the first invention, the output of j counters is selected by i gates and then decoded by the segment decoder. And the number of gates can be reduced. As a result, for example, the chip area of the semiconductor integrated circuit can be reduced and the cost of the semiconductor integrated circuit can be reduced. Furthermore, since the chip area of the semiconductor integrated circuit can be reduced, the chip yield is increased. According to the second invention, the first gate selects the output of either the first or the second decimal counter based on the control signal, and the second gate is the hexadecimal counter or the binary counter. Select either output. As a result, the first and second gates can output only the counting result of the minute at one time, and the first and second gates can output only the counting result of the time at some time. Therefore, if the control signal is changed over time, the first
It is possible to realize a display device of a digital timepiece which alternately displays the hour and the minute with 1/2 duty while having the effect of the invention.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a display device according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram showing a conventional display device.

FIG. 3 is a diagram showing an appearance of a display unit.

FIG. 4 is a diagram for explaining the operation of the display device of FIG.

[Explanation of symbols]

10 display section 11, 12 minutes, hour display area 20, 40 drive section 21 first decimal counter 22 hexadecimal counter 23 second decimal counter 24 binary counter 41, 42 first and second gates 43, 44 1st, 2nd segment decoder 45, 46 1st, 2nd segment driver a, b, c, d, e, f, g segment s1-s6 control signal

Claims (2)

[Claims] 1. A display section which is divided into i (where i is a positive integer) display areas, each segment being composed of a display tube for time display, and counting the number of pulses of a clock signal In a display device configured with a drive unit that displays the time on the display tube of each segment based on a count value, the drive unit counts the number of pulses of the clock signal and sequentially carries the carry generated in the lower digit. Propagate to upper digit j
(Where j is a positive integer), i gates that select the output of the common radix counter among the j counters based on the control signal, and the outputs of the gates are decoded. A display device comprising: i segment decoders; and i segment drivers that drive the output of each segment decoder to display a display tube of each segment. 2. The display section comprises a segment of the display tube for displaying a two-digit number for hour display and a segment of the display tube for displaying a two-digit number for minute display, and the j The counter is composed of a first decimal counter and a hexadecimal counter for minute counting and a second decimal counter and a binary counter for clock number, and the i gates are based on the control signal. A first gate for selecting the output of either the first or second decimal counter and a second gate for selecting the output of either the hexadecimal counter or the binary counter based on the control signal. And the i segment decoders are composed of first and second segment decoders that decode the outputs of the first and second gates, respectively, and the i number of the first and second segment decoders Decor Wherein the output of the driving between the first and second segment driver for displaying the display tube of each segment, the display device according to claim 1, characterized by being configured.