JPS5821712B2 - densid cay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece that drives a matrix circuit display device in a time division manner.

The display device has one digit electrode common to each digit and a plurality of segment electrodes corresponding to the digit electrode.

As a drive circuit for driving this display device, for example, a static drive circuit that uses two voltage levels of "0" and "1" is widely known.
When a display element without directionality, such as a liquid crystal, is used as the matrix type display element, crosstalk occurs, making it impractical.

Therefore, when using a display element that does not have directivity as described above, for example, a drive voltage consisting of a combination of voltage levels "0" and "1" and a drive voltage whose voltage levels are "0" and "1" are used.
The crosstalk problem described above is solved by adopting a drive voltage consisting of a combination of "2" and "2".

However, when we look at the voltage and temperature characteristics of the luminance of the liquid crystal as a display element, we find that even if the voltage applied to the liquid crystal is constant, the luminance changes due to changes in the temperature of the liquid crystal itself. However, depending on the temperature conditions, sufficient luminance may not be obtained.

In order to avoid this, the applied voltage may be increased, but the above-mentioned crosstalk problem will occur again.

In addition, when using the static drive circuit described above, a decoder is required for each digit, which increases the number of connections with display elements, reduces the reliability of the connector part, and increases the size of the entire circuit. Therefore, it has the disadvantage that the manufacturing cost is also high.

Furthermore, since a direct current voltage is applied to the display element driven by the drive circuit, when liquid crystal is used as the display element, the life of the liquid crystal is relatively short.

Therefore, the present invention makes it possible to reduce the number of circuits and the number of connection terminals in a clock by time-divisionally driving a display device of a matrix circuit, and moreover, it is possible to reduce the number of circuits and connection terminals of a clock, and to maintain good performance without causing crosstalk even when driven at high voltage. The purpose is to propose an electronic timepiece that can display information, and its details will be explained below based on the illustrated embodiments.

1 to 5 show an embodiment of a display device according to the present invention, and reference numeral 1 denotes a power supply circuit, which has a battery as a power supply and drives electric circuits such as an oscillator and a frequency dividing circuit, which will be described later. A plurality of DC voltages having different voltage levels are generated: a voltage for driving the decoder, a voltage for driving the segment electrode drive circuit and a digit electrode drive circuit, which will be described later.

An oscillator 2 such as a crystal oscillator connected to a power supply circuit 1 generates a signal of a predetermined constant frequency, and its output signal is frequency-divided by a frequency dividing circuit 3.

The frequency divider circuit 3 generates an output signal of pulses every minute, which output signal is input to a minute counter 4 as a sexagesimal counter consisting of, for example, four binary counters (flip-flops).

The carry output from minute counter 4, i.e. 10 every minute/X? The pulse time (Rus) is input to a minute counter 5 consisting of a hexadecimal counter, and the carry output from the minute counter 5, that is, the time of one hourly pulse (Rus) is input to an hour counter 6 consisting of a decimal counter. be done.

A carry output from the hour counter 6, that is, a time pulse that occurs once every 10 hours, is input to an hour counter 7 consisting of a binary counter.

Minute counter 4, 10 minute counter 5, hour counter 6.
The count contents of the 10 o'clock counter 7 are inputted to the corresponding date circuits 8.9, 10, and 11, respectively.

From the frequency dividing circuit 2 shown in detail in FIG. 2, a divided signal n whose frequency has been divided 0 times, a divided signal n+1 whose frequency has been divided n+1 times, and a divided signal n whose frequency has been divided n+2 times as shown in FIG. 6 are output.
+2 are taken out, and they are the control signal generation circuit 12.
is input.

The control signal generation circuit 12 includes a two-man power AND gate 13 to which the branch signal n+1n+2 is applied, and a four-stage shift register 14 to which the output of the branch signal n and the AND date 13 is applied.

Each stage of the shift register 14 generates an output signal, and the output is the control signal φ of the control signal generation circuit 12.
1 to φ4, and has a waveform as shown in FIG.

The above control signal φ1. φ2, φ3, and φ4 are input to the date circuits 8 to 11'', respectively.

Therefore, the date circuits 8 to 11 correspond to the respective counters 4 to 11.
The outputs of the decoders 7 are controlled by the control signals φ1 to φ4, and are sequentially input to one decoder 15 at regular time intervals.

The decoder 15 converts the outputs of the counters 4 to 7 into seven command signals a1 to g1 and sends them to the segment electrode drive circuit 1.
6.

As shown in FIG. 3, the segment electrode drive circuit 16 is composed of a drive voltage generation section 17 and a switch circuit section 18.

The drive voltage generator 17 has four input terminals 19, 20, 21.
．． 22, the frequency divided signal n generated from the frequency dividing circuit 3 is applied to the input terminal 19, and the DC voltage of voltage level "3" generated by the power supply circuit 1 is applied to the billfold blade terminal 20. is applied to the input terminal 21, and a DC voltage of voltage level "1-2" also generated from the power supply circuit 1 is applied to the input terminal 22. DC voltage is applied.

The input terminal 19 is connected to the amplifier 23, and the input terminal 2
0 is connected to the power supply line of the amplifier 23, and an output terminal N is connected to the output side of the amplifier 23.

As shown in FIG. 6N, the first drive voltage A consisting of voltage levels "0" and "3" which are switched back and forth in synchronization with the branch signal n appears at the output terminal N.

The output side of the amplifier 23 is connected to one control terminal of the transmission date 24.25, and is connected to the other control terminal of the transmission date 24.25 via an inverter 26.

The input terminal 21 is connected to the input terminal of the transmission date 24, and the input terminal 22 is connected to the input terminal of the transmission gate 25.1. The output sides of the pair of transmission gates 424 and 25 are connected to output terminal B.

Therefore, the above transmission game 1-24.25
are alternately controlled to open and close by the first drive voltage A, so that the DC voltages applied to the input terminals 21 and 22 alternately appear at the output terminals.

That is, the output terminal is connected to the first terminal as shown in FIG. 6B.
The voltage levels “2” and “2” have an inverse relationship with the drive voltage N of
Q at which a second drive voltage consisting of repetitions of "1"appears; switch circuit section 1 connected to the output terminals N and B;
Reference numeral 8 designates seven switch circuits 27, 28, and 29 corresponding to the number of output terminals of the decoder 15.

30.31.32,33.

The switch circuit 27 is connected to the transmission gates 34, 3
The output terminal N is connected to the input side of the transmission gate 35, and the output terminal B is connected to the input side of the transmission gate 34.

One control terminal of the transmission gates 34 and 35 is, for example, the output terminal a of the decoder 15.

The other control terminal is connected to the output terminal a1 via the inverter 36, and the decoder 15
Opening/closing is controlled by a command signal a1 generated from the control panel.

The output sides of the transmission dates 34 and 35 are joined together and connected to the output terminal a.

Therefore, when the switch circuit 27 receives the high-level command signal a1 from the decoder 15, the transmission gate 35 enters the CN state, and the output terminal a receives voltage levels "0" and "3". On the other hand, when the low-level command signal a1 is input from the decoder 15, the transmission date 34 is turned on, so that the voltage levels "2" and "2" are output to the output terminal a. The second drive voltage B consisting of a repeating operation of "1" is output.

Similarly, the other switch circuits 28 to 33 have the same configuration as the switch circuit 27, and have the same functions, but each command signal b1 to g from the decoder 15 is
1, and their outputs are output to output terminals b-g, respectively.

Control signal φ1 generated from the control signal generation circuit 12
~φ4 is applied to the level shifter 37, amplified to voltage level "3", and input to the digit electrode drive circuit 38.

The digit electrode drive circuit 38 is composed of a drive voltage generation section 39 and a switch circuit section 40, as shown in FIG.

The drive voltage generator 39 has four input terminals 41, 42, 43.
44, the divided signal n generated from the frequency dividing circuit 3 is applied to the input terminal 19, and the DC voltage of voltage level "3" generated by the power supply circuit 1 is applied to the input terminal 42. is applied to the input terminal 43, a DC voltage of voltage level "2" also generated from the power supply circuit 1 is applied to the input terminal 44, and a DC voltage of voltage level "1" also generated from the power supply circuit 1 is applied to the input terminal 44. DC voltage is applied.

The input terminal 41 is connected to a pair of inverters 45 and 46, and the input terminal 42 is connected to the power supply line of the inverters 45 and 46.

An output terminal C is connected to the output side of the impark 46, and the output terminal C has voltage levels "3" and "3" having an inverse relationship with the first drive voltage N as shown in FIG. 6C. 0
” appears.

The output side of the inverter 45 is connected to one control terminal of a pair of transmission gates 47 and 48, and is connected to the other control terminal of the transmission gates 47 and 4B via an inverter 49.

The input terminal 43 is connected to the input terminal of the transmission date 47, the input terminal 44 is connected to the input terminal of the transmission date 48, and the output sides of the pair of transmission gates 47.4B are connected to the output terminal C. It is connected to the.

Therefore, since the transmission dates 47 and 48 are alternately controlled to open and close by the inverter 45, the DC voltages applied to the input terminals 43 and 44 alternately appear at the output terminals.

In other words, the output terminal is connected to the third terminal as shown in the sixth diagram.
The voltage levels "1" and "
A fourth drive voltage consisting of a reversal of 2'' appears.

The switch circuit unit 40 connected to the output terminals C and D receives the control signal φ1 outputted via the level shifter 37.
~Four switch circuits 50, 51, 52 corresponding to φ4
．． It has 53.

The switch circuit 50 is a transmission gate 54°5
The output terminal C is connected to the input side of the transmission gate 55, and the output terminal C is connected to the input side of the transmission gate 54.

One control terminal of the transmission gates 54 and 55 is connected to the level shifter 37, and the other control terminal is connected to the level shifter 37 via an inverter 56.
Opening/closing is controlled by a control signal φ1 amplified by .

The output sides of the transmission gates 54 and 55 are joined together and connected to the output terminal X1.

Therefore, the switch circuit 50 is connected to the level shifter 3.
When a high-level control signal φ1 is input from 7, the transmission gate 55 is turned on, and the output terminal X1 receives the third drive signal, which consists of switching between voltage levels "3" and "0". While the voltage C is output, when the low level control signal φ1 is input from the level shifter 37, the transmission gate 54 is turned on, so the output terminal The fourth driving voltage is output.

Similarly, the other switch circuits 51 to 53 have the same configuration as the switch circuit 50 and have the same functions, but each control signal φ2 from the level shifter 37
~φ4, and their outputs are output to output terminals X2 to X4, respectively.

The output terminals X1 to x4 of the digit electrode drive circuit 38 and the outputs a to g of the segment electrode drive circuit 16 are connected to a display section 57 of a matrix circuit having digit electrodes and a plurality of segment electrodes corresponding to the digit electrodes. Ru.

The display section 57 has a plurality of digit electrodes 58 to 6 as shown in FIG.
1, a set of seven segment electrodes a to g provided correspondingly, and a display element such as a liquid crystal (
(not shown).

A set of segment electrodes a to g are arranged to substantially form the number 8, and segment electrodes a, . . . are connected to output terminals a of the segment electrode drive circuit 16, respectively.

Similarly, segment electrodes b..., C..., d...,
e..., f...2g... are the output terminals of the pole drive circuit 16, c, d.

e, f, and g, respectively.

Further, the digit electrode 58 is connected to the output terminal X of the digit electrode drive circuit 38.
Connected to 1.

Similarly, each digit electrode 59, 60, 61 is connected to the digit electrode drive circuit 38.
are connected to output terminals X2, g, X3, and X4, respectively.

Note that the above-mentioned display elements such as liquid crystals have a threshold voltage slightly higher than the voltage "1", and when a reference voltage with a potential difference "1" is applied between the digit electrode and the segment electrode, a display phenomenon occurs. This rarely occurs, and a display phenomenon occurs when a voltage higher than the reference voltage is applied.

In this manner, the electronic timepiece of the present invention extracts control signals φ1 to φ4 corresponding to the number of digits on the display section 57 by the control signal generation circuit 12 connected to the division circuit 3, and uses these control signals to output the control signals φ1 to φ4. Date circuit 8 connected to ~7
~11 is time-divided and the output is sent to the coder 15.
Since the control signals φ1 to φ4 are applied to the digit electrode drive circuit 38 via the level shifter 37, the digit electrode drive circuit 16 and the segment electrode drive circuit 38 are It will be synchronized.

The numbers I and 2 are displayed on the display section 57 of the electronic clock configured in this way.
, 3, and 4, output terminals a1 to g1 of the decoder 15 generate command signals 81 to g1 with waveforms as shown in FIG. If the control signals φ1 to φ4 are sequentially generated at regular time intervals, the segment electrode drive circuit 16 generates the control signals φ1 to φ4 shown in FIG.

Voltage levels “1”, “2” and “3” as shown in ■
A drive signal a''g having a waveform consisting of a combination of "0" and "0" is generated, and the digit electrode drive circuit 38 generates drive signals X1 to X4 having waveforms as shown in FIG.

That is, the segment electrode drive circuit 16 and the digit electrode drive circuit 38 drive the segment electrodes aFdpegfy during time T1 as shown in FIG.
The second driving voltage consisting of voltage levels "1" and "2" is applied to g, and the first driving voltage consisting of voltage levels "3" and "0" is applied to the other segment electrodes s and c. At the same time, a third driving voltage consisting of voltage levels "0" and "3" is applied only to the digit electrode 58, and the other digit electrodes 59°60.6
1 is applied with a fourth drive voltage consisting of voltage levels "2" and "1".

Therefore, an alternating current voltage with a duty of 1/2 is applied to the digit electrodes 58 to 61 and segment electrodes a to g of the display section 57, and only between the digit electrode 58 and the corresponding segment electrodes a to c. A potential difference of "3" is generated, and a reference voltage with a potential difference of "1" is generated between the other electrodes.

Therefore, the segment electrodes corresponding to the digit electrodes 38,
A voltage equivalent to three times the reference voltage is applied only to c, and a display element such as a liquid crystal provided therebetween causes a display phenomenon and the number 1 is displayed brightly.

On the other hand, since the other display elements are applied with a reference voltage that is less than the threshold value of the display element, no display phenomenon occurs and a display with good contrast can be obtained.

Next, during time T2', the digit electrode 59 and its corresponding segment electrodes a, b, d,
e.

Since a voltage equivalent to three times the reference voltage is applied to g in an alternating current manner, the number 2 is displayed in the portion corresponding to the digit electrode 59.

Similarly, during time T3, the digit electrode 60 and the corresponding segment electrode a.

Since a voltage equivalent to three times the reference voltage is applied to b p Cy dy g, the number 3 is displayed, and during the next time T3, the digit electrode 61 and the corresponding segment electrodes S, e, f, A voltage equivalent to three times the reference voltage is applied to g, and the number 4 is displayed.

Note that the numbers displayed on the display device change as the outputs of the counters 4 to 7 change accordingly.

Although the electronic timepiece according to the present invention has been described above with reference to the drawings, the present invention is not limited to the above-mentioned embodiments. For example, the transmission date constituting the switch circuit may be composed of ordinary transistors. ,
Further, the number and arrangement of the segment electrodes of the display section 57 can be changed as appropriate to display characters other than numbers, and the voltage level applied to the digit electrodes and segment electrodes can also be changed as appropriate. Various changes and improvements can be made.

As shown above, the electronic timepiece according to the present invention time-divides the outputs of counters such as seconds, minutes, hours, etc. through a gate circuit controlled by a control signal generated from a control signal generation circuit 12 and sends them to a decoder at regular time intervals. Because it is configured to input, the number of circuits can be reduced without providing multiple decoders, the number of connection terminals can be reduced, and the reliability of the joint can be improved. While the digit electrode drive circuit is configured to control the opening and closing of the switch circuit using time-divided signals and selectively apply a reference voltage or a drive voltage higher than the reference voltage to the segment electrodes of the display section, the digit electrode drive circuit Since the switch circuit is configured to open and close using a control signal and selectively apply a reference voltage or a driving voltage higher than the reference voltage to the digit electrodes of the display section, the digit electrodes and segment electrodes in the non-display area During this time, a reference voltage that is slightly lower than the threshold of the display element such as a liquid crystal is applied in an alternating current manner, so that the display element does not cause any display phenomenon (cross), and does not cause any cross-reflection. Since a drive voltage that is sufficiently higher than the above reference voltage is applied between the digit electrode and the segment electrode in an alternating current manner, the display element always displays a display phenomenon with strong contrast without being affected by the ambient temperature. This has great practical effects, such as extending the life of the liquid crystal, and reducing power consumption because the circuit can be composed almost entirely of C, MOS, and IC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an electronic timepiece according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a segment electrode drive circuit forming a part of a control signal generation circuit forming a part of the electronic timepiece. 4 is a circuit diagram showing an embodiment of a digit electrode drive circuit forming a part of the electronic timepiece, and FIG. 5 is a circuit diagram showing an embodiment of a display section forming a part of the electronic timepiece. The figure shown,
6 and 7 are waveform diagrams for explaining the operation of the electronic timepiece according to the present invention. 1...Power supply circuit, 2...Level shifter, 3...Division circuit, 4, 5, 6, 7...
・Counter, 8,9゜10.11...Gate circuit, 12...Control signal generation circuit, 15...
... Decoder, 16 ... Segment electrode drive circuit, 37 ... Level shifter, 38 ...
Digit electrode drive circuit, 57...display section.

Claims (1)

[Claims] In an electronic watch equipped with a display section of a matrix circuit having a one-digit electrode and a plurality of corresponding segment electrodes, there is a counter into which pulses are input for a predetermined period of time, and the output of the counter is time-divided to display a predetermined period of time. a gate circuit that transmits information at intervals; a control signal generation circuit that generates a control signal to control the output of the gate circuit; and an output of the gate circuit controlled by the control signal generation circuit that is input to the segment electrode. A decoder that generates a corresponding command signal, a power supply circuit that has a DC power supply and generates a plurality of DC voltages each having a predetermined voltage level, and a power supply circuit that inputs a plurality of voltages generated from the power supply circuit and generates a voltage. A drive voltage generator converts the drive voltage into a first drive voltage and a second drive voltage of different levels, and a pair of drive voltages generated from the drive voltage generator are selectively applied to the segment electrodes according to a command signal from the decoder. a segment electrode drive circuit comprising a switch circuit for supplying voltages; a level shifter for level-shifting a control signal generated from the control signal generating section to one voltage generated from the power supply circuit; A drive voltage generation section inputs the voltage and converts it into a third drive voltage and a fourth drive voltage each having a different voltage level, and a pair of drive voltages generated from this drive voltage generation section is selectively selected by the output of the level shifter. and a switch circuit that supplies the digit electrodes to the digit electrodes, and the second drive voltage and the fourth drive voltage are applied between the digit electrodes and unselected electrodes among the plurality of segment electrodes. A reference voltage is applied between the selected digit electrode and the segment electrode, while the first drive voltage and the third drive voltage are applied between the selected electrode and the reference voltage is applied between the digit electrode and the segment electrode. An electronic clock characterized by the fact that a high voltage is applied in an alternating current manner.