JPH0734431B2 - Method for manufacturing semiconductor crystal layer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for producing a semiconductor crystal layer. More specifically, it relates to a method for solid phase epitaxial growth of a single crystal semiconductor layer by causing a solid phase-solid phase transition of an amorphous semiconductor layer formed on an insulating layer.

[Background Art and Problems to be Solved by the Invention]

A lot of research is currently underway to improve the performance of integrated circuits, but from the viewpoint of materials, compound semiconductors and SOI (Silicon on Insulator) on the insulating film are being researched.

Especially, in the latter (SOI), a highly integrated and high-speed integrated circuit can be realized because the integrated circuit manufacturing process in the current silicon technology can be used almost as it is, the element isolation is easy, and the parasitic capacitance is small. be able to. In addition, SOI is an essential structure for the fabrication of three-dimensional integrated circuits and is considered to be a promising candidate for next-generation integrated circuits. Moreover, since SOI by solid phase epitaxial growth does not need to heat silicon above its melting point, it is a low manufacturing temperature and energy-saving, and is suitable for the fabrication of three-dimensional integrated circuits and large-area liquid crystal displays that want to avoid high temperature processes as much as possible. It is indispensable for realizing a drive circuit. Therefore, the results of SOI research by solid-phase epitaxial growth are strongly expected.

However, in the conventional simple furnace annealing method that performs uniform heating, the lateral solid phase epitaxial growth distance does not exceed 100 μm, and a technique for forming a high-quality and large-area silicon single crystal thin film is desired. There is.

When trying to obtain a large area of single crystal silicon (c-Si) by the solid-phase epitaxial growth method, the obstacle is polycrystallization. That is, a thin film of amorphous silicon (a-Si) is formed on an insulating layer such as a silicon oxide film (SiO ₂ ),
When this amorphous silicon is thermally annealed, the single crystal silicon layer gradually undergoes solid phase epitaxial growth from the single crystal seeding portion adjacent to the amorphous silicon. A crystal nucleus is generated, and this crystal nucleus grows. Then, since the crystal orientation of the crystal nuclei is random, the crystal nuclei become polycrystalline, and a large lateral solid phase epitaxial growth distance cannot be obtained due to the random nucleation.

Therefore, the present inventors continued basic research on the crystallization process of amorphous silicon in order to obtain a high-quality, large-area silicon polycrystalline thin film. As a result, random nucleation does not occur immediately when amorphous silicon is heated,
It was found that there is a time delay called an induction time (latency time) before crystallization occurs mainly in the nucleus. Therefore, in order to facilitate understanding of the present invention, the method and results of this basic research will be described below.

First, a large number of samples were prepared by forming a thin film of amorphous silicon on the surface of a quartz glass substrate. When this sample is placed in an annealing furnace and annealed, random microcrystalline nuclei are generated in the amorphous phase as described above, and this grows to form a polycrystalline phase. In order to know the state of generation of crystal nuclei, the inventors of the present invention examined various changes in the annealing temperature and the annealing time for the above samples, and examined whether or not crystallization (phase change) occurred in the thin film. Here, as a technique for forming an amorphous thin film, plasma is used.
The CVD (vapor phase chemical reaction) method, the CVD method, the sputtering method, etc. were used. In order to crystallize amorphous silicon, isothermal annealing (Isothermal
Annealing).

The sample thus anisothermally annealed was inspected for crystallization by X-ray diffraction. In addition, the samples with insufficient X-ray diffraction were inspected by Raman scattering, and the results of Raman scattering were prioritized. In X-ray diffraction, (11
1) Since the diffraction line due to the plane appears most prominently, we focused on the intensity of this diffraction line. About Raman scattering, about 520 cm
^The peak appearing at ^-1 was used as a standard for crystallization of the amorphous phase.
Part of this result is shown in the graph of FIG. This is a thin film of amorphous silicon formed by plasma CVD method.
It shows the results of measurement by X-ray diffraction and Raman scattering for a sample that has been subjected to an isothermal annealing treatment at an annealing temperature in the range of ° C to 680 ° C.

In each of FIGS. 6 (a) to 6 (d), the vertical axis represents the X-ray intensity, the horizontal axis represents the annealing time, and the ∘ mark indicates the X-ray measurement result, and the ∘ mark and the dotted circle Marks are plots of Raman scattering measurement results. However, ◎
Indicates that crystal peaks did not appear in both X-ray measurement and Raman scattering measurement, and the results of both were in agreement, whereas the dotted circles indicate that the results of both were inconsistent, and therefore Raman scattering This is a plot with priority given to the result of. Here, the X-ray intensity in the (111) direction is zero on the side where the annealing time is shorter than the shaded region, because this is in the amorphous phase and does not scatter X-rays strongly in a specific direction. Is. Further, on the side where the annealing time is longer than the shaded region, X-ray scattering in the (111) direction occurs due to crystallization. That is, when a thin film of amorphous silicon is inserted into a high temperature annealing furnace, it does not crystallize immediately, but remains in an amorphous state (amorphous phase) for a long time after reaching a certain temperature (annealing temperature). Stays in
It can be seen that crystallization is progressing rapidly after a certain time has passed. As a result, it can be concluded that there is a latency in the crystallization process of the amorphous phase, and the inventors named this latency the induction time t _d for nucleation.

Induction time t _d is in FIG. 6 (a) ~ hatched region in (d), induction time t _d As apparent from the figure has changed by the annealing temperature T.
Therefore, it is taken ordinate in logarithmic scale the induction time t _d the width of the shaded area as a measurement error, which the 1 / T was plotted the relation between t _d and 1 / T for the horizontal axis is Figure 7. As a result, the relationship between the induction time t _d and 1 / T is represented by a straight line as shown in Fig. 7. By expressing this with a formula, t _d = τ _o exp (E _a / kT) …… is obtained. To be Here, E _a is the activation energy of the induction time, τ _o is a constant that changes depending on the material of the semiconductor thin film layer and the thin film forming technology, and corresponds to the induction time at infinite temperature. _o can be determined empirically. It should be noted that although the result of forming the thin film layer of amorphous silicon by the CVD method or the sputtering method is not shown, the result is qualitatively the same although there is a difference in the quantity.

The mechanism in the above crystallization process can be interpreted as follows. When an amorphous layer is heated at an appropriate temperature, microcrystalline nuclei are generated, and these microcrystalline nuclei grow to form a polycrystalline layer. The driving force for this phenomenon is the amorphous phase and the crystalline phase. This is due to the difference in free energy between the phases. That is, since the microcrystalline nuclei have large surface free energy, there is a probability that they will return to a disordered amorphous state once they are generated, and microcrystalline nuclei are generated in an amorphous layer placed at a certain temperature. We are reducing it. Therefore, it is expected that a threshold exists in the three-dimensional size of the microcrystal nuclei in order that the microcrystal nuclei exist stably and grow. Then, this threshold value causes an induction time or a time delay in the production of a polycrystalline phase. Here, consider the temperature dependence of the induction time. The generation rate of microcrystalline nuclei depends on temperature, and it is considered that the higher the temperature, the greater the generation rate, and the probability that the microcrystalline nuclei reach the threshold for achieving stable growth also depends on temperature. It is considered that the probability also increases. Moreover, it is appropriate to consider that both of these processes have activation-type temperature dependence. Therefore, it is considered that the higher the temperature is, the shorter the induction time tends to be, and its temperature dependence is also expected to be the activation type proportional to exp (E _a / kT), as shown in Fig. 7. The summarized experimental results and formulas are considered to be valid results.

Therefore, the present invention has been made based on the above findings (particularly, when the amorphous phase is heated, a finite induction time needs to elapse before random nucleation occurs). The object of the invention is to provide a method capable of solid phase epitaxial growth of a large-area polycrystalline semiconductor layer by suppressing polycrystallization due to random nucleus growth.

[Means for Solving the Problems]

Therefore, the method for producing a semiconductor crystal layer of the present invention, an amorphous semiconductor layer is formed on the insulating layer, and the amorphous semiconductor layer is formed within a time shorter than the induction time for random nucleation. Solid phase (amorphous semiconductor) -solid phase by increasing the temperature from the initial temperature to the solid phase epitaxial set temperature, annealing under temperature conditions having a steep rising temperature gradient, and relatively moving the annealing region. It is characterized in that a phase transition between (single crystal semiconductor) is caused to cause solid phase epitaxial growth of the single crystal semiconductor layer on the insulating layer.

The steep temperature gradient κ may be determined so as to satisfy the following equation.

Where T ₁ is the initial temperature, T _ep is the solid phase epitaxial set temperature, E _a is the activation energy of the induction time,
k is a Boltzmann constant, T is an integration constant, V is a moving speed of the amorphous semiconductor layer, and τ _o is a constant, which is an induction time until generation of crystal nuclei at infinite temperature.

In addition, a metal layer for seeding is provided on a part of the insulating layer or the amorphous semiconductor layer, and a single crystal semiconductor is formed from a eutectic region formed between the metal layer and the amorphous semiconductor layer which are adjacent to each other. The layers may be solid phase epitaxially grown.

[Action]

In the present invention, the amorphous semiconductor layer is moved and annealed under the temperature condition having a steep rising temperature gradient, and the single crystal semiconductor layer is solid-phase epitaxially grown. It can be set so that random nucleation does not occur until the phase epitaxial set temperature is reached, and solid phase epitaxial growth over a wide area becomes possible. That is, the amorphous semiconductor layer is moved and annealed under a temperature condition having a steep rising temperature gradient, so that the initial temperature of the low temperature is changed to the epitaxial set temperature within a time shorter than the induction time for random nucleation. It is possible to raise the temperature all at once, and therefore, before random nucleation occurs in the amorphous semiconductor layer, the crystal plane with the highest crystallization rate is amorphous from the already crystallized region by solid phase epitaxial growth. Since it penetrates into the semiconductor layer, it is possible to suppress the generation of the polycrystalline layer and grow the single crystal semiconductor layer. By suppressing the generation of the polycrystalline phase in this manner, a large-area single crystal semiconductor layer can be obtained.

Here, the steep rising temperature gradient κ is expressed by the following equation when the temperature change is linearly approximated. (Here, L is the distance from the end of the region changing from the initial temperature T _i to the solid-phase epitaxial set temperature T _ep .), Which is referred to as the moving speed V. By setting so as to satisfy the above equation in relation to the above, the amorphous semiconductor layer can reach the solid phase epitaxial set temperature within a time shorter than the induction time. Therefore, the lower limit of the required rising temperature gradient can be quantified by the equation.

Further, by forming a seeding metal layer on the insulating layer, a eutectic region serving as a seeding portion can be formed to realize stable solid phase epitaxial growth.

〔Example〕

 An embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

(Sample) First, the prepared sample 13 is an amorphous silicon film 2 (an amorphous semiconductor in this example) on the surface of a quartz glass substrate 1 (insulating layer in this example) by a plasma CVD method. As shown in FIG. 1, a thin gold film [Au] 4 for seeding (metal layer in this embodiment) is further formed on one end of the amorphous silicon film 2 as shown in FIG. It is vapor-deposited. The sample 13 does not have the gold film 4 as a seed crystal, and when the front edge of the sample 13 is heated to be polycrystallized, it is covered with a crystal having a crystal orientation with the highest growth rate. Although it is possible to obtain a single crystal layer having a large area, the reproducibility of single crystal growth can be improved by forming the gold film 4 adjacent to the amorphous silicon film 2 as described above. It was That is, the amorphous silicon film 2
This is because the Si-Au eutectic region can be formed in the adjacent region at a low temperature of 377 ° C. by providing the gold film 4 adjacent to the seed film, so that the existence of the seed crystal can be ensured. The metal layer is not limited to the gold layer, but an aluminum layer or the like may be used.

(Lateral Annealing Furnace) FIG. 2 is a schematic sectional view of a lateral annealing furnace for performing lateral solid phase epitaxial growth (LSPE). The lateral annealing furnace 5 includes a sample cooling stage 6, a sample support stage 7, a sample fine feed device 8,
It comprises a spot-shaped local heating device 9 and a linear local heating device 10.

The sample cooling stage 6 and the sample support stage 7 support the sample 13 horizontally and smoothly move it.
In each case, a plate made of a material having a high thermal conductivity, for example, a copper plate or the like is used to finish the upper surface to be smooth. Both sample stages 6 and 7 are horizontally supported by struts 11 and 12, respectively, and their tips are closely opposed to each other so that their upper surfaces are flush with each other at the same height. Stage 6,
A small gap 14 is formed between 7 along almost the entire width. Further, the sample cooling stage 6 is provided with a structure (not shown) for circulating water inside or on the lower surface and is cooled by a water cooling method.

The fine sample feed device 8 includes a push rod 15 for pushing the rear end of the sample 13 to move the sample 13, and a push rod 15.
The sample cooling stage 6 comprises a feeder main body 16 for moving the 15 horizontally and extremely precisely at a constant speed.
It is installed on the side. Then, the sample 13 placed on the sample cooling stage 6 and the sample supporting stage 7 is moved at a constant speed from the sample cooling stage 6 to the sample supporting stage 7 side by the fine sample moving device 8.

The spot-shaped local heating device 9 is arranged above the sample stages 6 and 7, and is provided with a laser oscillator 17 and an optical system 18 for focusing, as shown in FIG. 3 (a). Then, as shown in FIGS. 1 and 3 (a), the laser beam 19 emitted from the laser oscillator 17 is narrowed down by the optical system 18, and is placed on the sample stage 6, 7 at the position of the small gap 14. It is adjusted so that a point-like focus is formed on almost the center of the upper surface of the sample 13 placed on. The laser oscillator 17 used here is
A semiconductor laser with a wavelength of 800 nm and an output of 100 mW. In the embodiment, a semiconductor laser is used as the spot-shaped local heating device 9, but other lasers may be used, and it is also conceivable to use an ion beam, an electron beam, or an optical system in which the light of a lamp is narrowed down. To be The position of the laser beam 19 is fixed, and the sample 13 is not scanned in the width direction.

The linear local heating device 10 is an elliptical reflection furnace having an elliptical reflection surface 22.
A linear heat source 21 is arranged inside 20. This elliptical reflection furnace 20 is obtained by subjecting an elliptical reflection surface 22 to a mirror treatment by gold plating, and the elliptical reflection surface 22 is formed so that its cross section draws an ellipse (thus, three-dimensionally an elliptical tubular body). , The linear heat source 21 is arranged at the focal point below the elliptical reflecting surface 22. Further, the elliptical reflection surface 22 is opened with its upper part cut off, and the elliptical reflection furnace 20 is installed so that the sample stages 6 and 7 are located in the upper opening. Furthermore, a small gap 14 between the sample stages 6 and 7 is located in the center of the elliptical reflection furnace 20, and the focus on the upper side of the elliptical reflection surface 22 is that of the sample 13 placed on the sample stages 6 and 7. The height is adjusted to be the same as that of the amorphous semiconductor layer (however, when the sample 13 is placed so that the light beam from the linear heat source 21 passes through the quartz glass substrate 1 and hits the amorphous semiconductor layer). Takes into consideration the refraction of light by the quartz glass substrate 1.). Therefore, the heat source 24 emitted from the linear heat source 21 is reflected by the elliptical reflecting surface 22 and collected by the amorphous semiconductor layer of the sample 13. Further, as the linear heat source 21, a halogen lamp, an infrared lamp, a canthal ribbon heater, or the like can be used, but a halogen lamp is particularly preferable. As the linear local heating device 10, a device in which only a Kanthal ribbon heater or the like is arranged close to the sample cooling stage 6 and the sample support stage 7 is possible, but the elliptical reflection furnace 20 is used as described above. As a result, the reproducibility of single crystal growth could be improved.

(Method of Implementation and Result) Next, a method of lateral solid phase epitaxial growth using the above-mentioned lateral annealing furnace will be described. First, place the sample 1 on the sample stages 6 and 7 in an atmosphere such as nitrogen gas.
3 is placed, the spot heating device 9 and the linear heating device 10
The region where the gold layer 4 and the amorphous silicon film 2 overlap is heated by. Thus, the eutectic region of gold and silicon 23
Are formed, and this eutectic region 23 becomes a seed crystal for growing a single crystal. Then, while heating the surface of the sample 13 by the spot-shaped local heating device 9 and the linear local heating device 10, the sample 13 is pushed by the sample fine movement feeding device 8 and moved horizontally at a constant speed V. Then, as the sample 13 moves, the sample
The annealing region of 13 moves, and the single crystal silicon film 3 (single crystal semiconductor layer in this embodiment) on the surface of the sample 13 gradually solid-phase epitaxially grows from the eutectic region 23. Looking at this with a particular cross section of sample 13,
First, on the sample cooling stage 6, the sample 13 has been cooled to the initial temperature T _i , and when it goes beyond the end of the sample cooling stage 6 and comes out above the small gap 14, it is rapidly heated by the linear local heating device 10 from below. It Therefore, the sample 13 is rapidly heated up to the solid phase epitaxial set temperature T _ep under the rising temperature gradient. Further, since the central portion is heated by the spot-shaped local heating device 9 from above, annealing is performed under a steeper rising temperature gradient.
FIG. 3B shows the temperature change along the length direction of the sample 13. In the figure (b), the horizontal axis is the distance measured along the sample, the vertical axis is the temperature, and the a on the horizontal axis corresponds to the end of the sample cooling stage 9. In this graph, the solid line B represents the state of being cooled by the sample cooling stage 6, the broken line D represents the state of heating by the linear local heating device 10, and the two-dot chain line E is the spot local heating. The heating state by the device 9 is shown, and the solid line F shows the gradually cooled state on the sample support stage 7 side. The heating curve D by the linear local heating device 10 has a steep rising characteristic, but rises relatively broadly as compared with the heating region by the spot local heating device 9. Therefore, when the heating by the spot-shaped local heating device 9 is superimposed on the heating by the linear local heating device 10, a steeper rising temperature gradient is obtained as indicated by the solid line C in FIG. 3 (b). . Thus, by moving the sample 13 and annealing the amorphous silicon film 2 on the surface under the temperature condition of the steep rising temperature gradient, the temperature can be quickly raised to the solid phase epitaxial set temperature. Then, when the temperature of the amorphous silicon film 2 is raised to the solid phase epitaxial set temperature within a time shorter than the induction time for nucleation, random nucleation occurs because the induction time has not yet passed. On the other hand, on the other hand, the amorphous silicon film 2 which has reached the solid-phase epitaxial set temperature, the single-crystal silicon film 3 is generated by the solid-phase epitaxial growth from the eutectic region. As a result, a large area single crystal silicon film 3 containing no polycrystalline silicon is obtained. FIG. 4 schematically shows the sample 13 thus solid-phase epitaxially grown. Here, the rightmost part is the vapor-deposited gold layer 4, and this part was first heated to form a eutectic at 377 ° C., but the film thickness was thick and gold elements above the solid solution limit remained. The area is opaque due to Further, the left end portion is the amorphous silicon film 2 which is not annealed, and remains unchanged reddish black. The central portion is a single crystal silicon film 3 that has been single-crystallized, and this portion is light yellow and transparent because it has a smaller absorption coefficient in visible light than the amorphous phase. The length s of this portion is the lateral solid phase epitaxial growth distance, and the experimental result was about 2 mm. This value of 2 mm is much larger than the conventional value of 44 μm (a two-digit large number), but it should be extended to the cm order by improving the temperature control accuracy of the lateral annealing furnace. It can be expected that a wafer size wafer can be manufactured.

Further, both side portions of the amorphous silicon film 2 which are not irradiated with the spot-shaped local heating device 9 are annealed under the temperature condition having a steep rising temperature gradient as shown by a broken line D in FIG. 3 (b). However, the solid-phase epitaxial growth is further dragged by the central portion where the lateral solid-phase epitaxial growth rate is large on both sides. That is, since the central portion is heated by the spot-shaped local heating device 9 and has a temperature higher than those on both sides, it has a large lateral solid phase epitaxial growth rate,
This central portion serves as a seed crystal and grows so that both side portions are dragged. Therefore, the left edge of the crystalline silicon film 3 looks like a dogleg as shown in FIG. Therefore, if the moving speed of the sample 13 is changed,
It is assumed that the angle of this dogleg shape also changes.

Annealing temperature is below the melting point of silicon, 80 ℃ ~ 900
A temperature of ° C is considered suitable, but in the above example about 78
Presumed to be annealed at 0 ° C. The solid-phase epitaxial growth rate V _ep of about 1000 μm / h could be achieved.

(First Conditional Expression) Next, an expression for estimating the magnitude of the required rising temperature gradient is given. That is, assuming that the temperature of the sample 13 is raised from the initial temperature T _i to the solid phase epitaxial set temperature T _ep with the temperature gradient κ, the temperature gradient κ at this time is related to the moving speed V of the sample 13, Must satisfy the formula.

Next, we prove this formula. First, it is assumed that the sample temperature linearly rises from the initial temperature T _i to the solid-phase epitaxial set temperature T _ep while the sample 13 moves the distance L.
Let's approximate the temperature gradient linearly as shown by the broken line in the figure. temperature
Temperature T _x at the position of distance x from the position of the T _i is expressed by _{T x = κx + T i ......} . Where the temperature gradient κ is It is represented by.

Further, the section L is divided into n equal sections ξ (ξ = 1,2, ..., n), and a straight line connecting T _i and T _ep between them is approximated by a stepped polygonal line as shown in FIG. To do. Therefore, the width Δx of each minute section ξ, the time Δ that the sample 13 stays in each minute section ξ
t and the temperature increment ΔT for each minute section are given by the following equations.

Δx = L / n Δt = Δx / V ΔT = (T _ep −T _i ) / n When Δx and n are deleted from these three formulas and the relationship between Δt and ΔT is obtained, Δt = LΔT / (T _ep − T _i ) V, which can be expressed as Δt = ΔT / κV ... Using the temperature gradient κ.

Next, assuming a case where the temperature changes stepwise as shown in FIG. 9, let's find the time left until random nucleation occurs in each micro region ξ. Since the induction time t _{d at the} temperature T is given by t _d = τ _o · exp (E _a / kT) ... As described in the background section, in the minute region of the temperature T _i (ξ = 1) The induction time is τ _o exp (E _a / kT _i ), and at the end of this minute region, the remaining time until random nucleation (hereinafter simply referred to as remaining time) is τ _o exp (E _a / KT _i ) -Δt. From this, the remaining time ratio in the small area ξ = 1 is Given in.

Next, consider a small region (ξ = 2) of temperature T _i + ΔT. Since it has already been annealed for Δt time at the temperature T _i in the minute region of ξ = 1, if this is used as the starting point, the induction time until nucleation will have a time corresponding to the ratio represented by the remaining time ratio. There is. Therefore, the induction time in the minute region of ξ = 2 is represented by τ _o exp (E _a / k (T _i + ΔT)) × [1- (Δt / τ _o ) exp (−E _a / kT _i )] It Therefore, the remaining time in the small region ξ = 2 is τ _o exp (E _a / k (T _i + ΔT)) [1- (Δt / τ _o ) × exp (-E _a / kT _i )]-Δt , The remaining time ratio is {τ _o exp (E _a / k (T _i + ΔT)) [1- (Δt / τ _o ) exp (-E _a / kT _i )] − Δt} ÷ τ _o exp (E _a / k (T _i + ΔT)) = 1− (Δt / τ _o ) exp (−E _a / kT _i ) − (Δt / τ _o ) exp (−E _a / k (T _i + ΔT)).

Similarly, in the small region ξ = 3 of the temperature T _i + 2ΔT, if only the result is shown, the induction time; τ _o exp (E _a / k (T _i + 2ΔT)) [1 − (Δt / τ _o ) exp ( −E _a / kT _i ) − (Δt / τ _o ) exp (−E _a / k (T _i + ΔT))] Remaining time; τ _o exp (−E _a / k (T _i + 2ΔT) [1 − (Δt / τ _o ) exp (−E _a / kT _i ) − (Δt / τ _o ) exp (−E _a / k (T _i + ΔT))] −Δt Remaining time rate; 1− (Δt / τ _o ) exp ( −E _a / kT _i )] − (Δt / τ _o ) exp (−E _a / k (T _i + ΔT)) − (Δt / τ _o ) exp (−E _a / k (T _i + 2ΔT)) To be done.

By deducing this, the induction time; τ _o exp [E _a / k (T _i + (n-1) ΔT)] in the last minute region (ξ = n) of the temperature T _i + (n-1) ΔT × {1- (Δt / τ _o ) exp (−E _a / kT _i ) − (Δt / τ _o ) exp (−E _a / k (T _i + ΔT)) − (Δt / τ _o ) exp (−E _a / k (T _i + 2ΔT)) …………
……………………… − (Δt / τ _o ) exp [−E _a / k (T _i + (n-2) Δ
T)]} Remaining time; τ _o exp [E _a / k (T _i + (n-1) ΔT)] × {1- (Δt / τ _o ) exp (−E _a / kT _i ) − (Δt / τ _o ) exp (−E _a / k (T _i + ΔT)) − (Δt / τ _o ) exp (−E _a / k (T _i + 2ΔT)) …………
……………………… − (Δt / τ _o ) exp [−E _a / k (T _i + (n-2) Δ
T)]}-Δt remaining time rate; 1- (Δt / τ _o ) exp (-E _a / kT _i )]-(Δt / τ _o ) exp (-E _a / k (T _i + ΔT))-( Δt / τ _o ) exp (−E _a / k (T _i + Δ2T)) …………
............ − (Δt / τ _o ) exp [−E _a / k (T _i + (n−1) ΔT)] is obtained.

Therefore, the induction time at the moment when the solid phase epitaxial set temperature T _ep is reached is τ _o exp (E _a / k (T _i + nΔT)) × {1- (Δt / τ _o ) exp (−E _a / kT _i ) − (Δt / τ _o ) exp (−E _a / k (T _i + ΔT)) − (Δt / τ _o ) exp (−E _a / k (T _i + 2ΔT)) …………
……………………… − (Δt / τ _o ) exp [−E _a / k (T _i + (n-1) Δ
T)]} ...

The condition for solid phase epitaxial growth without causing random nucleation is that the induction time has not yet passed when the sample reaches the solid phase epitaxial set temperature T _ep and becomes a single crystal. .

The condition is that the above equation is positive. That is, τ _o exp (E _a / k (T _i + nΔT)) × {1- (Δt / τ _o ) exp (−E _a / kT _i ) − (Δt / τ _o ) exp (−E _a / k ( T _i + ΔT)) − (Δt / τ _o ) exp (−E _a / k (T _i + 2ΔT)) …………
……………………… − (Δt / τ _o ) exp [−E _a / k (T _i + (n-1) Δ
T)]} ≧ 0 Furthermore, this conditional expression is 1 ≧ (Δt / τ _o ) {exp (−E _a / kT _i ) + exp (−E _a / k (T _i + ΔT)) + exp (−E _a / k (T _i + 2ΔT)) ……………………………… + exp [-E _a / k (T _i + (n-1) ΔT)]} is transformed into Is τ _o κV ≧ ΔT · Σexp [−E _a / k (T _i + (ξ−1) Δ
T)] (the sum is from ξ = 1 to ξ = n). Therefore, if T _i + (ξ−1) ΔT = T is set and ΔT → 0 (n → ∞), the above expression is rewritten as an integral expression. Is obtained.

Also, this formula is You can also write

Note that τ _o is defined by an equation and can be determined by experiment.

(Second Conditional Expression) The steep rising temperature gradient κ may be determined so as to satisfy the above expression, but this also changes depending on the moving speed V of the sample, and if the moving speed of the sample is increased, the temperature gradient is increased. The demand for κ will be lenient.

However, the moving speed V of the sample cannot be arbitrarily increased, and there is an upper limit speed. That is, if the moving speed V of the sample is higher than the solid phase epitaxial growth speed V _ep , the single crystal cannot grow sufficiently. Therefore, it is necessary to satisfy V ≦ V _ep .. .., and the upper limit of the moving speed V of the sample is the solid phase epitaxial growth speed V _ep .

It is known that when a single crystal exists adjacent to the amorphous phase, solid phase epitaxial growth occurs from the single crystal, but the solid phase epitaxial growth rate V _ep increases with increasing temperature. Solid phase epitaxial growth is
This is because the atoms of the amorphous phase at the interface between the crystal and the amorphous phase occur when they fall into the crystal lattice position where the free energy is lower. FIG. 8 shows the experimental results for examining the relationship between the solid phase epitaxial growth rate V _ep and the solid phase epitaxial set temperature T _ep . From this result, the temperature dependence of V _ep = V _o exp (−E _ep / kT _ep ) is obtained. Here, E _ep is the activation energy of solid phase epitaxial growth. Then,
The sample moving speed V must be determined so as to satisfy V ≦ V _o exp (−E _ep / kT _ep ).

FIG. 5 shows another example of the present invention in which an insulating layer 1a of silicon oxide (SiO ₂ ) is formed on a silicon single crystal layer 25, and an appropriate window 26 is opened in the insulating layer 1a. To expose the silicon single crystal layer 25, and the amorphous silicon film 2a is formed on the entire surface.
This is a case of using a sample having a film formed thereon. Thus, the sample 13 is moved while irradiating the spot-shaped local heating device with the laser beam 19 from above in a dot shape and irradiating the linear local heating device with the linear heating wire 24 extending in the width direction from above. . Thus, the amorphous silicon film 2a is solid-phase epitaxially grown using the silicon single crystal layer 25 exposed from the window 26 as a seed crystal to form the single crystal silicon film 3a. Then, a MOSFET having an SOI structure or the like can be formed on the single crystal silicon film 3a.

The present invention can be appropriately modified in addition to this, and for example, solid phase epitaxial growth may be performed while scanning a spot-shaped local heating device such as a laser in the width direction of the sample. It is also possible to use a sample in which an amorphous semiconductor layer is formed on the lower surface of a quartz glass substrate.

〔effect〕

According to the present invention, an amorphous semiconductor layer can be solid-phase epitaxially grown without causing random nucleation that hinders the growth of a uniform single crystal semiconductor layer, and a large-area single crystal semiconductor layer is obtained. Is something that can be done.

[Brief description of drawings]

FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a schematic view showing the entire lateral annealing furnace, and FIG. 3 (a).
(B) is a side view of the above and a graph showing the temperature distribution of the sample,
FIG. 4 is a plan view showing a sample in which a single crystal semiconductor layer is solid-phase epitaxially grown by the above-mentioned lateral annealing furnace, FIG. 5 is a sectional view showing a sample of another form, and FIGS. 6 (a) and 6 (b). (C) and (d) are graphs showing the relationship between annealing time and X-ray intensity at different annealing temperatures,
FIG. 7 is a graph showing the relationship between induction time and temperature, FIG. 8 is a graph showing an example of the relationship between solid phase epitaxial growth rate and temperature, and FIG. 9 is a reference for deriving an equation that gives the necessary temperature gradient. It is a figure. 1 ... Quartz glass substrate, 1a ... Insulating layer, 2,2a ... Amorphous silicon film, 3,3a ... Single crystal silicon film, 4 ... Gold layer.

(72) Inventor Eiichi Eiichi 2-11-4 Otino, Kanazawa City, Ishikawa Prefecture Miyamoto Heights (72) Inventor Shuichi Okano 1248, Nonomachi, Takaoka City, Toyama Prefecture (72) Inventor Yoshio Kakimoto Kanazawa City, Ishikawa Prefecture 2-6-23 Heiwacho 23-205 Prefectural residence 23-205 (72) Inventor Watari Uesaka 35-22 Moriyashinmachi, Takatsuki-shi, Osaka Matsusetori (56) References JP 62-92427 (JP, A) JP Sho 61-196515 (JP, A) JP-A-58-114420 (JP, A)

Claims (3)

[Claims] 1. An amorphous semiconductor layer is formed on an insulating layer, and the amorphous semiconductor layer is heated from an initial temperature to a solid phase epitaxial set temperature within a time shorter than an induction time for random nucleation. Phase transition between solid phase (amorphous semiconductor) and solid phase (single crystal semiconductor) by increasing temperature and annealing under temperature conditions having a steep rising temperature gradient and moving the annealed region relatively. And a single crystal semiconductor layer is grown on the insulating layer by solid phase epitaxial growth. 2. Under the temperature condition where the initial temperature T _i changes to the solid phase epitaxial set temperature T _ep with a steep temperature gradient κ, the following conditional expression (Where Ea is the activation energy, k is the Boltzmann constant, T is the integration constant, and τ _o is a constant, which is the induction time until the generation of crystal nuclei at infinite temperature.) The method for producing a semiconductor crystal layer according to claim 1, wherein the crystalline semiconductor layer and the insulating layer are relatively moved at a speed V. 3. A seeding metal layer is provided on a part of the insulating layer or the amorphous semiconductor layer, and a eutectic region is formed by the metal layer and the amorphous semiconductor layer. The method for producing a semiconductor crystal layer according to claim 1, wherein the single crystal semiconductor layer is grown by solid-phase epitaxial growth from the crystal region.