JPH07335116A - Electron emission device - Google Patents

Electron emission device

Info

Publication number
JPH07335116A
JPH07335116A JP13148894A JP13148894A JPH07335116A JP H07335116 A JPH07335116 A JP H07335116A JP 13148894 A JP13148894 A JP 13148894A JP 13148894 A JP13148894 A JP 13148894A JP H07335116 A JPH07335116 A JP H07335116A
Authority
JP
Japan
Prior art keywords
electron
electron emission
fine
conductor region
emitting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13148894A
Other languages
Japanese (ja)
Inventor
Tadashi Sakai
忠司 酒井
Tomio Ono
富男 小野
Hiroyuki Nakamura
裕之 中村
Tetsushi Tanamoto
哲史 棚本
Masayuki Nakamoto
正幸 中本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13148894A priority Critical patent/JPH07335116A/en
Publication of JPH07335116A publication Critical patent/JPH07335116A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide an electron emission device capable of emitting electrons with high intensity and uniformity by forming an electron emission cathode of a conductor region in the gap of fine skeletons formed on the main surface of a semiconductor board. CONSTITUTION:A silicon nitride film 2 is formed on one main surface of a silicon board 1, and an aluminium electrode 3 is deposited on the other main surface. The silicon board other than a part for forming an electron emission cathode is covered with an acid resistant protection film, and anodically formed in a hydrofluoric acid family etching solution to form silicon fine skeletons 4. Porous silicon obtained has the three dimensionally extended silicon fine skeletons 4, and gaps 5 exist between them. Anodic oxidation is conducted in a non-etching electrolyte solution by using silicon as an anode to form an anode oxide film 6 on the surface of the silicon fine skeleton 4. By using nickel for a conductor, a conductor region 7 is formed in the gap 5. Nickel electrodes 8 serving as electrodes in the conductor region 7 are arranged at both ends of a device by utilizing continuity in the lateral direction of the conductor region 7 to complete an electron emission device.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子放出素子に関する。FIELD OF THE INVENTION The present invention relates to an electron-emitting device.

【0002】[0002]

【従来の技術】電子放出源として用いられる電子放出素
子は近年、超高速マイクロ波デバイス・電子線デバイス
・平面型画像表示装置などへの応用が進められている。
従来、電子放出源としては熱陰極型電子放出素子が多く
用いられてきたが、熱陰極を利用した電子放出素子では
加熱によるエネルギ−ロスが大きく予備電離が必要であ
るうえ、過熱による陰極先端の消耗や汚染が激しく寿命
が短いなどの問題があった。
2. Description of the Related Art In recent years, electron-emitting devices used as electron-emitting sources have been applied to ultra-high-speed microwave devices, electron beam devices, flat-panel image display devices and the like.
Conventionally, hot cathode type electron-emitting devices have been widely used as electron emission sources, but electron-emitting devices using hot cathodes require large pre-ionization due to large energy loss due to heating, and also the cathode tip due to overheating. There were problems such as severe wear and pollution and short life.

【0003】これらの問題を解決するために注目されて
いる従来の電子放出素子には冷陰極型のものが知られて
おり、その中でも局部的に高電界を発生させて電界放出
を行わせる電界効果型の電子放出素子の研究が近年盛ん
に行われている。
A cold cathode type is known as a conventional electron-emitting device which has been drawing attention to solve these problems. Among them, an electric field for locally generating a high electric field to perform field emission is known. In recent years, active electron emission devices have been actively researched.

【0004】この電界効果型の電子放出素子の一例とし
て、特開平5−211030号公報に示されたものを図
6の断面図に挙げる。まずアルミニウム(Al)を陽極
化成して細孔61を開ける。このとき細孔61は電界を
加えた方向に対して水平な方向、つまり紙面の縦方向に
成長する。またAlは陽極化成を行うときに同時に陽極
酸化されてアルミナ(Al23 )層62となる。この
後、細孔61の一部に電子放出陰極63を充填し、Al
23 層62の片面上に導電部64を形成して複数の電
子放出陰極63を結合する。
As an example of this field effect type electron-emitting device, the one shown in Japanese Unexamined Patent Publication No. 5-211030 is shown in the sectional view of FIG. First, aluminum (Al) is anodized to open the pores 61. At this time, the pores 61 grow in a direction horizontal to the direction in which the electric field is applied, that is, in the vertical direction of the paper surface. Further, Al is anodized at the same time when anodization is performed to form an alumina (Al 2 O 3 ) layer 62. After that, a part of the pores 61 is filled with the electron emission cathode 63, and Al
A conductive portion 64 is formed on one surface of the 2 O 3 layer 62 to bond the plurality of electron emission cathodes 63.

【0005】この様な構造をとると、陰極の形状をAl
23 層62に開けた細孔61の形状によって決めるこ
とができるので、陰極の先端形状のばらつきが小さくな
り信頼性の高い電子放出素子を得ることができる。
With such a structure, the shape of the cathode is changed to Al.
Since it can be determined by the shape of the pores 61 formed in the 2 O 3 layer 62, the variation in the shape of the tip of the cathode is reduced and a highly reliable electron-emitting device can be obtained.

【0006】しかしこの電子放出素子では次のような問
題があった。まずAlの陽極酸化膜は電界を加えた方向
に対して水平な方向に細孔61が成長し、ほとんど枝別
れや横方向の成長をしない。したがってこの細孔に電子
放出陰極63を充填するとほぼ垂直な柱状の構造となる
一方で、充填しなかった細孔61が縦方向に長い空洞と
して残るために素子の強度が弱くなってしまい十分な耐
久性を得ることができない。
However, this electron-emitting device has the following problems. First, in the anodic oxide film of Al, the pores 61 grow in the direction horizontal to the direction in which the electric field is applied, and there is almost no branching or lateral growth. Therefore, when the electron emitting cathode 63 is filled in the pores, a substantially vertical columnar structure is formed. On the other hand, the unfilled pores 61 remain as cavities that are long in the vertical direction, so that the strength of the device is weakened, which is sufficient. Durability cannot be obtained.

【0007】また電子放出陰極63が縦方向に長い柱状
に独立して並んでいるため導電部でつながってはいて
も、細孔61自体の直径がまちまちであるためここに充
填された電子放出陰極63は直径が不均一で、抵抗値も
変わってしまい、1本1本に流れる電流の均一性はあま
り高くない。したがって均一な電界集中による電子放出
ができない。
Further, since the electron-emitting cathodes 63 are arranged independently in a column shape long in the vertical direction and are connected by a conductive portion, the diameters of the pores 61 themselves are different, so that the electron-emitting cathodes filled therein are filled. No. 63 has a non-uniform diameter, and the resistance value also changes, so the uniformity of the current flowing through each wire is not very high. Therefore, electrons cannot be emitted due to uniform electric field concentration.

【0008】[0008]

【発明が解決しようとする課題】以上のべたように、従
来の電子放出素子では素子の強度が弱く、また均一な電
界集中による電子放出ができないという問題があった。
本発明は以上のような問題を解決し、強度が強く、均一
な電子放出ができる電子放出素子を提供することを目的
とする。
As described above, the conventional electron-emitting device has the problems that the device is weak in strength and that it cannot emit electrons due to uniform electric field concentration.
An object of the present invention is to solve the above problems and to provide an electron-emitting device having high strength and capable of uniform electron emission.

【0009】[0009]

【課題を解決するための手段】上記の問題を解決するた
めに本発明は請求項1の発明として、半導体基板の主面
に形成された微細骨格と、この微細骨格の間隙に充填さ
れた導体領域の電子放出陰極とを備えたことを特徴とす
る電子放出素子を提供する。
In order to solve the above problems, the present invention provides a first aspect of the present invention, wherein a fine skeleton formed on a main surface of a semiconductor substrate and a conductor filled in a gap between the fine skeletons. Provided is an electron-emitting device having an area electron-emitting cathode.

【0010】また請求項2の発明として、半導体基板の
主面に形成された微細骨格の電子放出制御ゲ−トと、前
記微細骨格の間隙に充填された導体領域の電子放出陰極
とを備えたことを特徴とする電子放出素子を提供する。
According to a second aspect of the present invention, there is provided an electron emission control gate of a fine skeleton formed on the main surface of the semiconductor substrate, and an electron emission cathode of a conductor region filled in the gap of the fine skeleton. An electron-emitting device is provided.

【0011】さらに本発明は請求項3の発明として、半
導体基板の主面に形成された微細骨格の電子放出陰極
と、前記微細骨格の間隙に充填された導体領域とを備え
たことを特徴とする電子放出素子を提供する。
Further, the present invention provides, as the invention of claim 3, an electron emitting cathode having a fine skeleton formed on the main surface of the semiconductor substrate, and a conductor region filled in a gap of the fine skeleton. Provided is an electron emitting device.

【0012】また請求項4の発明として、半導体基板の
主面に形成された微細骨格の電子放出陰極と、前記微細
骨格の間隙に充填された導体領域の電子放出制御ゲ−ト
とを備えたことを特徴とする電子放出素子を提供する。
According to a fourth aspect of the present invention, there is provided an electron emission cathode having a fine skeleton formed on the main surface of the semiconductor substrate, and an electron emission control gate for the conductor region filled in the gap of the fine skeleton. An electron-emitting device is provided.

【0013】さらに本発明は請求項7の発明として、半
導体基板の主面に形成され、導体層が被覆された微細骨
格の電子放出陰極を備えたことを特徴とする電子放出素
子を提供する。
Further, the present invention provides, as a seventh aspect of the invention, an electron-emitting device comprising an electron-emitting cathode of a fine skeleton formed on the main surface of a semiconductor substrate and covered with a conductor layer.

【0014】ここで半導体基板とは表面に半導体が露出
した基板のことであり、半導体そのものを用いたものの
ほかにも、絶縁性物質の表面に半導体層が形成されたも
のなども含む。
Here, the semiconductor substrate means a substrate in which the semiconductor is exposed on the surface, and includes not only a substrate using the semiconductor itself but also a substrate having a semiconductor layer formed on the surface of an insulating material.

【0015】また微細骨格とは半導体基板に陽極化成な
どを施すことによって形成されるものであり、例えば珊
瑚やヘチマのように細線状の骨格が3次元的に連結され
ている構造をいい、細線が柱状に並列していてほとんど
連結していない状態とは異なる。
The fine skeleton is formed by subjecting a semiconductor substrate to anodization or the like, and refers to a structure in which fine line-shaped skeletons are three-dimensionally connected, such as coral and loofah. It is different from the state in which columns are parallel to each other and hardly connected.

【0016】このような微細骨格の形状は、用いる半導
体基板の不純物濃度によって変わってくる。不純物濃度
が高いと細線が柱状に並列する構造に近くなり、不純物
濃度が低くなるにつれて柱状の構造からより遠い3次元
的な構造になってくる。また半導体基板の不純物濃度が
高い場合でも陽極化成工程において光を照射したり流す
電流を大きくしたりすると、不純物濃度が低い場合と同
じような微細骨格の構造になる。
The shape of such a fine skeleton varies depending on the impurity concentration of the semiconductor substrate used. When the impurity concentration is high, the thin wires are close to a columnar parallel structure, and as the impurity concentration is low, the structure becomes a three-dimensional structure farther from the columnar structure. Further, even when the impurity concentration of the semiconductor substrate is high, if the light is irradiated or the current flowing in the anodization step is increased, the structure has a fine skeleton similar to that when the impurity concentration is low.

【0017】また導体領域を微細骨格の間隙に充填する
とは、微細骨格の間隙すべてに導体領域を形成すること
のほかに、間隙の一部に導体領域を形成することも含
む。例えば間隙の途中まで導体領域が形成され間隙の上
部にはない場合や、間隙の一部で導体領域がなくなって
いて導体領域中に細孔が形成されている場合である。
Filling the gaps of the fine skeleton with the conductor regions includes not only forming the conductor regions in all the gaps of the fine skeleton but also forming the conductor regions in a part of the gaps. For example, there is a case where a conductor region is formed in the middle of the gap and is not above the gap, or a case where the conductor region is lost in a part of the gap and pores are formed in the conductor region.

【0018】ここで導体領域あるいは導体層に用いるこ
とのできる材料としては、金(Au)、白金(Pt)な
どのように表面が酸化変質しにくく安定である材料や、
銀(Ag)などのように電気的な伝導性に優れている材
料、さらにはダイアモンド(C)やシリコンカ−バイド
(SiC)などのように強度が高く機械的に安定な材
料、サ−メットなどのように融点が高く耐熱性に優れる
材料などがある。また以上のものに限らず、仕事関数が
低く電子放出の効率のよい材料であれば何でも用いるこ
とができる。
Here, as a material that can be used for the conductor region or the conductor layer, a material such as gold (Au) or platinum (Pt) whose surface is resistant to oxidative deterioration and is stable,
Materials with excellent electrical conductivity such as silver (Ag), and materials with high strength and mechanical stability such as diamond (C) and silicon carbide (SiC), cermet, etc. As described above, there are materials having a high melting point and excellent heat resistance. Further, not limited to the above materials, any material having a low work function and a high electron emission efficiency can be used.

【0019】また請求項1〜4の発明においては、微細
骨格を持つ半導体基板の主面を陽極酸化して陽極酸化膜
を形成しても良い。陽極酸化膜を形成した場合、しない
場合いずれも、請求項1の発明では導体領域を電子放出
陰極、請求項2の発明では導体領域を電子放出陰極、微
細骨格を電子放出制御ゲ−トとして用いることができ
る。あるいはその逆に、請求項3の発明では微細骨格を
電子放出陰極、請求項4の発明では微細骨格を電子放出
陰極、導体領域を電子放出制御ゲ−トとして用いること
ができる。このため請求項2・4の発明では電界放出制
御ゲ−トを別に設ける必要がなくなる。
Further, in the inventions of claims 1 to 4, the main surface of the semiconductor substrate having a fine skeleton may be anodized to form an anodized film. In both cases where the anodic oxide film is formed and not formed, the conductor region is used as an electron emission cathode in the invention of claim 1, the conductor region is used as an electron emission cathode in the invention of claim 2, and the fine skeleton is used as an electron emission control gate. be able to. On the contrary, in the invention of claim 3, the fine skeleton can be used as an electron emission cathode, in the invention of claim 4 the fine skeleton can be used as an electron emission cathode, and the conductor region can be used as an electron emission control gate. Therefore, in the inventions of claims 2 and 4, it is not necessary to separately provide a field emission control gate.

【0020】ここで導体領域を電子放出陰極として用い
る場合、形成した陽極酸化膜をエッチングして導体領域
が露出するようにすればより良好な電子放出が行えるよ
うになる。
When the conductor region is used as an electron emission cathode, it is possible to perform better electron emission by etching the formed anodic oxide film to expose the conductor region.

【0021】さらに請求項1の発明においては、導体領
域を形成した後に微細骨格の上部をエッチングして導体
領域の側面が露出するようにしても良い。この場合には
陽極酸化膜は形成しない。
Further, in the invention of claim 1, after forming the conductor region, the upper part of the fine skeleton may be etched to expose the side surface of the conductor region. In this case, the anodic oxide film is not formed.

【0022】また請求項7の発明においては、表面に導
体層が形成された微細骨格を電子放出陰極として用いる
ことになる。この場合、微細骨格の表面と導体層との間
に陽極酸化膜を形成しても良い。電子放出陰極は先端が
露出した状態になるので良好な電子放出が行える。
Further, in the invention of claim 7, the fine skeleton having the conductor layer formed on the surface thereof is used as the electron emission cathode. In this case, an anodic oxide film may be formed between the surface of the fine skeleton and the conductor layer. Since the tip of the electron emission cathode is exposed, good electron emission can be performed.

【0023】請求項1〜4の発明では微細骨格の間隙に
導体領域を充填し、請求項7の発明では導体層を,微細
骨格を持つ半導体基板の主面に被覆する。これは導体を
形成する時間によって変えることができる。時間を長く
すれば充填が行われ、時間を短くすれば被覆されるだけ
ですむ。
In the first to fourth aspects of the invention, the conductor regions are filled in the gaps of the fine skeleton, and in the seventh aspect of the invention, the conductor layer is coated on the main surface of the semiconductor substrate having the fine skeleton. This can be changed by the time it takes to form the conductor. Longer times will only fill, shorter times will only cover.

【0024】この違いは陽極酸化膜を形成する場合には
陽極酸化を行うときの電流によっても左右される。電流
が大きいと、微細骨格の底部に形成される陽極酸化膜の
厚さが微細骨格の他の部分に形成される陽極酸化膜の厚
さよりも厚くなり、導体が微細骨格の底部から順に充填
されやすくなる。これに対して電流が小さいと、形成さ
れる陽極酸化膜の厚さは均一で導体も均一に形成されや
すくなる。ただ、電流が小さくても導体を形成する時間
が長ければ導体は微細骨格の間隙に充填される。
This difference also depends on the current when anodizing is performed when forming the anodized film. When the current is large, the thickness of the anodic oxide film formed on the bottom of the fine skeleton becomes thicker than the thickness of the anodic oxide film formed on other parts of the fine skeleton, and the conductors are sequentially filled from the bottom of the fine skeleton. It will be easier. On the other hand, when the current is small, the thickness of the formed anodic oxide film is uniform, and the conductor is easily formed uniformly. However, even if the current is small, if the time for forming the conductor is long, the conductor is filled in the gaps of the fine skeleton.

【0025】[0025]

【作用】本発明の請求項1〜4の発明によれば、半導体
基板の主面に形成された微細骨格が3次元的に連結され
た構造をとっていて横方向へも電子が自由に動け、この
微細骨格あるいは微細骨格の間隙に充填された導体領域
のいずれかを電子放出陰極として用いるため、電子放出
陰極が柱状に並んだ従来の電子放出素子と比べると強度
が強くなり、また陰極ごとの電子放出が均一となる。
According to the first to fourth aspects of the present invention, the fine skeleton formed on the main surface of the semiconductor substrate has a structure in which the fine skeletons are three-dimensionally connected, and electrons can freely move in the lateral direction. Since either the fine skeleton or the conductor region filled in the gap of the fine skeleton is used as the electron emission cathode, the strength is higher than that of the conventional electron emission device in which the electron emission cathodes are arranged in a columnar shape, and The electron emission becomes uniform.

【0026】また請求項7の発明によれば、微細骨格を
持つ半導体基板の主面に導体層を形成し微細骨格を電子
放出陰極として用いる。この場合も請求項1〜4の発明
と同様に従来の電子放出素子と比べると強度が強くな
り、均一な電子放出ができるようになる。
According to the invention of claim 7, a conductor layer is formed on the main surface of a semiconductor substrate having a fine skeleton, and the fine skeleton is used as an electron emission cathode. In this case as well, as in the first to fourth aspects of the invention, the strength is higher than that of the conventional electron-emitting device, and uniform electron emission can be performed.

【0027】[0027]

【実施例】以下、本発明の実施例を説明する。 (実施例1)図1に本実施例に係る電子放出素子の製造
工程の模式的な断面図を示す。この電子放出素子は微細
骨格を電子放出制御ゲ−ト、導体領域を電子放出陰極と
して用いている。以下、図1に沿って説明する。
EXAMPLES Examples of the present invention will be described below. (Embodiment 1) FIG. 1 shows a schematic sectional view of a manufacturing process of an electron-emitting device according to this embodiment. This electron-emitting device uses a fine skeleton as an electron emission control gate and a conductor region as an electron emission cathode. Hereinafter, description will be given with reference to FIG.

【0028】まず半導体基板として、(100)方位を
有する面、p型、体積抵抗率10Ωcmのシリコン(S
i)基板1の一方の主面に窒化シリコン膜2を形成す
る。Si基板1の電子放出陰極を形成する部分に相当す
る窒化シリコン膜2の部分をパターニングした後、窒化
シリコン膜2を形成したのと反対の主面に300nmの
厚さのAl電極3を蒸着形成し、さらにオーミック接触
を取るために窒素+水素の混合雰囲気中で470℃、2
0分間のシンターリングを行った。
First, as a semiconductor substrate, silicon (S) having a plane having a (100) orientation, p-type and a volume resistivity of 10 Ωcm (S
i) A silicon nitride film 2 is formed on one main surface of the substrate 1. After patterning a portion of the silicon nitride film 2 corresponding to a portion forming the electron emission cathode of the Si substrate 1, an Al electrode 3 having a thickness of 300 nm is formed by vapor deposition on the main surface opposite to the surface on which the silicon nitride film 2 is formed. 470 ° C. in a mixed atmosphere of nitrogen and hydrogen for further ohmic contact, 2
Sintering was performed for 0 minutes.

【0029】そして電子放出陰極を形成する部分を残し
てSi基板1を耐酸性の保護膜(図示せず)で覆い、フ
ッ酸系エッチング溶液中で陽極化成を行い、平均高さ1
0μmのSi微細骨格4を形成した。エッチング溶液に
は49%のフッ酸:エタノール=2:3の混合溶液を用
いた。また陽極化成は1mA/cm2 の電流密度で、白
熱ランプを至近距離から照射しながら行った。化成時間
は5分とした。この様にして得られた多孔質のSiは3
次元的にSi微細骨格4が伸び、その間に間隙5が存在
する構造になっている。上下に存在するいくつもの間隙
は紙面の奥行き方向でつながっている。(図1
(a))。
Then, the Si substrate 1 is covered with an acid-resistant protective film (not shown) while leaving a portion for forming an electron emission cathode, and anodization is performed in a hydrofluoric acid-based etching solution to obtain an average height of 1
A Si fine skeleton 4 of 0 μm was formed. As the etching solution, a mixed solution of 49% hydrofluoric acid: ethanol = 2: 3 was used. The anodization was performed at a current density of 1 mA / cm 2 while irradiating an incandescent lamp from a very short distance. The formation time was 5 minutes. The porous Si obtained in this way is 3
The Si fine skeleton 4 extends dimensionally, and a gap 5 exists between them. The gaps that exist above and below are connected in the depth direction of the paper. (Fig. 1
(A)).

【0030】続いて非エッチング性の電解溶液中でSi
を陽極にして陽極酸化を行い、Si微細骨格4の表面に
陽極酸化膜6を形成した。この時の電流密度は1mA/
cm2 とし、電圧は酸化を開始する時点から20V以下
に抑えた。これは過大な電圧まで酸化を行うとSi微細
骨格4が電気的に基板と絶縁されてしまうため、これを
防ぐためである。基板と絶縁されてしまう理由は、電圧
が大きくなるとSi微細骨格4の根元が他の部分よりも
優先的に酸化されてしまい、電気的に絶縁された状態と
なるからだと考えられている(図1(b))。
Subsequently, in a non-etching electrolytic solution, Si
Was used as an anode to carry out anodization to form an anodized film 6 on the surface of the Si fine skeleton 4. The current density at this time is 1 mA /
cm 2 and the voltage was suppressed to 20 V or less from the time when the oxidation was started. This is to prevent the Si fine skeleton 4 from being electrically insulated from the substrate when it is oxidized to an excessive voltage. It is considered that the reason why the Si fine skeleton 4 is electrically insulated from the substrate is that the root of the Si fine skeleton 4 is more preferentially oxidized than other portions when the voltage is increased, and becomes electrically insulated (Fig. 1 (b)).

【0031】次に導体としてニッケル(Ni)を用い、
間隙5に導体領域7を形成した。形成には電解メッキ法
を用いた。条件は次のようにした。硫酸ニッケル(Ni
SO4 )+塩化ニッケル(NiCl2 )+ほう酸からな
る酸性のニッケルメッキ液を用い、メッキ時の電流密度
を、Si基板1の陽極化成を行う前の表面積に対して1
0mA/cm2 とする。メッキ液を50℃に昇温して撹
拌し、必ず光を照射して行う。また時間は1分とした
(図1(c))。
Next, using nickel (Ni) as a conductor,
The conductor region 7 is formed in the gap 5. An electrolytic plating method was used for formation. The conditions were as follows. Nickel sulfate (Ni
SO 4 ) + nickel chloride (NiCl 2 ) + boric acid was used as an acidic nickel plating solution, and the current density during plating was 1 with respect to the surface area of the Si substrate 1 before anodization.
It is set to 0 mA / cm 2 . The plating solution is heated to 50 ° C., stirred, and irradiated with light without fail. The time was 1 minute (FIG. 1 (c)).

【0032】この様にして得られた、間隙5内の導体領
域7は極めて高密度の細線の端面があり、この細線の断
面積は数nm〜数百nmのオーダーと極めて細い。この
後、電子放出の効率をさらに上げるために、Si微細骨
格4と導体領域7との間にある陽極酸化膜6を、フッ化
アンモニウム(NH4 F)/フッ化水素(HF)の混合
溶液を用いて選択的にエッチバックし導体領域7の上部
が陽極酸化膜6に接触しないようにした。
The conductor region 7 in the gap 5 thus obtained has an end face of extremely high-density thin wire, and the cross-sectional area of this thin wire is extremely thin, on the order of several nm to several hundred nm. After that, in order to further increase the efficiency of electron emission, the anodic oxide film 6 between the Si fine skeleton 4 and the conductor region 7 is treated with a mixed solution of ammonium fluoride (NH 4 F) / hydrogen fluoride (HF). Is selectively used to etch back so that the upper portion of the conductor region 7 does not come into contact with the anodic oxide film 6.

【0033】最後に導体領域7の電極としてNiの電極
8を、導体領域7は横方向にもつながっていることを利
用して素子の両端部に設けて、本実施例に係る電子放出
素子が完成する(図1(d))。
Finally, the Ni electrode 8 is provided as the electrode of the conductor region 7 at both ends of the device by utilizing the fact that the conductor region 7 is connected in the lateral direction. It is completed (Fig. 1 (d)).

【0034】この電子放出素子ではSi微細骨格4を電
子放出制御ゲートとして、導体領域7を電子放出陰極と
して用いる。電子放出制御ゲートの電極にはAl電極3
を用いることができる。
In this electron-emitting device, the Si fine skeleton 4 is used as an electron emission control gate and the conductor region 7 is used as an electron emission cathode. Al electrode 3 is used as the electrode of the electron emission control gate.
Can be used.

【0035】この電子放出素子を陰極に用いると、従来
の電子放出素子と比べると陰極が3次元的につながって
いて横方向への連絡もあるので、強度が強くなり、また
陰極ごとの電子放出が均一になる。
When this electron-emitting device is used for the cathode, the cathode is three-dimensionally connected and there is lateral communication as compared with the conventional electron-emitting device, so that the strength is increased and the electron emission for each cathode is increased. Becomes uniform.

【0036】またp型Siを用いた本実施例の場合、陰
極に対してSi基板側のゲ−ト電位をゼロからマイナス
にしている範囲では陰極とゲ−トとの間には電流は流れ
ず、電界だけが印加された。このときの印加電圧を変化
させることによって、この陰極と対抗する位置に配置さ
れた陽極への放射電流を制御することができる。
In the case of this embodiment using p-type Si, a current flows between the cathode and the gate in the range in which the gate potential on the Si substrate side with respect to the cathode is set from zero to minus. Instead, only the electric field was applied. By changing the applied voltage at this time, it is possible to control the emission current to the anode arranged at a position opposed to the cathode.

【0037】なお陽極化成のときの電流密度は1〜10
0mA/cm2 の範囲であることが望ましい。これは電
流密度が高くなるにつれてSiの多孔度が大きくなるた
め、1mAより小さいとSiがほとんど陽極化成され
ず、100mAより大きいとほとんどが陽極化成されて
しまい微細骨格がほとんど残らないからである。また化
成時間は10秒〜10分であることが望ましい。これは
電流密度が高くなるにつれて微細骨格の深さが深くなっ
ていくため、10秒より短いと微細骨格の深さが浅す
ぎ、10分より長いと微細骨格の深さが深くなり過ぎる
からである。
The current density during anodization is 1 to 10
It is preferably in the range of 0 mA / cm 2 . This is because the porosity of Si increases as the current density increases, so that if the current density is less than 1 mA, Si is hardly anodized, and if it is more than 100 mA, most of the Si is anodized and the fine skeleton hardly remains. Further, the formation time is preferably 10 seconds to 10 minutes. This is because the depth of the fine skeleton becomes deeper as the current density becomes higher, and the depth of the fine skeleton becomes too shallow when the time is shorter than 10 seconds and becomes too deep when the time is longer than 10 minutes. is there.

【0038】陽極酸化のときの電流密度は10mA/c
2 以下であることが望ましい。これは電流密度が高す
ぎると陽極酸化膜の形成速度が速くなり過ぎて制御が難
しく、また微細骨格の上部に優先的に酸化膜が形成され
てしまい均一な膜厚を得ることが難しいからである。
The current density during anodic oxidation is 10 mA / c.
It is preferably m 2 or less. This is because if the current density is too high, the rate of formation of the anodic oxide film becomes too fast, making it difficult to control, and the oxide film is preferentially formed on the upper part of the fine skeleton, making it difficult to obtain a uniform film thickness. is there.

【0039】メッキを行うときの電流密度は10mA/
cm2 以下であることが望ましい。これは電流密度が高
すぎると導体領域の形成速度が速くなり過ぎて制御が難
しくなり、また微細骨格の上部に優先的に導体領域が形
成されてしまい微細骨格の下部にまで導体が入り込んで
いかないからである。またメッキ時間は30秒以上であ
ることが望ましい。これは30秒より短いと微細骨格の
間隙全体に導体領域が充填されないからである。
The current density when plating is 10 mA /
It is desirable that it is not more than cm 2 . This is because if the current density is too high, the formation speed of the conductor region becomes too fast, which makes control difficult, and the conductor region is preferentially formed on the upper part of the fine skeleton, so that the conductor may reach the lower part of the fine skeleton. Because there is no. The plating time is preferably 30 seconds or longer. This is because if it is shorter than 30 seconds, the entire conductor gap is not filled in the gaps of the fine skeleton.

【0040】またこの導体領域を充填する方法としては
無電解メッキ法を用いることもできる。この場合には例
えば酸性浴で次亜塩素酸ナトリウム(NaClO)+酢
酸ナトリウム(CH3 COONa)+硫酸ニッケル(N
iSO4 )の水溶液を90℃に保ち、これに基板を浸漬
してニッケルメッキを行うことができる。さらには、通
常の薄膜を形成する手段では入り込み得ない微細孔や間
隙などに液体あるいは気体を充填させ、その後の反応に
より導体領域となる導体材料を形成させる方法であれば
以上の方法の他にも制限なく用いることができる。具体
的には電解重合法、有機金属の熱分解法、含浸法、圧力
法、CVD法などである。
As a method of filling this conductor region, electroless plating can be used. In this case, for example, sodium hypochlorite (NaClO) + sodium acetate (CH 3 COONa) + nickel sulfate (N
An aqueous solution of iSO 4 ) can be kept at 90 ° C., and the substrate can be dipped in this for nickel plating. Furthermore, in addition to the above methods, any method may be used as long as it is a method of filling a liquid or a gas into micropores or gaps which cannot be entered by a means for forming a normal thin film, and forming a conductor material to be a conductor region by a subsequent reaction. Can be used without limitation. Specifically, there are an electrolytic polymerization method, an organic metal thermal decomposition method, an impregnation method, a pressure method, a CVD method and the like.

【0041】さらに導体領域としてはNiの他にも金属
あるいは低抵抗の半導体、例えばAu、Pt、インジウ
ム(In)、パラジウム(Pd)、Ag、銅(Cu)、
酸化スズ(SnO2 )、酸化タンタル(TaO5 )、酸
化インジウム(InO3 )、SiC、ニオブ(Nb)を
添加したSnO2 ,リン化インジウム(InP)、ヒ化
ガリウム(GaAs)、窒化ガリウム(GaN)、Ga
AlAsなどを使用できる。またこれらのうちの金属の
合金でも良い。
Further, as the conductor region, in addition to Ni, a metal or a low resistance semiconductor such as Au, Pt, indium (In), palladium (Pd), Ag, copper (Cu),
Tin oxide (SnO 2), tantalum oxide (TaO 5), indium oxide (InO 3), SiC, SnO 2 were added niobium (Nb), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride ( GaN), Ga
AlAs or the like can be used. Also, an alloy of metals among these may be used.

【0042】また裏面に形成する電極としてはAl以外
にもAu、AuGe、金(Au)/チタン(Ti)、A
u/Cr、ケイ化アルミニウム(AlSi)などを用い
ることもできる。 (実施例2)この電子放出素子は実施例1の電子放出素
子と構造はほぼ同じである。異なる点は微細骨格を電子
放出陰極、導体領域を電子放出制御ゲ−トとして用いて
いる点である。
In addition to Al, Au, AuGe, gold (Au) / titanium (Ti), A is used as the electrode formed on the back surface.
It is also possible to use u / Cr, aluminum silicide (AlSi), or the like. (Embodiment 2) This electron-emitting device has substantially the same structure as the electron-emitting device of Embodiment 1. The different point is that the fine skeleton is used as an electron emission cathode and the conductor region is used as an electron emission control gate.

【0043】この電子放出素子も実施例1の電子放出素
子と同様に従来の電子放出素子と比べると、強度が強く
なり、また陰極ごとの電子放出が均一になる。 (実施例3)図2に本実施例に係る電子放出素子の製造
工程の模式的な断面図を示す。以下の実施例において図
中の番号は、図1と同じ部分には同じ番号を付け詳しい
説明は省略する。この電子放出素子は陽極酸化膜を形成
せず微細骨格の上部をエッチングして導体領域を露出さ
せた点、そして導体領域を電子放出陰極として用いるが
微細骨格は電子放出制御ゲ−トとして用いない点が実施
例1の電子放出素子とは異なる。以下、図2に沿って説
明する。
Similar to the electron-emitting device of the first embodiment, this electron-emitting device is stronger than the conventional electron-emitting device, and the electron emission is uniform for each cathode. (Embodiment 3) FIG. 2 shows a schematic sectional view of a manufacturing process of an electron-emitting device according to this embodiment. In the following embodiments, the numbers in the figure are the same as those in FIG. 1, and the detailed description is omitted. In this electron-emitting device, the conductor region is exposed by etching the upper portion of the fine skeleton without forming an anodic oxide film, and the conductor region is used as an electron emission cathode, but the fine skeleton is not used as an electron emission control gate. The point is different from the electron-emitting device of the first embodiment. Hereinafter, description will be given with reference to FIG.

【0044】まず半導体基板として(100)方位を有
する面、n型、体積抵抗率0.1ΩcmのSi基板1を
用い、窒化シリコン膜を形成しなかった以外は実施例1
の図1(a)と同様にして陽極化成を行いSi微細骨格
4を形成した(図2(a))。
First, Example 1 was used except that a Si substrate 1 having a surface having a (100) orientation, an n-type, and a volume resistivity of 0.1 Ωcm was used as a semiconductor substrate, and a silicon nitride film was not formed.
Anodization was performed in the same manner as in FIG. 1A to form the Si fine skeleton 4 (FIG. 2A).

【0045】次に光を照射しない以外は実施例1の図1
(c)と同様に電解メッキ法によって間隙5に導体領域
7を充填した。なお光の照射は行っても良い(図2
(b))。
Next, as shown in FIG. 1 of Example 1 except that light is not irradiated.
Similarly to (c), the conductor region 7 was filled in the gap 5 by the electrolytic plating method. Note that light irradiation may be performed (Fig. 2
(B)).

【0046】最後にSi微細骨格4の表面から300n
m程度の厚さまでSiのみを選択的にエッチングして除
去した。エッチング溶液としてはヒドラジン:水=1:
1の混合溶液を用い、これを窒素雰囲気中で70℃に昇
温してエッチングを行った。この結果、導体領域7が突
出した状態になる(図2(c))。
Finally, from the surface of the Si fine skeleton 4 300 n
Only Si was selectively etched and removed to a thickness of about m. As an etching solution, hydrazine: water = 1:
Etching was performed by using the mixed solution of No. 1 and raising the temperature to 70 ° C. in a nitrogen atmosphere. As a result, the conductor region 7 is projected (FIG. 2C).

【0047】このようにして本実施例に係る電子放出素
子が完成する。この電子放出素子の場合は導体領域7を
電子放出陰極として用いる。次に図3に陰極に加えて電
界放出制御ゲ−トを形成した例を示す。図2と同じ部分
には同じ番号を付けた。
In this way, the electron-emitting device according to this example is completed. In the case of this electron-emitting device, the conductor region 7 is used as an electron-emitting cathode. Next, FIG. 3 shows an example in which a field emission control gate is formed in addition to the cathode. The same parts as those in FIG. 2 have the same numbers.

【0048】(100)面・n型・0.1ΩcmのSi
基板1の上にCVD法によって酸化Si膜31を形成し
てから、酸化Si膜31を形成したのと反対の主面に3
00nmの厚さのAl電極3を蒸着形成して、オーミッ
ク接触を取るために窒素+水素の混合雰囲気中で470
℃、20分間のシンターリングを行った。
Si of (100) plane, n-type, 0.1 Ωcm
After the Si oxide film 31 is formed on the substrate 1 by the CVD method, 3 is formed on the main surface opposite to the surface on which the Si oxide film 31 is formed.
An Al electrode 3 having a thickness of 00 nm is formed by vapor deposition, and 470 is formed in a mixed atmosphere of nitrogen and hydrogen for ohmic contact.
Sintering was performed at 20 ° C. for 20 minutes.

【0049】次に酸化Si膜31の上にマグネトロンス
パッタ法によって電界放出制御ゲ−トとなるNiの電極
層32を形成する。電子放出陰極を形成する部分の上の
電極層32と酸化Si膜31とを共にパタ−ニング除去
する。この後、電子放出陰極を形成する部分以外を耐酸
性のテ−プで覆って陽極化成を図2(a)と同様に行
い、後は図2(b)〜(c)に示したのと同様な工程で
電子放出素子が完成する。この際、基板1およびAl電
極3は陰極に電子を供給する電極として働く。
Next, an electrode layer 32 of Ni serving as a field emission control gate is formed on the Si oxide film 31 by magnetron sputtering. The electrode layer 32 and the Si oxide film 31 above the portion forming the electron emission cathode are both patterned and removed. After this, except for the portion where the electron emission cathode is formed, it is covered with an acid resistant tape to perform anodization in the same manner as in FIG. 2A, and thereafter, as shown in FIGS. 2B to 2C. An electron-emitting device is completed in the same process. At this time, the substrate 1 and the Al electrode 3 function as electrodes for supplying electrons to the cathode.

【0050】この電子放出素子も実施例1の電子放出素
子と同様に、強度が強くなり、陰極ごとの電子放出が均
一になる。なお陽極化成のときの電流密度は1〜50m
A/cm2 の範囲であることが望ましい。これは1mA
より小さいとSiがほとんど陽極化成されず、50mA
より大きいと陽極化成されてしまう体積が大きいため、
電子放出陰極として用いる、充填する導体領域の体積が
大きくなり、微細な構造を要求される電子放出陰極には
ふさわしくない構造となってしまうからである。また化
成時間は実施例1と同様な理由で10秒〜10分である
ことが望ましい。
Similar to the electron-emitting device of the first embodiment, this electron-emitting device has high strength and uniform electron emission for each cathode. The current density during anodization is 1 to 50 m.
It is preferably in the range of A / cm 2 . This is 1mA
If it is smaller, Si is hardly anodized and 50 mA
If it is larger, the volume that is anodized is large, so
This is because the volume of the filled conductor region used as the electron emission cathode becomes large and the structure becomes unsuitable for the electron emission cathode which requires a fine structure. The formation time is preferably 10 seconds to 10 minutes for the same reason as in Example 1.

【0051】陽極酸化・メッキのときの条件は実施例1
と同様で良い。 (実施例4)図4に本実施例に係る電子放出素子の製造
工程の模式的な断面図を示す。この電子放出素子は陽極
酸化膜を形成せず微細骨格の表面に導体層を被覆した点
が実施例2の電子放出素子とは異なる。ここでは導体層
を被覆した微細骨格が電子放出素子として用いられる。
以下、図4に沿って説明する。
The conditions at the time of anodic oxidation / plating are as in Example 1.
The same as (Embodiment 4) FIG. 4 shows a schematic sectional view of a manufacturing process of an electron-emitting device according to this embodiment. This electron-emitting device differs from the electron-emitting device of Example 2 in that the surface of the fine skeleton is covered with a conductor layer without forming an anodic oxide film. Here, the fine skeleton covering the conductor layer is used as an electron-emitting device.
Hereinafter, description will be given with reference to FIG.

【0052】まず実施例2の図2(a)と同様に陽極化
成を行い、Si基板1にSi微細骨格4を形成した(図
4(a))。次に実施例2の図2(b)と同様に電解メ
ッキ法を用いてSi微細骨格4の表面に導体層41を被
覆した。ただし時間は30秒とした(図4(b))。
First, anodization was performed in the same manner as in FIG. 2A of Example 2 to form the Si fine skeleton 4 on the Si substrate 1 (FIG. 4A). Next, the surface of the Si fine skeleton 4 was coated with the conductor layer 41 by using the electrolytic plating method as in FIG. However, the time was set to 30 seconds (FIG. 4 (b)).

【0053】このようにして本実施例に係る電子放出素
子が完成する。次に図5に電界放出制御ゲ−トを形成し
た例を示す。(100)面・n型・0.1ΩcmのSi
基板1の上にCVD法によって酸化Si膜31を形成し
てから、酸化Si膜31を形成したのと反対の主面に3
00nmの厚さのAl電極3を蒸着形成して、オーミッ
ク接触を取るために窒素+水素の混合雰囲気中で470
℃、20分間のシンターリングを行った。
In this way, the electron-emitting device according to this example is completed. Next, FIG. 5 shows an example in which a field emission control gate is formed. (100) surface, n-type, 0.1 Ωcm Si
After the Si oxide film 31 is formed on the substrate 1 by the CVD method, 3 is formed on the main surface opposite to the surface on which the Si oxide film 31 is formed.
An Al electrode 3 having a thickness of 00 nm is formed by vapor deposition, and 470 is formed in a mixed atmosphere of nitrogen and hydrogen for ohmic contact.
Sintering was performed at 20 ° C. for 20 minutes.

【0054】次に酸化Si膜31の上にマグネトロンス
パッタ法によって電界放出制御ゲ−トとなるNiの電極
層32を形成する。電子放出陰極を形成する部分の上の
電極層32と酸化Si膜31とを共にパタ−ニング除去
する。この後、電子放出陰極を形成する部分以外を耐酸
性のテ−プで覆って陽極化成を図3(a)と同様に行
い、後は図3(b)に示したのと同様な工程で電子放出
素子が完成する。図においてSi微細骨格4の表面には
導電層が被覆された状態となっている。
Next, an electrode layer 32 of Ni, which serves as a field emission control gate, is formed on the Si oxide film 31 by magnetron sputtering. The electrode layer 32 and the Si oxide film 31 above the portion forming the electron emission cathode are both patterned and removed. Thereafter, except for the portion where the electron emission cathode is formed, it is covered with an acid resistant tape to perform anodization in the same manner as in FIG. 3A, and thereafter, the same steps as shown in FIG. 3B are performed. The electron-emitting device is completed. In the figure, the surface of the Si fine skeleton 4 is covered with a conductive layer.

【0055】この電子放出素子も実施例1の電子放出素
子と同様に、強度が強くなり、陰極ごとの電子放出が均
一になる。なお陽極化成・陽極酸化のときの条件は実施
例1と同様で良い。
Similar to the electron-emitting device of the first embodiment, this electron-emitting device has a higher strength and the electron emission is uniform for each cathode. The conditions for the anodization and anodic oxidation may be the same as in Example 1.

【0056】メッキを行うときの電流密度は実施例1と
同様な理由で0.1〜10mA/cm2 であることが望
ましい。またメッキ時間は1〜30秒であることが望ま
しい。これは1秒より短いと導体層がほとんど被覆され
ず、30秒より長いと導体が微細骨格の間隙全体に充填
されてしまうからである。
The current density during plating is preferably 0.1 to 10 mA / cm 2 for the same reason as in Example 1. The plating time is preferably 1 to 30 seconds. This is because if it is shorter than 1 second, the conductor layer is hardly covered, and if it is longer than 30 seconds, the conductor is filled in the entire gap of the fine skeleton.

【0057】[0057]

【発明の効果】以上説明したように本発明によれば、強
度が強く、均一な電子放出ができる電子放出素子を提供
することができる。
As described above, according to the present invention, it is possible to provide an electron-emitting device having high strength and capable of uniform electron emission.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例1に係る電子放出素子の製造
工程の模式的断面図。
FIG. 1 is a schematic sectional view of a manufacturing process of an electron-emitting device according to a first embodiment of the present invention.

【図2】 本発明の実施例2に係る電子放出素子の製造
工程の模式的断面図。
FIG. 2 is a schematic cross-sectional view of the manufacturing process of the electron-emitting device according to the second embodiment of the present invention.

【図3】 本発明の実施例2に係る電子放出素子の製造
工程断面図。
FIG. 3 is a sectional view of a manufacturing process of the electron-emitting device according to the second embodiment of the present invention.

【図4】 本発明の実施例3に係る電子放出素子の製造
工程の模式的断面図。
FIG. 4 is a schematic cross-sectional view of the manufacturing process of the electron-emitting device according to the third embodiment of the present invention.

【図5】 本発明の実施例3に係る電子放出素子の製造
工程断面図。
FIG. 5 is a sectional view of a manufacturing process of the electron-emitting device according to the third embodiment of the present invention.

【図6】 従来の電子放出素子の断面図。FIG. 6 is a sectional view of a conventional electron-emitting device.

【符号の説明】[Explanation of symbols]

1…Si基板 3…Al電極 4…Si微細骨格 5…間隙 6…陽極酸化膜 7…導体領域 31…酸化Si膜 32…電極層 41…導体層 DESCRIPTION OF SYMBOLS 1 ... Si substrate 3 ... Al electrode 4 ... Si fine skeleton 5 ... Gap 6 ... Anodized film 7 ... Conductor area 31 ... Si oxide film 32 ... Electrode layer 41 ... Conductor layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 棚本 哲史 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 中本 正幸 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Tanamoto 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center (72) Inventor Masayuki Nakamoto Small, Kawasaki-shi, Kanagawa Muko Toshiba Town No. 1 Inside Toshiba Research and Development Center, a stock company

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の主面に形成された微細骨格
と、 この微細骨格の間隙に充填された導体領域の電子放出陰
極とを備えたことを特徴とする電子放出素子。
1. An electron-emitting device comprising: a fine skeleton formed on a main surface of a semiconductor substrate; and an electron-emitting cathode in a conductor region filled in a gap of the fine skeleton.
【請求項2】 半導体基板の主面に形成された微細骨格
の電子放出制御ゲ−トと、 前記微細骨格の間隙に充填された導体領域の電子放出陰
極とを備えたことを特徴とする電子放出素子。
2. An electron comprising an electron emission control gate of a fine skeleton formed on a main surface of a semiconductor substrate and an electron emission cathode of a conductor region filled in a gap of the fine skeleton. Emissive element.
【請求項3】 半導体基板の主面に形成された微細骨格
の電子放出陰極と、 前記微細骨格の間隙に充填された導体領域とを備えたこ
とを特徴とする電子放出素子。
3. An electron emitting device comprising an electron emitting cathode having a fine skeleton formed on a main surface of a semiconductor substrate, and a conductor region filled in a gap of the fine skeleton.
【請求項4】 半導体基板の主面に形成された微細骨格
の電子放出陰極と、 前記微細骨格の間隙に充填された導体領域の電子放出制
御ゲ−トとを備えたことを特徴とする電子放出素子。
4. An electron comprising an electron emission cathode having a fine skeleton formed on a main surface of a semiconductor substrate, and an electron emission control gate of a conductor region filled in a gap of the fine skeleton. Emissive element.
【請求項5】 前記微細骨格と前記導体領域との間に陽
極酸化膜の絶縁分離体が形成されたことを特徴とする請
求項1、2、3または4記載の電子放出素子。
5. The electron-emitting device according to claim 1, wherein an insulating separator of an anodic oxide film is formed between the fine skeleton and the conductor region.
【請求項6】 前記微細骨格のエッチングによって前記
導体領域の側面が露出されたことを特徴とする請求項1
または2記載の電子放出素子。
6. The side surface of the conductor region is exposed by etching the fine skeleton.
Alternatively, the electron-emitting device according to item 2.
【請求項7】 半導体基板の主面に形成され、導体層が
被覆された微細骨格の電子放出陰極を備えたことを特徴
とする電子放出素子。
7. An electron-emitting device comprising an electron-emitting cathode of a fine skeleton formed on the main surface of a semiconductor substrate and covered with a conductor layer.
JP13148894A 1994-06-14 1994-06-14 Electron emission device Pending JPH07335116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13148894A JPH07335116A (en) 1994-06-14 1994-06-14 Electron emission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13148894A JPH07335116A (en) 1994-06-14 1994-06-14 Electron emission device

Publications (1)

Publication Number Publication Date
JPH07335116A true JPH07335116A (en) 1995-12-22

Family

ID=15059170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13148894A Pending JPH07335116A (en) 1994-06-14 1994-06-14 Electron emission device

Country Status (1)

Country Link
JP (1) JPH07335116A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001086685A1 (en) * 2000-05-11 2001-11-15 Matsushita Electric Industrial Co., Ltd. Electron emission thin film, plasma display panel comprising it and method of manufacturing them
WO2002037518A1 (en) * 2000-11-06 2002-05-10 Fujitsu Limited Field-emission cathode and method for manufacturing the same
WO2004079766A1 (en) * 2003-03-06 2004-09-16 Matsushita Electric Industrial Co., Ltd. Electron-emitting device, phosphor light-emitting device and image drawing device
JP2011233531A (en) * 2003-03-26 2011-11-17 Alcatel-Lucent Usa Inc Device with group iii-nitride and method for fabricating the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001086685A1 (en) * 2000-05-11 2001-11-15 Matsushita Electric Industrial Co., Ltd. Electron emission thin film, plasma display panel comprising it and method of manufacturing them
US7161297B2 (en) 2000-05-11 2007-01-09 Matsushita Electric Industrial Co., Ltd. Electron emission thin-film, plasma display panel comprising it and method of manufacturing them
US7911142B2 (en) 2000-05-11 2011-03-22 Panasonic Corporation Electron emission thin-film, plasma display panel and methods for manufacturing
WO2002037518A1 (en) * 2000-11-06 2002-05-10 Fujitsu Limited Field-emission cathode and method for manufacturing the same
US7030545B2 (en) 2000-11-06 2006-04-18 Fujitsu Limited Field emission cathode with emitters formed of acicular protrusions with secondary emitting protrusions formed thereon
KR100701476B1 (en) * 2000-11-06 2007-03-29 후지쯔 가부시끼가이샤 Field-emission cathode and method for manufacturing the same
WO2004079766A1 (en) * 2003-03-06 2004-09-16 Matsushita Electric Industrial Co., Ltd. Electron-emitting device, phosphor light-emitting device and image drawing device
US7163429B2 (en) 2003-03-06 2007-01-16 Matsushita Electric Industrial Co., Ltd. Method for manufacturing electron-emitting material
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USRE47767E1 (en) 2003-03-26 2019-12-17 Nokia Of America Corporation Group III-nitride layers with patterned surfaces

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