JPH07334374A - Interruption detection processor - Google Patents

Abstract

PURPOSE:To provide the interruption detection processor for reducing the deceleration of execution speed and the memory consumption of a real computer caused by the detection processing of interruption to a software program to be executed by an emulator. CONSTITUTION:At an interruption handier part 4 to be started from the real computer corresponding to the generation of interruption, an instruction code storage control means 43 saves an instruction code for a prescribed length from the leading address of an instruction code B following an instruction code A, where the interruption is generated, and an instruction code reloading means 44 reloads this instruction code for the prescribed length into a jump instruction code 6 to an interruption preprocessing part 5 and recovers the instruction code A in the middle of execution later. Next, the following jump instruction code 6 is executed, the processing of the interruption preprocessing part 5 is started, an instruction code write back means 51 writes back the jump instruction code 6 to this saved instruction code for the prescribed length, and an interruption detecting means 52 detects the generation of interruption at a real computer and its kind and reports that information to an interruption processing part 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator for executing a software program having an interrupt processing means on a computer having a different processor architecture, and detecting an interrupt generated by the computer and notifying the interrupt processing means of the interrupt. The present invention relates to a detection processing device.

[0002]

2. Description of the Related Art In order to execute a software program on a computer having a different processor architecture, a software program code sequence is translated into an instruction code sequence of the computer, and the computer executes the translated instruction code sequence to execute the software program. An emulation method and a translation method are generally known as means for executing (hereinafter, a computer that executes a translated instruction code string is referred to as an “actual computer”). The software program before translation is executed on a virtual computer realized by an emulator based on an emulation method or a translation method executed on a real computer. It should be noted that the translation method may be included in the emulation method in a broad sense, but in the present invention, they will be described separately for the purpose of explaining the problems of the conventional technology and the improvements of the invention.

In the virtual machine, the hardware interrupt of the real machine occurs asynchronously with the execution of the software program on the virtual machine. Also, since interrupt processing in the virtual machine is realized by one process on the virtual machine, when a hardware interrupt of the real machine occurs, the process on the virtual machine being executed will It is necessary to shift to interrupt processing without fail. Therefore, in order to detect the occurrence of an interrupt in synchronization with the execution of an instruction code on a virtual machine, prepare a flag that indicates whether an interrupt has occurred using a memory or a register. It is necessary to include in the translated code of the real computer the code that detects the presence or absence of an interrupt by checking the state of. This makes it possible to reliably shift from a process being executed on a virtual computer to an interrupt process for a hardware interrupt generated on a real computer.

The following three methods are known as this interrupt detection method. In the emulation method, the first method is the instruction code of the software program before translation, that is, the instruction code of the virtual machine (hereinafter,
This is a method of incorporating an interrupt detection process before the step of reading the "virtual code") or before the step of dispatching to the processing of each virtual code corresponding to the read virtual code. FIG. 3 shows an example of the basic operation of the emulation method. This example is a system generally used when a virtual code is defined in a stack machine in a procedural programming language. First, the virtual computer reads the virtual code (step S1), then dispatches to the processing of the virtual code corresponding to the read virtual code (step S2), and then executes the processing of the read virtual code. Yes (step S3). When the above process is completed, the same process is repeated for the next virtual code to proceed the process.

FIG. 4 shows an example in which interrupt detection processing is added to the method of FIG. 3 described above. As shown in FIG. 4, the interrupt detection process is generally performed before the dispatch process (step S0) for the following reason. That is, when the interrupt detection process is performed on the virtual code, that is, when it is performed in step S3, control is transferred to the interrupt process at the stage where the virtual code process is interrupted, and the interrupted original execution state is restored. Interrupts must be between executions of virtual code because recovery is difficult.

The second method is to incorporate the interrupt detection processing code into the translated object code string of the real computer corresponding to the virtual code in the translation method. FIG. 5 shows an example of the correspondence relationship between the virtual code string 80 by the translation method and the object code string of the real computer translated from the virtual code string 80 and stored in the real computer cache 81. The translation method is applied to a software program to be executed in order to improve the lack of the execution performance of the emulation method, and speeds up the execution performance. The translation is executed for each procedure when a control transfer such as a procedure call or a return occurs. Further, if the procedure is translated each time it is called, the processing time required for the translation becomes an overhead, and the practical execution performance of the software program may not be obtained. Therefore, the result of translation can be cached for each procedure and reused to reduce the overhead due to translation. In other words, by the cache, the procedure of the virtual computer once translated can be executed at high speed as the procedure realized by the object code of the real computer in the second and subsequent executions. Therefore, the higher the reuse rate of the cached procedure, the higher the speed of the translation method.

FIG. 6 shows an example in which the interrupt detection processing code 82 is incorporated in the object code string translated and stored in the real computer cache 81 of the real computer shown in FIG. As shown in FIG. 6, in order to minimize the interrupt wait by the same method as the emulation method, it is necessary to include the interrupt detection processing code 82 in each instruction code of the object code of the real computer corresponding to the virtual code. This method is not practical because the code amount is increased and the execution speed is significantly reduced by adding the interrupt detection processing code 82.

The third method is to incorporate the interrupt detection processing code only in the control transfer and the backward jump. This method is used for applications that emphasize the minimization of reduction in execution speed. However, if the virtual code does not contain a control transfer or a backward jump for some time, the interrupt wait may be extended. However, in the actual object code, control transfer or backward jump appears in dozens of instructions at the longest, so it is practically used except when it is used for a critical purpose when the timing of interrupt processing is critical. There are often no problems with the above.

[0009]

In the first method described above, that is, in the emulation method, before the step of reading the virtual code or before the step of dispatching to the processing of each virtual code corresponding to the read virtual code. In the method of performing interrupt detection processing, the execution speed of the software program is reduced by executing the interrupt detection processing even when no interrupt occurs, and the code amount is reduced by expanding the interrupt detection processing on the memory. Inevitable increase. In the second method described above, that is, in the translation method, the method of incorporating the interrupt detection processing code into the translated object code string of the real computer corresponding to the virtual code is the same as the first method described above. There's a problem. Further, in the above-mentioned third method, that is, in the method of incorporating the interrupt detection processing limited to the control transfer and the backward jump, the waiting time from the time when the interrupt occurs to the interrupt processing may be extended.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt detection processing device that reduces the execution speed and the memory consumption of a real computer that accompany an interrupt detection process for a software program executed by an emulator.

[0011]

In order to achieve the above object, in the interrupt detection processing device of the present invention, an interrupt handler unit activated from a real computer when an interrupt occurs in the real computer generates an interrupt. Rewriting means for rewriting the instruction code of a predetermined length from the start address of the instruction code subsequent to the instruction code being executed on the real computer to the jump instruction code, and the instruction code of the predetermined length rewritten by the rewriting means. Storage control means for saving, wherein the interrupt preprocessing unit of the jump destination of the jump instruction code output by the rewriting means saves the jump instruction code rewritten by the rewriting means by the storage control means. A write-back means for writing back an instruction code of a prescribed length and the occurrence and type of an interrupt in a real computer are detected and interrupted by the interrupt processing means. Comprising generating and an interrupt detection means for notifying that type.

[0012]

In the interrupt detection processing device of the present invention having the above-described structure, in the interrupt handler section activated by the real computer when an interrupt occurs, a predetermined length from the start address of the instruction code being executed in the real computer where the interrupt has occurred. The instruction code of the predetermined length is rewritten to a jump instruction code to the interrupt preprocessing unit, and the jump instruction code of the instruction code of the saved predetermined length is written in the interrupt preprocessing unit. The code is written back to detect the occurrence of the interrupt and its type, and notify the interrupt processing means. Therefore, the interrupt detection processing code for realizing the interrupt detection means can be incorporated in the interrupt preprocessing unit, so that the interrupt detection processing code is incorporated in the instruction code string of the actual computer other than the interrupt preprocessing unit. No need. Further, the processing of the interrupt preprocessing unit including the interrupt detection unit is executed by the rewriting unit of the interrupt handler unit activated by the occurrence of an interrupt, rewriting the instruction code of the predetermined length into a jump instruction. Therefore, in the normal processing in which no interrupt occurs, the processing of the interrupt detecting means is not executed at all. In addition, since the interrupt detection unit of the interrupt preprocessing unit that is executed after the execution of the instruction code being executed is detected and the type of interrupt in the real computer is detected, the interrupt processing unit is notified.
The interrupt processing means can be executed before the subsequent instruction code is executed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of an interrupt detection processing device of the present invention. The virtual machine used as an example defines a virtual code as a stack machine based on a procedural programming language. The virtual computer memory 1 stores a software program code sequence before translation, that is, a virtual computer code (hereinafter abbreviated as “virtual code”) sequence. The data length of the virtual code is variable, and one virtual code requires one or more address areas. The real computer memory 2 stores an instruction code sequence obtained by translating a virtual code sequence into an object code of the real computer. One virtual code is translated into one or more object codes of a real computer. Moreover, one instruction code is associated with one virtual code. Therefore, one instruction code is composed of one or more object codes of the real computer. The map table 3 stores a pair of the start address of each virtual code stored in the virtual computer memory 1 and the start address of each instruction code of the real computer memory 2 corresponding to each virtual code. There is. This map table 3 calculates the start address of the corresponding instruction code of the real computer memory 2 from the address of the virtual computer memory 1 and, conversely, the start address of the virtual code of the corresponding virtual computer memory 1 from the address of the instruction code. Used to do.

The interrupt handler unit 4 is a software program called by the operating system of the real computer when a hardware interrupt occurs, and the interrupt position specifying unit 42 and the instruction code storage control unit 4 are provided.
3 and instruction code rewriting means 44. The interrupt position specifying means 42 obtains the value of the program counter of the real computer at the time when the interrupt occurs from the execution environment storage unit 21, refers to the map table 3 from this value, and refers to the virtual computer memory 1 at which the interrupt occurred. Of the virtual code A and the instruction code A of the real computer memory 2, and further refers to the map table 3 from the instruction code A to specify the subsequent instruction code B. The value of the program counter indicates the address of the real computer memory 2 of the object code next to the object code that has been executed by the time the processing is transferred to the interrupt handler unit 4 due to the occurrence of an interrupt. The instruction code storage control unit 43 stores an instruction code of a predetermined length (equal to the length of a jump instruction code described later) from the start address of the subsequent instruction code B rewritten by the instruction code rewriting unit 44. It is a means to evacuate to 22. The instruction code rewriting unit 44 is a unit that rewrites an instruction code of a predetermined length from the start address of the instruction code B into a jump instruction 6 to the interrupt preprocessing unit 5.

The interrupt preprocessing unit 5 performs preprocessing required for shifting to the processing in the interrupt processing unit 7, and includes an instruction code write-back unit 51, an interrupt detection unit 52 and an interrupt process activation. It is configured to include the means 53. Instruction code writing back means 5
Reference numeral 1 is a means for rewriting the jump instruction 6 to the instruction code of the above-mentioned predetermined length saved in the instruction code storage unit 22 and returning the instruction code B of the real computer memory 2 to the state before the interruption. When an interrupt occurs in the real computer, the real computer sets a flag indicating the type of hardware interrupt that has occurred in the interrupt register. The interrupt detection means 52 refers to the interrupt register and sets a flag corresponding to the type of the interrupt in the interrupt flag register 11 of the virtual machine memory 1 to notify the interrupt processing means of the virtual machine that an interrupt has occurred. Notify the type.

The interrupt process starting means 53 executes scheduling by the scheduler of the virtual machine, determines the order of execution of the generated interrupt in the virtual machine, and further executes the scheduling to start the next interrupt process. Of the virtual code C, that is, the address of the virtual code C of the virtual code string 71 is determined. Normally,
Interrupt processing is executed with the highest priority. Further, the interrupt process starting means 53 prepares data such as parameters and attributes which are determined by the scheduling and are necessary for executing the procedure to be executed next. When the object code of the real computer corresponding to the virtual code to be executed next is not in the cache of the real computer, it is newly translated and stored in the cache. Further, the interrupt processing activation means 53 refers to the map table 3 from the address of the virtual code C, the address of the first instruction code to be executed next, that is, the interrupt processing instruction code string 73.
The address of the instruction code C is determined.

The jump instruction 6 is an instruction code of a predetermined length (equal to the length of the jump instruction 6) following the instruction code being executed in the real computer memory 2 in which the interrupt has occurred.
By the instruction code rewriting means 44 of the interrupt handler unit 4,
It is an instruction code obtained as a result of rewriting to the jump instruction code to the interrupt preprocessing unit 5.

The interrupt processing unit 7 is a virtual code string 7 for interrupt processing.
1, an interrupt processing map table 72, and an interrupt processing instruction code string 73. The interrupt processing unit 7 performs processing of actual resource operations such as hardware associated with interrupt processing, and this interrupt processing is also converted into object code of a real computer by translation and executed. Interrupt processing virtual code string 7
1 is a part of the virtual code sequence of the procedure of the virtual computer prepared for each type of interrupt, and the virtual code C is
It is the virtual code at the beginning of the interrupt process for which an interrupt request was made. The interrupt process map table 72 is a map table of the interrupt process virtual code sequence 71 and the interrupt process instruction code sequence 73. The interrupt processing instruction code string 73 is an instruction code string on the real computer memory 2 corresponding to the interrupt processing virtual code string 71.

The interrupt flag register 11 determines the type of interrupt generated by the real computer by the interrupt detection means 52 in order to perform the processing corresponding to the type of interrupt generated by the real computer in the virtual computer. This is a register for notifying the means. The execution environment storage unit 21 is
This is a storage unit that saves the program execution environment data required when the process on the real computer shifts to the interrupt process due to the occurrence of the interrupt and returns to the original process on the real computer again. The value of the program counter when the interrupt occurs is also included in the storage data of the execution environment storage unit 21. The instruction code storage unit 22 is a storage unit for saving the instruction code rewritten by the instruction rewriting unit 44.

Next, the operation of the embodiment of the interrupt detection processing device of FIG. 1 configured as described above will be described with reference to FIG. While the instruction code A stored in the real computer memory 2 is being executed (step S11), the I / I of the real computer is
Control is transferred to the interrupt handler unit 4 when a hardware interrupt is generated from O or the like (step S12).

Next, the interrupt handler unit 4 disables interruption of subsequent processing. Next, the interruption position specifying means 42 of the interruption handler unit 4 obtains the value a of the program counter of the real computer at the time of interruption from the execution environment storage unit 21 (step S13), and maps from the value a. Table 3
And the value a is a value between the start address of the instruction code A and the start address of the instruction code B, it is known that an interrupt occurs during execution of the instruction code A in the real computer memory 2 ( Step S14). The search here is
The address of the real computer memory 2 included in the map table 3 is searched in the order of address, or by binary search or the like.

Next, the interrupt position specifying means 42 searches the map table 3 and specifies the virtual code A of the virtual computer memory 1 corresponding to the instruction code A. Virtual code A
If the type of instruction is jump or control transfer, the next instruction may not be executed, so this interrupt is canceled. That is, the instruction is not rewritten and the operation returns to the instruction code A. This operation causes an interrupt to be missed once, but since the timer interrupt enters every several tenths of a second, the interrupt process once missed can be performed when the timer interrupt is entered. In the virtual machine of the embodiment, the interrupt timing is set for each execution of each virtual code, a register is prepared in order to determine the interrupt type, and each bit of the register indicates which interrupt has occurred. Use as a flag. Therefore, even if you miss the interrupt,
The interrupt missed at the next interrupt process will also be processed, and the timer interrupt always enters as described above, so an interrupt process wait occurs, but there is usually no problem. Further, the interrupt position specifying means 42 specifies the virtual code B to be executed next, because the address after the address of the virtual code A stored in the map table 3 is the virtual code B, and further, Then, the start address of the instruction code B stored in the real computer memory 2 corresponding to the virtual code B is specified by referring to the map table 3 from the address of the virtual code B (step S15).

Next, the instruction code storage control means 43 has an instruction code equal to the length of the jump instruction 6 from the start address of the instruction code B specified in step S15 to the interrupt preprocessor 5, that is, the instruction code B. The area including the object code at the head of the is stored in the instruction code storage unit 22 of the real computer memory 2 (step S16).

Next, the instruction code rewriting means 44 rewrites the contents of the start address of the instruction code B into the jump instruction 6 to the interrupt preprocessing section 5 (step S17). After the above processing in the interrupt handler unit 4 is completed, the instruction code A that is being executed is returned (step S18). When the processor of the real computer has an instruction cache, the instruction cache is rewritten, so that processing such as flushing of the instruction cache is required.

Next, the real computer executes the rest of the instruction code A which is being executed, and shifts to the execution of the subsequent instruction code B.
Since the subsequent instruction code B has been rewritten to the jump instruction 6 by the instruction code rewriting means 44, the instruction code B jumps to the interrupt preprocessor 5 (step S19). Next, the instruction code write-back means 51 of the interrupt pre-processing unit 5 makes the jump instruction 6
Is written back to the instruction code saved in the instruction code storage unit 22 by the instruction code storage control means 43, and the instruction code B
To the state before the interruption occurred (step S20). Next, the interrupt detecting means 52 sets the type of the hardware interrupt generated in the real computer in the interrupt flag register 11 of the virtual computer memory 1 and notifies the virtual computer of the occurrence of the interrupt (step S21).

Next, the interrupt process starting means 53 executes scheduling by the scheduler of the virtual machine,
The execution order of the generated interrupts in the virtual computer is determined (step S22), and by executing the scheduling, the top virtual code address of the interrupt process to be executed next, that is, the address of the virtual code C of the virtual code string 71 is determined. (Step S23), referring to the map table 3 from the address of the virtual code C, the address of the first instruction code of the interrupt process to be executed next, that is, the instruction code C of the instruction code sequence 73 of the interrupt process The address is determined (step S24). Next, interrupt processing starting means 5
Since No. 3 shifts to the processing of the interrupt processing unit 7, it jumps to the address of the instruction code C (step S25).

After that, the interrupt processing unit 7 executes and when the interrupt processing unit 7 finishes the process, the scheduler normally operates again (step S26), and the instruction code B of the interrupted real computer memory 2 is executed. Is executed (step S2
7). The processing is executed as described above. Although the instruction code having the same length as the jump instruction 6 is saved and written back in the above embodiment, if the area that can be rewritten by the jump instruction 6 is included in the saved and written back area, It may be a region longer than the length.

[0028]

According to the interrupt detection processing apparatus of the present invention, an interrupt handler unit activated by a real computer when an interrupt occurs generates an instruction code subsequent to the instruction code being executed in the real computer in which the interrupt occurred. By rewriting the jump instruction code to the interrupt preprocessor and performing interrupt detection processing in the interrupt preprocessor of the jump destination, interrupt detection processing is performed only when an interrupt occurs, so interrupts are not generated normally. In processing, there is no reduction in execution speed due to interrupt detection processing. Further, since the interrupt detection processing code for realizing the interrupt detection means may be incorporated only in the interrupt preprocessing section, the object code amount of the real computer hardly increases due to the interrupt detection processing. Also,
Since the processing of the interrupt processing unit is executed before the subsequent instruction code is executed, the waiting time of the interrupt processing will not be extended.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an interrupt detection processing device of the present invention.

FIG. 2 is a flowchart showing the overall operation of the embodiment shown in FIG.

FIG. 3 is a flowchart showing an operation of a conventional emulation method.

FIG. 4 is a flowchart showing the operation of a conventional method in which an interrupt detection process is incorporated in the emulation method of FIG.

FIG. 5 is an explanatory diagram showing an example of translation in a conventional translation method.

FIG. 6 is a diagram showing a conventional method in which an interrupt detection process is incorporated into an example of translation of the translation system shown in FIG. 5;

[Explanation of symbols]

 1 virtual machine memory 2 real machine memory 3 map table 4 interrupt handler section 5 interrupt preprocessing section 6 jump instruction 7 interrupt processing section 11 interrupt flag register 21 execution environment storage section 22 instruction code storage section 42 interrupt position specification Means 43 Instruction code storage control means 44 Instruction code rewriting means 51 Instruction code write back means 52 Interrupt detection means 53 Interrupt processing activation means 71 Interrupt virtual code string 72 Interrupt processing map table 73 Interrupt processing instruction code string 80 Virtual Code Sequence 81 Real Computer Cache 82 Translation Interrupt Detection Processing Code

Claims (1)

[Claims] 1. In order to execute a software program having an interrupt processing means on a computer having a different processor architecture, the software program code string is translated into an instruction code string of the computer, and the computer executes the instruction code string. In the emulator for executing the software program having the interrupt processing, the interrupt handler unit activated by the computer when the interrupt occurs in the computer is a successor to the instruction code being executed in the computer where the interrupt occurs. Rewriting means for rewriting a predetermined length instruction code from the start address of the instruction code to a jump instruction code, and storage control means for saving the predetermined length instruction code rewritten by the rewriting means, The output from the rewriting means A write-back means for rewriting the jump instruction code rewritten by the rewriting means to the instruction code of the predetermined length saved by the storage control means, An interrupt detection processing device for detecting the occurrence of an interrupt and its type, and notifying the interrupt processing means of the occurrence of the interrupt and its type.