JP3766772B2 - Information processing apparatus, exception recovery processing method, and recording medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus, an exception recovery processing method, and a recording medium, and more particularly, to an apparatus and method for controlling an operation of exception recovery processing for dealing with errors and exceptional conditions that occur during normal processing. It is suitable for use.
[0002]
[Prior art]
In the current computer system, if an error occurs in executing a program or if an exceptional condition is met, processing different from the original program is performed to solve the problem. From the original program to continue the process. In general, when an error has occurred, an exception has occurred and processing for solving the problem is called exception recovery processing.
[0003]
If an exception occurs during normal processing, control of the processor is transferred to a processing program called an exception handler different from the original program. In the exception handler, exception recovery processing is performed such that the problem causing the exception is processed and resolved, and then the original program is resumed.
[0004]
FIG. 7 is a flowchart showing the operation of a conventional exception handler. If an exception occurs during normal processing, the processor writes the information of the program counter at the time of the exception occurrence, the state of the processor, the cause of the exception, etc. to the register, so that the processor operation before the exception occurs Save information. Then, the processor transitions from the user state to the supervisor state (privileged state), and shifts the processing from a normal application program to an exception handler as shown in FIG.
[0005]
In FIG. 7, in step S21, processing for eliminating the exception factor is performed based on information such as the factor of the exception occurrence stored in the register when the exception occurs. When the elimination of the cause of the exception is completed, the process proceeds to step S22, and the original instruction (exception that caused the exception on the normal application program is generated based on the value of the program counter saved in the register when the exception occurred. Return to cause instruction).
[0006]
For example, it is assumed that an exception related to memory access of an MMU (Memory Management Unit) occurs in the load instruction (2: ld) in the program shown in FIG. In this case, the load instruction (2: ld) in this program is transferred to the exception handler processing program and the processing shown in FIG. 7 is performed. After the problem that caused the exception is resolved, recovery from the exception is realized by returning to the original load instruction (2: ld) that is the exception-causing instruction and restarting the processing of the original program.
[0007]
Further, in recent processor microarchitectures, techniques such as time direction parallelization (for example, a pipeline method) and space direction parallelization (for example, a superscalar processor) are employed in order to improve processor processing performance. Is done. FIG. 9 shows the state of processing when the program of FIG. 8 is pipeline-operated.
[0008]
In the example of FIG. 9 representing the pipeline operation, D means an instruction decode stage, E means an operation execution stage, C means a memory access stage, and W means a register write stage. In the example of FIG. 9, the pipeline operation is realized by immediately starting the decoding process of the next instruction when the decoding process of one instruction is completed.
[0009]
[Problems to be solved by the invention]
When the processor is performing a pipeline operation, if the time from execution of one instruction to writing the result in a register is different for each instruction, the instruction completion order is guaranteed to be in program order. Things get harder. That is, in the example of FIG. 9, the load instruction (2: ld) on the second line requires five stages of DECCW for processing, whereas the subtract instruction (3: sub) on the third line has three stages of DEW. The process ends, and the load instruction requires a longer processing time. For this reason, the subtraction instruction on the third line is completed earlier than the load instruction on the second line.
[0010]
Assume that an exception occurs in the write stage in the load instruction (2: ld) on the second line during such a pipeline operation. In this case, for the subtraction instruction (3: sub) next to the load instruction that is an exception-causing instruction, writing to the register is completed before the exception occurs, and the execution of the subtraction instruction has already been completed. Yes. In this case, if exception recovery processing is performed according to the flow shown in FIG. 7, after completion of the load instruction (2: ld) returned from the exception recovery processing, the already completed subtraction instruction (3: sub) is executed again. Will end up.
[0011]
In order to eliminate such an inconvenience, it is conceivable to implement a mechanism that guarantees the completion order in the program by hardware even when performing a pipeline operation. For example, it is possible to guarantee that the instruction completion order will be the program order by adopting a method such as delaying the execution start timing for an instruction that results in processing earlier. It is possible to prevent the inconvenience of re-execution of already executed instructions upon return.
[0012]
However, such a method increases the number of instruction execution cycles, which is a penalty in terms of processor performance. If a hardware mechanism is provided to guarantee the completion order of instructions, the mechanism for exception recovery becomes complicated and the circuit scale increases. In general, since the occurrence frequency of exceptions is low, it is uneconomical to put excessive hardware resources in the exception recovery mechanism. Therefore, current processors that require high performance often do not guarantee the completion order of instructions with hardware.
[0013]
On the other hand, there has been proposed a software function that prevents the inconvenience of re-execution of already executed instructions upon return from exception recovery processing. In the example of FIG. 9 above, in order to return correctly from exception recovery processing, after removing the cause of the exception for the load instruction (2: ld) on the second line where the exception occurred, Return and execute the load instruction (2: ld), then skip the already executed third line subtraction instruction (3: sub) and resume processing from the fourth line addition instruction (4: add) It is something to be made.
[0014]
FIG. 10 is a flowchart showing the operation of the exception handler when instructions are not completed in the program order. In this case, if an exception occurs during normal processing, the processor counts the value of the program counter at the time of the exception, the unexecuted instruction that comes first after the exception-causing instruction (in the example of FIG. By writing information such as the address of the add instruction (4: add) on the line, the state of the processor, the cause of the exception that has occurred, etc., to the register, the operation information of the processor before the exception is saved. Then, the processor shifts from the user state to the supervisor state, and shifts the processing from the normal application program to the exception handler as shown in FIG.
[0015]
In FIG. 10, in step S31, processing for eliminating the exception factor is performed based on information such as the factor of the exception occurrence stored in the register when the exception occurs. When the elimination of the exception factor is completed, the process proceeds to step S32, and the exception-causing instruction is read from the memory and executed based on the value of the program counter saved in the register when the exception occurs. Thereafter, the process proceeds to step S33, and the process returns to the original application program process from the uncompleted instruction based on the address of the unexecuted instruction saved in the register when the exception occurs.
[0016]
Thus, when returning from exception recovery processing, after removing the cause of the exception, it is necessary to perform processing for executing only the exception-causing instruction by some method before restarting the processing of the original program. Conventionally, in order to realize this, the following method has been adopted.
(1) A method of analyzing an exception-caused instruction to be executed and emulating the instruction using a plurality of instruction sequences prepared in advance.
(2) A self-preparing area for replacing instructions in the instruction sequence of the exception handler, copying the exception-causing instruction you want to execute, and executing the exception-causing instruction by executing the copied instruction Method by modified code.
[0017]
FIG. 11 is a flowchart showing a process for re-executing a single exception-causing instruction by instruction emulation. In FIG. 11, in step S41, an exception-causing instruction is acquired from the memory based on the value of the program counter saved when the exception occurred. In step S42, the acquired exception cause instruction is analyzed, and step S43 is performed according to the analysis result. _-1 ~ S43 _-n One of the emulation processes is executed.
[0018]
For example, step S43 _-1 This process indicates a process of reading 1 byte of data from the memory into the register. Step S43 _-2 This process indicates a process of reading 2 bytes of data from the memory into the register. _-3 This process indicates a process of reading 4 bytes of data from the memory into the register. In FIG. 11, only the data load instruction and the store instruction are shown as an example of emulation for each instruction. However, actually, arithmetic instructions such as addition / subtraction and multiplication / division are also provided. An appropriate one is selected and executed according to the analysis result.
[0019]
FIG. 12 is a flowchart showing a process for re-executing a single exception-causing instruction using self-modifying code. In FIG. 12, in step S51, an exception-causing instruction is acquired from the memory based on the value of the program counter saved when the exception occurred. In step S52, the acquired exception cause instruction is copied to a memory area prepared in advance separately from the exception handler on the memory using a load / store instruction.
[0020]
Next, in step S53, the cache memory is flushed and invalidated. Cache flushing refers to the process of reflecting the data stored in the data cache memory on the main memory. Cache invalidation refers to the process of invalidating the instructions stored in the instruction cache memory. To tell.
[0021]
By performing such cache flushing and invalidation processing, it is possible to prevent the instruction before copying to the storage area on the main memory from being read from the cache memory and executed, and to copy the exception-caused instruction. It can be read from the storage area of the main memory and executed.
[0022]
In step S54 after the process of step S53, the process moves to the storage area where the exception-causing instruction is copied, and in step S55, the exception-causing instruction is executed. In the copy destination storage area, a return instruction is stored immediately after the exception-causing instruction, and after execution of the exception-causing instruction, the process immediately returns to the processing of the original exception handler in step S56. As a result, the process proceeds to step S33 in FIG. 10, the already executed instruction is skipped, and the process is restarted from the unexecuted instruction.
[0023]
However, in the method of emulating instructions, many instructions are required to analyze and emulate the instructions, which increases the execution time of exception recovery and increases the code size. There was a problem. There is also a problem that the code size of the exception handler becomes enormous because it is necessary to be able to emulate all instructions that generate exceptions.
[0024]
In the method using the self-modifying code, since many current computer systems use a cache memory, cache flushing and invalidation operations are required to use the self-modifying code. However, since these processes require a lot of execution time, there is a problem that the processing speed of exception recovery decreases. In addition, if the cache is invalidated, the cached instruction in the original program sequence is invalidated, so that the cache performance when the original program is executed is reduced, and the overall processing speed is also reduced. There was a problem of being lowered.
[0025]
In a computer system using a processor that performs a pipeline operation, the present invention increases the circuit scale when it is attempted to implement correct exception recovery processing by hardware, particularly when the completion of each instruction is different from the program execution order. This is designed to solve the conventional problem of causing a hindrance to increase the operating frequency and reducing the processing speed when trying to implement it with software, and to improve the processing speed of exception recovery with less hardware For the purpose.
[0026]
[Means for Solving the Problems]
When an exception occurs, the information processing apparatus of the present invention obtains at least one instruction word or instruction address of an instruction word of the exception-causing instruction and an incomplete execution instruction that has been interrupted due to the occurrence of the exception. Means for holding; Furthermore, when returning from exception recovery processing to normal processing, it is necessary to re-execute an exception-causing instruction or an instruction that has not yet been executed. Means for executing processing in accordance with the stored instruction word or the instruction word existing at the stored instruction address.
The re-execution instruction may be included in an instruction sequence for exception recovery processing.
[0027]
Since the present invention comprises the above technical means, it is possible to realize the re-execution process required when returning from the exception recovery process to the normal process only by executing one re-execution instruction. There is a need for complicated processing such as preparing instruction-specific emulations in advance and selectively executing one of the emulations by interpreting the instruction word or performing cache flushing and invalidation operations. Disappear.
[0028]
According to another feature of the present invention, when an exception-causing instruction is re-executed, the instructions are sequentially processed according to the instruction sequence of the exception recovery process, and the re-execution instruction written therein is simply executed. Therefore, it is not necessary to rewrite the value of the program counter to the address value of another storage area in which the exception cause instruction to be re-executed is stored, and the exception cause instruction is re-executed without accessing the other area. It becomes possible.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a processor (information processing apparatus) to which the exception recovery processing method according to the first embodiment is applied.
In FIG. 1, reference numeral 10 denotes a memory, which stores programs such as application programs and exception handlers. Reference numeral 20 denotes an instruction fetch unit, 30 denotes an instruction analysis execution control unit, 40 denotes an instruction execution unit such as an ALU (arithmetic logic unit), and 50 denotes a register unit.
[0030]
The instruction fetch unit 20 includes a program counter 21, an instruction register 22, and a selector 23. The instruction fetch unit 20 reads instruction words one by one from the memory 10 on the basis of the instruction address indicated by the program counter 21 during execution of normal processing and exception recovery processing in which no exception has occurred, and selects them from the selector 23. Are stored in the instruction register 22 via the instruction analysis execution control unit 30. On the other hand, when returning from the exception recovery process to the original normal process, the instruction word of the exception-caused instruction supplied from the register unit 50 is selected by the selector 23, and the instruction register 22 is used to interpret the instruction word to control the instruction analysis execution. To the unit 30.
[0031]
The instruction fetch unit 20 programs the supplied instruction address when a branch destination instruction address is supplied from the instruction analysis execution control unit 30 or when the leading address of an exception handler is supplied in response to the occurrence of an exception. Write to counter 21 In other cases, the value of the program counter 21 is incremented to sequentially read out the next instruction word.
[0032]
The instruction analysis execution control unit 30 includes a decoder 31 that analyzes the instruction word supplied from the instruction fetch unit 20, an exception processing control unit 32 that controls exception recovery processing according to the analysis result of the instruction word, and the instruction word And an execution control unit 33 that controls the instruction execution unit 40 according to the analysis result. Among these, the execution control unit 33 controls the instruction execution unit 40 in accordance with the instruction of the instruction word supplied from the instruction fetch unit 20 and analyzed by the decoder 31, and executes various processes such as calculation, branching, data load / store, etc. To do.
[0033]
For example, when the supplied instruction word is an arithmetic instruction, the instruction execution unit 40 controls the data value read from the memory 10 according to the designated address or the register unit 50 based on the control from the execution control unit 33. An operation is executed based on a data value read from a general-purpose register (not shown). When the supplied instruction word is a branch instruction and the branch condition is satisfied, the execution control unit 33 supplies the instruction address of the branch destination to the instruction fetch unit 20.
[0034]
When the supplied instruction word is a load instruction or a store instruction, the execution control unit 33 controls the instruction execution unit 40 to store the data in the storage area corresponding to the designated address on the memory 10. Reading or writing of data (data of a general register (not shown) in the register unit 50) is performed.
[0035]
Further, when any problem or the like (for example, an error such as division by zero or data overflow) occurs in the process of executing the operation by the instruction execution unit 40, the exception processing control unit 32 receives the notification and receives the notification. The instruction execution unit 40 and the register 50 are controlled to execute exception recovery processing.
[0036]
That is, when the exception processing control unit 32 detects the occurrence of an exception, it supplies the instruction fetch unit 20 with the exception handler start address corresponding to the detected exception content, and sets the address in the program counter 21. In addition, an instruction such as instruction cancellation is issued to the instruction execution unit 40, and processing for writing the information described below to each of the registers 51 to 54 in the register unit 50 is performed. Thereafter, the processor transits from the user state to the supervisor state, and executes exception recovery processing according to the instruction address of the exception handler set in the program counter 21.
[0037]
The register unit 50 includes a general-purpose register (not shown) that holds data used for operations of the instruction execution unit 40 and registers 51 to 54 that hold data used for exception recovery processing described below. 20, the instruction analysis execution control unit 30 and the instruction execution unit 40 read or write data to these registers. In addition, since the exchange of data between the instruction execution unit 40 and the register unit 50 is general, the illustration is omitted here. The exception recovery processing registers 51 to 54 will be described below.
[0038]
The exception instruction word register 51 is a register for holding the instruction word of the exception-causing instruction when an exception occurs. The state register 52 is a register that holds the state of the processor (user state, supervisor state, etc.) before the occurrence of the exception. The factor register 53 is a register that holds the cause of the exception that has occurred. The return address register 54 is a register that holds an instruction address in the original program that returns from the exception recovery process, and stores the address of the unexecuted instruction that comes first after the exception-causing instruction. The values of these registers 51 to 54 are all set when an exception occurs.
[0039]
Further, during the execution of the exception recovery process, the exception processing control unit 32 reads from the memory 10 according to the program counter 21 that is sequentially incremented, and the exception handler instruction interpreted by the decoder 31 is in the middle of the exception handler. It is determined whether or not an instruction re-execution instruction (hereinafter referred to as a REI instruction) unique to the present embodiment incorporated in (the part where exception recovery processing ends).
[0040]
When it is determined that the instruction read from the memory 10 is the REI instruction, the exception cause read from the exception instruction word register 51 is switched by switching the selection state of the selector 23 in the instruction fetch unit 20 to the A side. Control to select an instruction. After executing this exception-causing instruction, the remaining state of the exception handler (return processing to the original program) is executed by returning the selection state of the selector 23 to the B side.
[0041]
In other words, after executing the exception-causing instruction, the exception processing control unit 32 changes the processor state to the original user state based on the value of the state register 52, and also returns the instruction in the original program from the exception recovery processing. The address is read from the return address register 54 and set in the program counter 21 of the instruction fetch unit 20. As a result, the instruction fetch unit 20 sequentially reads out the instruction words of the original program from the memory 10 based on the instruction address set in the program counter 21 and executes them in the instruction analysis execution control unit 30.
[0042]
Next, the operation of the processor shown in FIG. 1 will be described by taking as an example a case where a program is pipelined as shown in FIG.
When in the user state where no exception has occurred, the instruction fetch unit 20 reads the instruction word of the program from the memory 10 on the basis of the instruction address indicated by the program counter 21, and selects the read instruction word as the selector 23 and the instruction register. The instruction analysis execution control unit 30 is supplied to the instruction analysis execution control unit 30.
[0043]
The instruction analysis execution control unit 30 interprets the supplied instruction word by the decoder 31, and the execution control unit 33 controls the instruction execution unit 40 according to the instruction of the instruction, thereby executing processing of the program. If no exception occurs in this user state, the processor repeats the above operation by pipeline processing. However, when the instruction analysis execution control unit 30 detects the occurrence of an exception, the exception processing control unit 32 in the instruction analysis execution control unit 30 controls the instruction fetch unit 20 and the register unit 50 to perform the following exception recovery processing. I do.
[0044]
First, the exception handling control unit 32 stores an exception-causing instruction when an exception occurs in the exception instruction word register 51. In the example of FIG. 9, since an exception has occurred in the load instruction (2: ld) on the second line, the instruction word of this load instruction is stored in the exception instruction word register 51 as an exception causing instruction. In addition, the exception processing control unit 32 stores the state of the processor before the occurrence of the exception in the state register 52 and stores the cause of the generated exception in the factor register 53.
[0045]
Further, the exception processing control unit 32 stores, in the return address register 54, the address of the unexecuted instruction that comes first after the exception-causing instruction as the instruction address in the original program that returns from the exception recovery process. In the example of FIG. 9, when an exception occurs at the write stage of the load instruction (2: ld) on the second line, the subtraction instruction (3: sub) on the next third line has already been executed, Further, the add instruction (4: add) on the next fourth line has not yet been processed. Therefore, the address of the addition instruction in the fourth row is stored in the return address register 54.
[0046]
Next, the exception processing control unit 32 supplies the instruction fetch unit 20 with the leading address of the exception handler corresponding to the generated exception, and sets the value in the program counter 21. Through the above processing, the processor transitions from the user state to the supervisor state. The processor that has transitioned to the supervisor state reads the instruction word of the exception handler to the instruction fetch unit 20 according to the start address of the exception handler set in the program counter 21, and the read instruction word is transmitted via the selector 23 and the instruction register 22. To the instruction analysis execution control unit 30.
[0047]
The instruction analysis execution control unit 30 repeats the operation of executing the instruction words sequentially supplied toward the final address of the exception handler unless an REI instruction is generated during the processing of the exception handler. However, when the exception cause is finished and the REI instruction is read from the memory 10 during the operation of the exception handler, the exception processing control unit 32 controls to execute the REI instruction.
[0048]
That is, the exception processing control unit 32 switches the selection state of the selector 23 from the B side to the A side, thereby causing an exception causing instruction (load instruction (2: ld)) held in the exception instruction word register 51 when an exception occurs. ) Is selected by the selector 23 and supplied to the instruction analysis execution control unit 30 via the instruction register 22. As a result, the instruction execution unit 40 executes the supplied exception cause instruction based on the control of the instruction analysis execution control unit 30.
[0049]
Then, after executing the exception cause instruction based on the REI instruction in this way, the exception processing control unit 32 returns the selection state of the selector 23 to the B side, so that the remaining processing of the exception handler (return to the user state) Process). That is, when the processing of the exception-causing instruction is completed, the instruction analysis execution control unit 30 executes the exception return instruction of the exception handler read from the memory 10.
[0050]
At this time, the instruction analysis execution control unit 30 reads the instruction address (addition instruction (4: add)) in the original program that returns from the exception recovery process from the return address register 54, and sets it in the program counter 21. The instruction fetch unit 20 reads an instruction word during normal operation from the memory 10 based on the instruction address set in the program counter 21 and supplies the instruction word to the instruction analysis execution control unit 30. As a result, the processor transitions from the supervisor state to the user state, and the instruction execution unit 40 executes the remaining processing of the program corresponding to the normal operation.
[0051]
With this operation, after exception recovery is performed in the exception handler in response to the occurrence of the exception, only one exception-causing instruction (load instruction (2: ld)) is executed, and the already executed subtraction instruction ( 3: sub) can be skipped and processing can be resumed from the next unexecuted addition instruction (4: add). That is, as shown in the flowchart of FIG. 10, after the exception cause is eliminated in step S31, only the exception cause instruction is executed in step S32, and the unfinished instruction is returned to the processing of the original program in step S33. Is possible.
[0052]
FIG. 2 is a flowchart showing the processing of this embodiment in which a single exception-causing instruction is re-executed in step S32. As shown in FIG. 2, in this embodiment, when the REI instruction is read from the memory 10 in accordance with the value of the program counter 21 that is sequentially incremented from the head address of the exception handler, the REI instruction is executed in step S1. Just do it.
[0053]
As described above in detail, according to the present embodiment, one REI instruction in which processing for executing only an exception-causing instruction when returning from the exception handler to the processing of the original program is incorporated in the exception handler. It can be realized simply by executing. As a result, emulation for each instruction is prepared in advance as shown in FIG. 11, and one of the emulations is selectively executed by interpreting the instruction word, or the cache is flushed as shown in FIG. And the need to perform invalidation operations.
[0054]
Further, in this embodiment, when re-executing an exception-causing instruction, it is only necessary to sequentially process the instruction according to the sequence of the exception handler and simply execute the REI instruction written therein, as shown in the flowchart of FIG. In addition, it is not necessary to rewrite the value of the program counter 21 to the address value of another area on the memory 10 to which the exception causing instruction to be re-executed is copied, and the exception causing instruction is re-executed without accessing the other area. Can be executed.
[0055]
As a result, it is possible to re-execute the exception-causing instruction with extremely simple processing as compared with the prior art, thereby improving the exception recovery processing speed and reducing the exception handler code size.
[0056]
Further, since the value of the program counter 21 is not rewritten to the address of the instruction to be re-executed, after the operation of the exception causing instruction is completed based on the REI instruction, the instruction described next to the REI instruction is continuously executed. The continuity of execution of the original program can be maintained. Further, since cache invalidation is not necessary, it is possible to prevent a decrease in cache performance when the original program is executed.
[0057]
Further, according to the present embodiment, the function of executing only an exception-causing instruction based on the REI instruction can be realized by adding few hardware resources such as the exception instruction word register 51 and the selector 23. In terms of control, the exception-causing instruction is written to the exception instruction word register 51 when an exception occurs, the exception-causing instruction is read from the exception instruction word register 51 when the REI instruction is executed, and the instruction fetch unit 20 is read. It is only necessary to add a few steps of transfer.
[0058]
(Second Embodiment)
FIG. 3 is a block diagram illustrating a configuration example of a processor (information processing apparatus) to which the exception recovery processing method according to the second embodiment is applied. In FIG. 3, the same reference numerals as those shown in FIG. 1 have the same functions, and thus detailed description thereof will be omitted.
[0059]
As shown in FIG. 3, in the second embodiment, instead of the exception instruction word register 51 used in the first embodiment shown in FIG. The exception instruction address register 55 is provided. Further, a selector 24 for selecting an instruction address is provided instead of the selector 23 for selecting an instruction word. The selector 24 selects the B side except when the REI instruction is executed in the exception handler, and selects the A side when the REI instruction is executed.
[0060]
In this embodiment, when the occurrence of an exception is detected by the instruction analysis execution control unit 30, the instruction fetch unit 20 determines the instruction address of the exception-causing instruction based on the notification from the exception processing control unit 32 (program when an exception occurs). (The value set in the counter 21) is stored in the exception instruction address register 55. Thereafter, according to the instruction address of the exception handler supplied from the exception processing control unit 32 and newly set in the program counter 21, the exception processing control unit 32 executes exception recovery processing.
[0061]
In this embodiment, when the exception cause is finished and the REI instruction is read from the memory 10 during the operation of the exception handler, the exception processing control unit 32 changes the selection state of the selector 24 from the B side to the A side. Switch. As a result, the instruction address of the exception-causing instruction held in the exception instruction address register 55 when the exception occurs is supplied to the memory 10, and the instruction word of the exception-causing instruction is read from the corresponding address and supplied to the instruction fetch unit 20. Like that.
[0062]
Then, the instruction fetch unit 20 supplies the instruction word of the exception-caused instruction read from the memory 10 to the instruction analysis execution control unit 30. Accordingly, the instruction analysis execution control unit 30 controls the instruction execution unit 40 to execute the supplied exception cause instruction. After executing the exception-causing instruction, the exception processing control unit 32 returns the selection state of the selector 24 to the B side so that the remaining processing of the exception handler (return processing to the user state) is executed. To.
[0063]
Also in the second embodiment configured as described above, the same effect as in the first embodiment can be obtained.
[0064]
(Third embodiment)
FIG. 4 is a block diagram showing a configuration example of a processor to which the exception recovery processing method according to the third embodiment is applied. In FIG. 4, components having the same reference numerals as those shown in FIG. 1 have the same functions, and thus detailed description thereof will be omitted.
[0065]
As shown in FIG. 4, in the third embodiment, in addition to the exception instruction word register 51 used in the first embodiment shown in FIG. An instruction word register 56 is provided for holding an instruction word of an unexecuted instruction whose execution has not been completed to the end due to the occurrence of.
[0066]
The third embodiment configured as described above is effective, for example, when a pipeline operation is performed as shown in FIG. That is, recent processors often execute a plurality of instructions simultaneously as shown in FIG. 5 in order to further increase the processing speed. In the example of FIG. 5, two instructions are executed simultaneously.
[0067]
When such a pipeline operation is performed, if an instruction is executed and the time until the result is obtained is different for each instruction, when an exception occurs, The order of instructions that have been executed may be mottled. In the example of FIG. 5, when an exception occurs in the write stage of the load instruction (3: ld) on the third line, the subtract instruction (4: sub) on the fourth line and the add instruction (6: add on the sixth line) ) Has completed execution, but the division instruction (5: div) on the fifth line in the meantime has not yet been executed.
[0068]
In such a case, when returning from exception recovery processing, in addition to the re-execution of the load instruction (3: ld), which is the instruction causing the exception, the re-execution of the division instruction (5: div) that has not been executed yet After performing the above, it is necessary to resume the execution of the original program from the addition instruction (7: add) on the seventh line. Therefore, in the present embodiment, when an exception occurs, not only the instruction word of the exception-causing instruction but also the instruction word of the unexecuted instruction is stored in the instruction word register 56.
[0069]
The processing flow of the exception handler in this embodiment is as shown in FIG. In FIG. 6, in step S11, processing for eliminating the exception factor is performed. When the exception cause is resolved and the REI instruction is read from the memory 10, the instruction word of the exception-causing instruction stored in the instruction word register 56 when the exception occurs is selected by the selector 23 in step S12. Execute the cause instruction.
[0070]
Further, after execution of the exception cause instruction, the process proceeds to step S13, and the instruction word of the incomplete execution instruction stored in the instruction word register 56 when the exception occurs is selected by the selector 23 following the exception cause instruction. Execute an incomplete instruction. In step S14, it is determined whether or not there is an instruction word of an unexecuted instruction that has not been processed in the instruction word register 56. If there is an instruction word, the process returns to step S13 to repeat the same processing. The selector 23 of the instruction fetch unit 20 selects the A side from the start of the process of step S12 until the exit of the loop of steps S13 and S14.
[0071]
Thereafter, when all the instruction words of the unexecuted instructions stored in the instruction word register 56 are processed, the process proceeds to step S15, and the instruction address saved in the return address register 54 when an exception occurs is used as the basis. Then, the process returns to the original program process from the unexecuted instruction. At this time, the selector 23 switches the selection state to the B side.
[0072]
As described above, according to the third embodiment, in addition to the effects described in the first embodiment, when an exception occurs, an execution incomplete instruction that has not been executed, and execution has been completed. Even when the order of execution completion instructions is mottled, there is an advantage that only instructions that need to be re-executed upon return from exception recovery processing can be executed with simple processing.
[0073]
In the third embodiment, the instruction word register 56 stores the instruction word of the exception-causing instruction and the instruction word of the unexecuted instruction, but stores only the instruction word of the unexecuted instruction. You may do it. For example, if a floating-point operation instruction is executed on a processor that does not have a function for processing floating-point data, an exception will be generated. Will occur. In such a case, if only the instruction word of the unexecuted instruction is stored in the instruction word register 56, it is possible to skip the exception causing instruction and return to the process from the next unexecuted instruction.
[0074]
In the third embodiment, the instruction word register 56 stores the instruction word of the exception cause instruction and the instruction word of the unexecuted instruction. However, as in the second embodiment, the exception cause An instruction address register for storing an instruction address of an instruction and an instruction address of an incomplete execution instruction may be provided instead of the instruction word register 56. In this case, a selector 24 for selecting an instruction address is provided instead of the selector 23 for selecting an instruction word.
[0075]
In the third embodiment, when an exception causing instruction or an incomplete execution instruction is re-executed based on the REI instruction, if an exception occurs again in the re-executed instruction, the exception of the REI instruction Instead, an exception of an instruction re-executed by the REI instruction is detected and generated. In this case, a register for storing information indicating that an exception has occurred in the re-executed instruction may be provided.
[0076]
The information processing apparatus according to the present embodiment described above is configured by a CPU or MPU of a computer, a RAM, a ROM, and the like, and can be realized by operating a program stored in the RAM or the ROM. Therefore, the program that causes the computer to perform the above functions can be realized by recording the program on a recording medium such as a CD-ROM and causing the computer to read the program. As a recording medium for recording the program, a floppy disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used in addition to the CD-ROM.
[0077]
Further, not only the functions of the above-described embodiments are realized by executing a program supplied to the computer, but the program is also used in cooperation with an OS (operating system) or other application software running on the computer. When the functions of the above-described embodiment are realized, or when all or part of the processing of the supplied program is performed by a function expansion board or a function expansion unit of the computer, the functions of the above-described embodiment are realized. Such a program is included in the embodiment of the present invention.
[0078]
Further, each of the embodiments described above is merely an example of a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. is there. In other words, the present invention can be implemented in various forms without departing from the spirit or main features thereof.
[0079]
The various aspects of the present invention are summarized as follows.
(1) instruction storage means for storing an instruction sequence;
An exception instruction word holding means for holding the instruction word of the instruction causing the exception when an exception occurs in the instruction read and executed from the instruction storage means;
Selecting means for selecting one of the instruction word read from the instruction storage means and the instruction word read from the exception instruction word holding means;
Control means for controlling the selection means so as to select an instruction word of the exception-causing instruction read from the exception instruction word holding means when a re-execution instruction of the exception-causing instruction is supplied. Information processing apparatus.
(2) The control means controls the selection means to select an instruction word read from the instruction storage means, except when a re-execution instruction for the exception-causing instruction is supplied. The information processing apparatus according to (1).
(3) The information processing apparatus according to (1), wherein the exception reexecution instruction re-execution instruction is included in an instruction sequence for exception recovery processing stored in the instruction storage means.
[0080]
(4) instruction storage means for storing an instruction sequence;
Instruction word holding means for holding an instruction word of an instruction caused by the exception or an execution incomplete instruction whose execution has been interrupted due to the occurrence of an exception when an exception occurs in an instruction read and executed from the instruction storage means; ,
Selecting means for selecting either an instruction word read from the instruction storage means or an instruction word read from the instruction word holding means;
Control means for controlling the selection means so as to select the exception cause instruction read from the instruction word holding means or the instruction word of the unexecuted instruction when the exception execution instruction re-execution instruction is supplied; An information processing apparatus comprising the information processing apparatus.
(5) The control means controls the selection means to select an instruction word read from the instruction storage means, except when a re-execution instruction for the exception-causing instruction is supplied. The information processing apparatus according to (4).
[0081]
(6) command storage means for storing a command sequence;
When an exception occurs in an instruction read and executed from the instruction storage means, an instruction word holding means for holding an instruction word of an incomplete execution instruction whose execution has been interrupted due to the occurrence of the exception;
Selecting means for selecting either an instruction word read from the instruction storage means or an instruction word read from the instruction word holding means;
Control means for controlling the selection means so as to select an instruction word of the unexecuted instruction read from the instruction word holding means when a re-execution instruction of an exception-causing instruction is supplied. Information processing apparatus.
(7) The control means controls the selection means to select an instruction word read from the instruction storage means, except when a re-execution instruction for the exception-causing instruction is supplied. The information processing apparatus according to (6).
[0082]
(8) command storage means for storing a command sequence;
An exception instruction address holding means for holding the instruction address of the instruction causing the exception when an exception occurs in the instruction read from the instruction storage means and executed;
A selection means for selecting either an instruction address read from a program counter or an instruction address read from the exception instruction address holding means as an instruction address for reading an instruction word from the instruction storage means;
And a control means for controlling the selection means so as to select an instruction address of the exception-caused instruction read from the exception instruction address holding means when a re-execution instruction for the exception-caused instruction is supplied. Information processing apparatus.
(9) The control unit controls the selection unit to select an instruction address read from the program counter except when a re-execution instruction for the exception-causing instruction is supplied. The information processing apparatus according to (8).
(10) The information processing apparatus according to (8), wherein the exception reexecution instruction re-execution instruction is included in an instruction sequence for exception recovery processing stored in the instruction storage means.
[0083]
(11) command storage means for storing a command sequence;
An instruction address holding means for holding the instruction address of an instruction caused by the exception or an execution incomplete instruction whose execution has been interrupted due to the occurrence of an exception when an exception occurs in an instruction read and executed from the instruction storage means; ,
A selection means for selecting one of an instruction address read from the program counter and an instruction address read from the instruction address holding means as an instruction address for reading an instruction word from the instruction storage means;
Control means for controlling the selection means so as to select the exception cause instruction read from the instruction address holding means or the instruction address of the unexecuted instruction when the exception execution instruction re-execution instruction is supplied; An information processing apparatus comprising the information processing apparatus.
(12) The control means controls the selection means so as to select an instruction address read from the program counter except when an exception execution instruction re-execution instruction is supplied. The information processing apparatus according to (11).
[0084]
(13) command storage means storing a command sequence;
An instruction address holding means for holding an instruction address of an execution incomplete instruction whose execution has been interrupted due to the occurrence of an exception when an exception occurs in an instruction read and executed from the instruction storage means;
A selection means for selecting one of an instruction address read from the program counter and an instruction address read from the instruction address holding means as an instruction address for reading an instruction word from the instruction storage means;
And a control means for controlling the selection means so as to select an instruction address of the unexecuted instruction read from the instruction address holding means when a re-execution instruction of an exception-causing instruction is supplied. Information processing apparatus.
(14) The control means controls the selection means so as to select an instruction address read from the program counter except when a re-execution instruction for the exception-causing instruction is supplied. The information processing apparatus according to (13).
[0085]
(15) An exception cause instruction re-execution instruction is included in the instruction sequence for exception recovery processing stored in the instruction storage means;
Holding an instruction word of the instruction that caused the exception when an exception has occurred in the instruction read and executed from the instruction storage means;
Selecting an instruction word of the exception-causing instruction held when the exception occurs as an instruction word to be executed when a re-execution instruction of the exception-causing instruction is supplied from the instruction storage unit An exception recovery processing method.
[0086]
(16) A re-execution instruction for an exception-causing instruction is included in the instruction sequence for exception recovery processing stored in the instruction storage means,
When an exception occurs in the instruction read and executed from the instruction storage means, holding the instruction address of the exception-causing instruction;
When an exception execution instruction re-execution instruction is supplied from the instruction storage means, an instruction address for reading an instruction word from the instruction storage means is used as an instruction address stored at the time of occurrence of the exception. And a step of selecting an instruction address.
[0087]
(17) Exception instruction word storage means for storing the instruction word of the exception-causing instruction in a register when an exception occurs in the instruction read and executed from the instruction storage means storing the instruction sequence;
Selecting means for selecting either an instruction word read from the instruction storage means or an instruction word read from the register;
When a re-execution instruction for the exception-causing instruction is supplied, a program for causing the computer to function as a control means for controlling the selection means to select an instruction word of the exception-causing instruction read from the register is recorded A computer-readable recording medium characterized by the above.
(18) The control means controls the selection means to select an instruction word read from the instruction storage means, except when a re-execution instruction for the exception-causing instruction is supplied. The computer-readable recording medium according to (17).
[0088]
(19) Exception instruction address storage means for storing the instruction address of the exception-causing instruction in a register when an exception occurs in the instruction read and executed from the instruction storage means storing the instruction sequence;
A selection means for selecting either an instruction address read from a program counter or an instruction address read from the register as an instruction address for reading an instruction word from the instruction storage means;
When a re-execution instruction for the exception-causing instruction is supplied, a program for causing the computer to function as a control means for controlling the selection means to select an instruction address of the exception-causing instruction read from the register is recorded A computer-readable recording medium characterized by the above.
(20) The control means controls the selection means so as to select an instruction address read from the program counter except when a re-execution instruction for the exception-causing instruction is supplied. The computer-readable recording medium according to (19).
[0089]
【The invention's effect】
According to the present invention configured as described above, the processing for instruction re-execution necessary for returning from the exception recovery processing to the original normal processing can be realized by executing only one re-execution instruction. Is possible. This eliminates the need for complicated processing such as software emulation and execution with self-modifying code, which has conventionally been necessary to re-execute instructions, and allows exception recovery processing to be performed easily.
[0090]
Further, according to the present invention, the exception recovery process described above includes the holding means for holding the instruction word or instruction address of the exception-causing instruction or the instruction that has not been executed, and the instructions that have been held when the re-executed instruction is executed. This can be realized simply by adding a small number of hardware resources such as selection means for selecting a word or instruction address.
[0091]
As described above, according to the present invention, the instruction sequence for exception recovery can be greatly reduced by adding a few hardware resources, and recovery from an exception can be easily performed. . As a result, it is possible to reduce the execution time required for exception recovery (improve exception response) and reduce the code size of the exception handler.
[0092]
According to another feature of the present invention, when an exception-causing instruction is re-executed, the instructions are sequentially processed according to the sequence of exception recovery processing, and the re-executed instruction written therein is simply executed. It is not necessary to rewrite the value of the program counter to the address value of another storage area in which the exception-causing instruction to be re-executed is stored, and the exception-causing instruction is re-executed without accessing the other area. Is possible. Therefore, exception recovery processing can be performed at high speed, and deterioration in cache performance when the original program is executed can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a processor (information processing apparatus) to which an exception recovery processing method according to a first embodiment is applied.
FIG. 2 is a flowchart illustrating a method for re-execution of an exception-causing instruction according to the present embodiment.
FIG. 3 is a block diagram showing a configuration example of a processor (information processing apparatus) to which an exception recovery processing method according to a second embodiment is applied.
FIG. 4 is a block diagram illustrating a configuration example of a processor (information processing apparatus) to which an exception recovery processing method according to a third embodiment is applied.
FIG. 5 is a diagram illustrating an example of a pipeline operation applicable to the third embodiment.
FIG. 6 is a flowchart showing the operation of an exception handler according to the third embodiment when instructions are not completed in program order.
FIG. 7 is a flowchart showing the operation of a conventional exception handler.
FIG. 8 is a diagram illustrating an example of an instruction sequence.
FIG. 9 is a diagram illustrating an example when the instruction sequence of FIG. 8 is pipelined.
FIG. 10 is a flowchart showing the operation of an exception handler when instructions are not completed in program order.
FIG. 11 is a flowchart showing conventional processing for re-executing a single exception-causing instruction by instruction emulation;
FIG. 12 is a flowchart showing a conventional process for re-executing a single exception-causing instruction by self-modifying code.
[Explanation of symbols]
10 memory
20 Instruction fetch section
21 Program counter
22 Instruction register
23, 24 selector
30 Instruction analysis execution controller
31 Decoder
32 Exception handling control unit
33 Execution control unit
40 Instruction execution unit (ALU)
50 Register section
51 Exception instruction word register
52 Status register
53 Cause register
54 Return address register
55 Exception instruction address register
56 Instruction word register

Claims (6)

An instruction storage means for storing an instruction sequence;
An exception instruction word holding means for holding the instruction word of the instruction causing the exception when an exception occurs in the instruction read and executed from the instruction storage means;
Selecting means for selecting one of the instruction word read from the instruction storage means and the instruction word read from the exception instruction word holding means;
Control means for controlling the selection means so as to select an instruction word of the exception-causing instruction read from the exception instruction word holding means when a re-execution instruction of the exception-causing instruction is supplied. Information processing apparatus. An instruction storage means for storing an instruction sequence;
An exception instruction address holding means for holding the instruction address of the instruction causing the exception when an exception occurs in the instruction read from the instruction storage means and executed;
A selection means for selecting either an instruction address read from a program counter or an instruction address read from the exception instruction address holding means as an instruction address for reading an instruction word from the instruction storage means;
And a control means for controlling the selection means so as to select an instruction address of the exception-caused instruction read from the exception instruction address holding means when a re-execution instruction for the exception-caused instruction is supplied. Information processing apparatus. In the instruction sequence for exception recovery processing stored in the instruction storage means, a re-execution instruction for the instruction causing the exception is held,
Holding an instruction word of the instruction that caused the exception when an exception has occurred in the instruction read and executed from the instruction storage means;
Selecting an instruction word of the exception-causing instruction held when the exception occurs as an instruction word to be executed when a re-execution instruction of the exception-causing instruction is supplied from the instruction storage unit An exception recovery processing method. In the instruction sequence for exception recovery processing stored in the instruction storage means, a re-execution instruction for the instruction causing the exception is held,
When an exception occurs in the instruction read and executed from the instruction storage means, holding the instruction address of the exception-causing instruction;
When an exception execution instruction re-execution instruction is supplied from the instruction storage means, an instruction address for reading an instruction word from the instruction storage means is used as an instruction address stored at the time of occurrence of the exception. And a step of selecting an instruction address. When an exception occurs in an instruction read and executed from the instruction storage means storing the instruction sequence, an exception instruction word storage means for saving the instruction word of the exception-causing instruction in a register;
Selecting means for selecting either an instruction word read from the instruction storage means or an instruction word read from the register;
When a re-execution instruction for the exception-causing instruction is supplied, a program for causing the computer to function as a control means for controlling the selection means to select an instruction word of the exception-causing instruction read from the register is recorded A computer-readable recording medium characterized by the above. An exception instruction address storing means for storing the instruction address of the instruction causing the exception in a register when an exception occurs in the instruction read and executed from the instruction storage means storing the instruction sequence;
A selection means for selecting either an instruction address read from a program counter or an instruction address read from the register as an instruction address for reading an instruction word from the instruction storage means;
When a re-execution instruction for the exception-causing instruction is supplied, a program for causing the computer to function as a control means for controlling the selection means to select an instruction address of the exception-causing instruction read from the register is recorded A computer-readable recording medium characterized by the above.

Images