JPH07334138A - Image display device - Google Patents

Abstract

PURPOSE:To suppress the scale of buffers of a system and improve the speediness and stability through simple constitution which uses inexpensive devices. CONSTITUTION:A buffer 13 for drawing has a random access port and a serial port and a buffer 14 for display has two serial ports which are usable as an input port and an output port. A plotting circuit 12 writes image data in the plotting buffer 13 through the random access port, and initializes the buffer and plots an image. A control circuit 11 controls the operation and timing of the initialization of the plotting buffer 13 by the plotting circuit 12, the drawing of the image, the transfer of image data from the plotting buffer 13 to the display buffer 14, and the transfer of image data from the display buffer 14 to a display 15. Then the initialization and plotting of the plotting buffer 13 are alternate by repeated, the transfer of the image data from the plotting buffer 13 to the display buffer 14 is performed before next initialization after plotting, and the image is repeatedly transferred to the display 15 to display images.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image display in, for example, a computer system, and particularly to an image for high-speed display suitable for three-dimensional graphics display, image display, or moving image display in a workstation. Regarding display device.

[0002]

2. Description of the Related Art As an image display device for displaying an image in a computer system, for example, a workstation
2. Description of the Related Art An image display device for performing high-speed graphics display such as three-dimensional graphics display, image display, or so-called animation display, that is, moving image display in an application is used.

Conventionally, in this kind of high-speed graphics display device, in order to prevent the display screen from being disturbed, a double buffer system which does not display the screen being drawn and uses two sets of image buffers is used. This double buffer system displays the contents of the other image buffer while drawing in one of the two image buffers, and when drawing in the one image buffer ends, the image is displayed. By switching the buffers, the one image buffer that has been drawn is used as a display buffer, the contents of the other image buffer that had been used for display are erased and initialized, and the other image buffer is next Start drawing.

This type of double buffer system will be described in detail. FIG. 12 shows the configuration of a double buffer system in a general graphics device.
The display system shown in FIG. 12 includes a control circuit 1, a drawing circuit 2, a first buffer 3, a second buffer 4, a first switching device 5, a second switching device 6 and a display 7. The first and second buffers 3 and 4, respectively, are frame buffers as dedicated memories into which image data to be drawn are written and image data output is taken out for display. These first and second buffers 3 and 4 usually have a random access port and a serial port, respectively. First or second
Initialization of the buffer 3 or 4 (clearing the screen) and drawing / writing of the image data are performed through the random access port, and output for displaying the image data from the first or second buffer 3 or 4. Is done through the serial port.

The first switching unit 5 switches to which of the first and second buffers 3 and 4 the drawing and writing by the drawing circuit 2 is performed. The second switch 6 outputs the display output to the display 7 to the first and second buffers 3.
Switch from which of 4 and 4 is taken out. The switching operation of the first and second switching devices 5 and 6 is alternately and complementarily controlled by the control circuit 1. That is, in the control circuit 1, the first switch 5 has the first buffer 3
Is selected, the second switch 6 selects the second buffer 4, and when the first switch 5 selects the second buffer 4, the second switch 6 is selected. Is the first buffer 3
Control to select. The control circuit 1 controls the drawing circuit 2 in conjunction with the operation of the first switching unit 5 to initialize the first or second buffer 3 or 4 selected by the first switching unit 5 and Draw and write. The display 7 displays image data as a visible image using a display element such as a CRT (cathode ray tube) and a liquid crystal panel.

FIG. 13 shows the timing relationship of initialization, drawing and display of the first and second buffers 3 and 4. As shown in FIG. 13, when the first switch 5 selects the first buffer 3 by the operation of the control circuit 1, the drawing circuit 2
Initializes the first buffer 3 and subsequently draws. During initialization and drawing of the first buffer 3, the operation of the control circuit 1 causes
The second switch 6 selects the second buffer 4, the display output is taken from the second buffer 4, and the display 7
Is displayed.

When the drawing of the first buffer 3 is completed, the control circuit 1 selects the second buffer 4 which has been used for the display by the first switch 5 and the drawing circuit 2 makes the second buffer. Initialization for 4 and subsequent drawing are performed. During the initialization and drawing of the second buffer 4, the operation of the control circuit 1 causes the second switch 6 to select the first buffer 3 for which drawing has already been completed, and the display output is Taken out of the first buffer 3,
The display is displayed on the display 7.

When the drawing of the second buffer 4 is completed, the first switching unit 5 selects the first buffer 3 which has been used for the display until then, and the initialization and the drawing of the first buffer 3 are completed. During the initialization and drawing of the first buffer 3, the display output is taken out from the second buffer 4 which has already been drawn, and the display 7 is displayed.
Is displayed in. Thereafter, in the same manner, the above operation is alternately repeated, and the initialization, drawing and display of the buffer are cyclically performed. Therefore, the state in the middle of drawing is not displayed.

As described above, the first and second buffers 3
Since and 4 alternately perform the same operation, a memory having an equivalent function and configuration is used.

[0010]

However, the display of image data in such a conventional system has the following problems.

Recently, image data itself such as three-dimensional graphics data and image data used for display has become large in capacity with the increase in resolution, and
For example, switching display of a large number of images such as animation display is required to be performed at higher speed. For such high-speed display of images, it is desirable to reduce the time required for initialization of the image buffer (that is, clearing the screen) and drawing as much as possible, and to reduce the influence of the drawing time on the display. Therefore, for example, in FIG.
As in the double buffer system shown in FIG. 13 and FIG. 13, screen initialization and drawing operations are performed independently so as not to overlap display operations.

In order to achieve higher speed image display in such a system, it is possible to prepare three sets of image buffers to form a triple buffer system. In this case, as shown in FIG. 14, the display of the first buffer and the initialization of the second buffer are performed during the drawing of the third buffer. Since the initialization of the second buffer is completed during the drawing of the third buffer, when the drawing of the third buffer is completed, the buffers are switched to display the third buffer and the drawing of the second buffer is completed. Done this second
The first buffer is initialized during drawing of the buffer.
In this case, since three operations of drawing, initialization and display are performed in parallel by three buffers, high-speed display can be achieved, but a video RAM (RAM: RAM: which is a memory generally used as an image buffer for display). Random access memory), or V-RAM, is expensive. In addition, for example, in a workstation that handles high-resolution data, the required capacity and number of V-RAMs increase significantly, and the ratio of buffers in the entire system becomes extremely large.

Further, in the case of a model or system in which the degree of high speed requirement is relatively low, even if it is desired to adopt a double buffer structure in order to stabilize the display to the minimum, it is the same as the buffer because of the problems of price and the number of memories. It may not be possible to prepare two V-RAMs with specifications. In such a case, it is desired to achieve high speed and stability comparable to a double buffer configuration using two V-RAMs having the same specifications by using a device that is cheaper than the V-RAM.

It is an object of the present invention to provide an image display device which has a simple structure using a cheaper device, can suppress the size of a buffer in the system, and can effectively achieve high speed and stability. is there.

[0015]

A first device according to the present invention is used for drawing means for drawing image data, a random access port that can be used for writing image data, and serial output of image data. A first image buffer for drawing, in which image data is drawn and formed by the drawing means through the random access port, and used for serial input and serial output of image data, respectively. First possible
And a second serial port, and a second display image in which the image data stored in the first drawing image buffer is transferred from the serial output port via the first serial port. An image display device comprising: a buffer; and image data stored in the image buffer for second display, which is transferred via the second serial port, and display means for displaying the image data. (Claim 1).

In the above-mentioned image display device, initialization of the image buffer for the first drawing, drawing formation of image data, and the image buffer for the first drawing to the image buffer for the second display Data transfer is repeated cyclically, and the first data transfer is performed after the first data transfer.
The image display may be performed by data transfer from the second image buffer for display to the display means during initialization of the image buffer for drawing and image data drawing (claim 2). . Further, there may be included means for making the input and output data transfer rates of the second image buffer for display correspond to the display scanning rate of the display means (claim 3).

The first image buffer for drawing may be composed of a plurality of image buffers in which drawing and formation of image data are performed alternately and complementarily (claim 4). A second device according to the present invention is provided with a drawing unit for drawing image data, a display unit for displaying an image, a random access port that can be used for writing the image data, and a serial output of the image data. A first image buffer for drawing, which has at least a serial output port that can be used, and a second image for display, which has first and second serial ports that can be used respectively for serial input and serial output of image data. An image is drawn and formed in the first drawing image buffer by the buffer and the drawing means via the random access port, and the image data stored in the first drawing image buffer is transferred to the serial output port. Via the first serial port to the image buffer for the second display via the second display Is the image data stored in the image buffer from the second serial port image display apparatus and a control means for displaying is transferred to the display unit (claim 5).

The control means initializes the image buffer for the first drawing, draws and forms image data, and transfers data from the image buffer for the first drawing to the image buffer for the second display. Transfer is cyclically repeated, and the initialization of the image buffer for the first drawing after the data transfer and the drawing of the image data from the image buffer for the second display to the display means are performed. Means for causing a data transfer for display may be included (claim 6). The control means may further include means for causing the input and output data transfer rates of the second display image buffer to correspond to the display scanning speed of the display means (claim 7).

The first image buffer for drawing may be composed of a plurality of image buffers in which drawing and formation of image data are alternately and complementarily performed (claim 8). A third device according to the present invention has at least a drawing means for drawing image data, a random access port that can be used for writing image data, and a serial output port that can be used for serial output of image data. A first drawing image buffer in which image data is drawn and formed by the drawing means via the random access port;
The random access port has at least a random access port that can be used for writing image data and a serial output port that can be used for serial output of image data, and is used alternately with the image buffer for the first drawing. A second image buffer for drawing in which image data is drawn and formed by the drawing means via the first and second serial ports that can be used for serial input and serial output of the image data, respectively. The first
And image data stored in the second image buffer for drawing are alternately transferred from the respective serial output ports through the first serial port when writing from the random access port is not performed. The third display image buffer and the image data stored in the third display image buffer are stored in the second display image buffer.
And an image display device for displaying the image data transferred via the serial port.

Transfer of image data from the second image buffer for drawing to the third image buffer for displaying while drawing and forming the image data in the first image buffer for drawing. While initializing the image buffer for the second drawing and drawing and forming the image data of the image buffer for the second drawing, the first
Image data is transferred from the drawing image buffer to the third display image buffer and the first drawing image buffer is initialized, and these operations are alternately repeated, and Image display is performed by data transfer from the third image buffer for display to the display means during a data transfer period from the first or second image buffer for drawing to the image buffer for third display. You may do so (Claim 10). It may further include means for making the input and output data transfer rates of the third display image buffer correspond to the display scanning rate of the display means (claim 11).

The drawing means is a first drawing means for initializing and drawing the first image buffer, and a second drawing means for initializing and drawing the second image buffer.
The drawing means may be included (claim 12).

A fourth device according to the present invention is a drawing device for drawing image data, a display device for displaying an image, a random access port that can be used for writing the image data, and a serial image data. First and second image buffers for drawing having at least a serial output port that can be used for output, and first and second serial ports that can be used for serial input and serial output of image data, respectively. 3 image buffers for display and the drawing means alternately draws and forms images in the first and second image buffers for drawing via the random access port, and these first and second image buffers are formed.
When the image data stored in the image buffer for drawing is alternately written via the serial output ports and not written from the random access port, the image data stored in the first serial port is output from the first serial port. And the image data stored in the third image buffer for display is transferred to the second image buffer for display.
And a control means for transferring and displaying the data from the serial port to the display means (claim 13).

The control means moves from the second image buffer for drawing to the third image buffer for display while drawing and forming the image data in the first image buffer for drawing. Of the first drawing image data while transferring the second image data and initializing the image buffer for the second drawing, and drawing and forming the image data of the image buffer for the second drawing. Means for transferring image data from the buffer to an image buffer for third display and initializing the image buffer for first drawing, and repeating the operations alternately; For displaying an image by data transfer from the third image buffer for display to the display means during the data transfer period from the second image buffer for drawing to the image buffer for third display. Means and Optionally comprise (claim 1
4). The control means may further include means for making the input and output data transfer rates of the third display image buffer correspond to the display scanning rate of the display means (claim 15).

[0024]

In the image display device according to the present invention, at least one image buffer for drawing having at least a random access port that can be used for writing image data and a serial output port that can be used for serially outputting image data, and An image buffer for display having first and second serial ports that can be used respectively for serial input and serial output of image data is used, and an image is drawn by the drawing means in the image buffer for drawing via the random access port. Data is drawn and formed, and the image data in the drawing image buffer is transferred to the display image buffer from the serial output port through the first serial port and is stored in the display image buffer. Display the image data that has been created via the second serial port. Since the image data is transferred to the device and displayed, the configuration can be simplified using a less expensive device, the size of the buffer in the system can be suppressed, and high speed and stability can be effectively achieved. It becomes possible.

That is, like a so-called field memory, which has only sequential input / output ports, it is relatively inexpensive as compared with a V-RAM generally used for an image buffer, and is small in size and compact. Shape memory can be used to configure the image buffer for display,
It is possible to realize a function substantially equivalent to a conventional double buffer or triple buffer using only V-RAM.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the image display device according to the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 shows the configuration of a principle image display device according to a first embodiment of the present invention.

The image display device of FIG. 1 is configured as a double buffer system in a general graphics device, and includes a control circuit 11, a drawing circuit 12, a drawing buffer 13, a display buffer 14 and a display 15.
It is equipped with.

The drawing buffer 13 is a buffer for directly writing image data by the drawing circuit 12 to draw and form an image, and is a V-frame generally used as a frame buffer.
-Use RAM. That is, the drawing buffer 13
It has a random access port and a serial port. Initialization of the drawing buffer 13 (clearing of the screen) and drawing / writing of image data are performed via the random access port, and image data output from the drawing buffer 13 is performed via the serial port.

The display buffer 14 is the drawing buffer 1.
The image data formed in 3 is transferred from the drawing buffer 13 and is a buffer for taking out the image data, outputting the image data, and displaying the image data.
A field memory is used that is relatively inexpensive and has a small size and shape. That is, the display buffer 14 is
It has two sets of serial ports, each of which can be used as an input port and an output port. Display buffer 1
The input / output of the image data of 4 is all performed through the serial port. Therefore, the image data is transferred from the drawing buffer 13 to the serial port of the drawing buffer 13,
The data is transferred to the display buffer 14 via the serial port of the display buffer 14 in sequence.

The serial ports in the drawing buffer 13 and the display buffer 14 described above are ports for sequentially inputting and outputting video data. Since these serial ports are generally used for displaying a video image or the like, it is possible to input / output video data sequentially in accordance with display scanning and at a high video display rate.

The drawing circuit 12 writes the image data in the drawing buffer 13 via the random access port,
The drawing buffer 13 is initialized and an image is drawn.
The display 15 displays image data as a visible image using a display element such as a CRT (cathode ray tube) and a liquid crystal panel.

The control circuit 11 initializes the drawing buffer 13 by the drawing circuit 12 and draws an image, transfers image data from the drawing buffer 13 to the display buffer 14, and from the display buffer 14 to the display 15.
Control the operation and timing of the transfer of image data to. That is, the control circuit 11 alternately repeats the initialization and the drawing of the drawing buffer 13, and from the drawing buffer 13 to the display buffer 1 before the next initialization after the drawing is completed.
The image data is transferred to No. 4. Furthermore, the control circuit 11
Causes the image data transferred to the display buffer 14 to be repeatedly transferred to the display 15 almost constantly for display.

FIG. 2 shows the timing relationship of initialization, drawing, transfer and display of the drawing buffer 13 and the display buffer 14. Under the control of the control circuit 11, first, the drawing circuit 12 initializes (writes initialization data) to the drawing buffer 13 via the random access port, and subsequently writes image data to form an image. Draw. When the drawing and writing to the drawing buffer 13 via the random access port is completed, the written image data is controlled by the control circuit 11 and the drawing buffer 13 is drawn via the serial port.
To the display buffer 14. That is, the image data is transferred from the drawing buffer 13 to the drawing buffer 13
The serial port (usually used for outputting image data for display in a frame buffer using a V-RAM or the like) and the serial port of the display buffer 14 are transferred to the display buffer 14. The image data transferred to the display buffer 14 is stored in the display buffer 14
The data is transferred from the serial port to the display 15 and provided for display. When the image data in the drawing buffer 13 is transferred to the display buffer 14, the drawing buffer 13 is initialized in preparation for the next drawing, and after initialization, the next image data is drawn in the drawing buffer 13. . After that, the same operation is repeated.

The transfer speed from the drawing buffer 13 to the display buffer 14 is sufficiently high as compared with the writing to the drawing buffer 13 from the random access port for initialization. Therefore, when sequentially updating the entire screen, initialization of the drawing buffer 13 is started if at least the first line of image data is transferred from the drawing buffer 13 to the display buffer 14. be able to. In addition, since the transfer to the display buffer 14 is performed at high speed, it is possible to display even during the transfer,
Transfer and display of image data from the display buffer 14 to the display 15 are continuously and repeatedly performed.

When data is transferred from the serial port, the serial port of the drawing buffer 13 can operate faster than the random access port of the drawing buffer 13. Therefore, when sequentially drawing the entire screen, transfer and initialization can be partially processed in parallel as shown in FIG. For example, assuming that the transfer is sequentially performed from the upper part of the screen, after the transfer of the first line is completed, the random port side of the drawing buffer 13
Initialization can be started from the first line.

Drawing buffer 13 (frame buffer)
The transfer between the display buffer 14 and the display buffer 14 (field memory) has a speed performance equivalent to the output speed of the display data from the display buffer 14 to the display 15. It can be completed in about 1 second. However, if the transfer rate from the drawing buffer 13 to the display buffer 14 is set too high, as shown in FIGS. 3 to 6, the scanning process for displaying the drawing result of the same frame should be performed. Then, the drawing result of the next frame is output and displayed, and the screen flickers for a moment.

That is, assuming that the screen next to the one-frame screen as shown in FIG. 3 is the one-frame screen as shown in FIG. 4, the transfer speed from the drawing buffer 13 to the display buffer 14 is displayed. When the scanning speed is faster than scanning, the screen displayed on the display 15 is switched to the screen shown in FIG. 4 in the middle of the screen shown in FIG. 3, and the screen shown in FIG. 5 is displayed momentarily. Line number of display data at this time,
FIG. 6 shows the relationship between the line number of the transfer data and the content of the display data displayed on the display 15. According to FIG. 6, the old data is displayed up to the fourth line, but when the fourth line is displayed, the display image data is switched to the newly transferred data, and as shown in FIG.
Old and new data will be mixed in the same frame.

Such a mixture of image data in the same frame causes image flicker, but when there is no great difference between images that change at high speed, such as some kind of animation display (moving image display). May not be so problematic. However, it is generally preferable that such flicker does not occur when the image output is recorded by a VTR (video tape recorder) or the like, when the character display screen is scrolled, or the like.

In order to prevent such flicker, FIG.
As shown in, the transfer of the image data from the drawing buffer 13 to the display buffer 14 is performed at the same speed in synchronization with the display output from the display buffer 14. In this way, the same screen is always displayed during each one-screen scan, and there is no inconvenience that half the screens display different screen information.

If the image to be rewritten is part of the screen, the drawing buffer 13 to the display buffer 14
Buffer 1 for drawing after the transfer of image data to the
A part of the screen of No. 3 will be initialized. However, in such a case, since the screen area to be initialized is small,
Since the time required for the initialization is short, there is no great influence on the time until the initialization is completed.

As described above, by transferring the image data from the drawing buffer 13 to the display buffer 14 at the video display rate, it is possible to perform display substantially equivalent to the conventional double buffer structure.

Incidentally, as an example of the V-RAM which can be used as the drawing buffer 13, MB818251-7
There is a 2 Mbyte V-RAM with a model number of 0 (manufactured by Fujitsu). In the case of this V-RAM, the random access port can read and write with an access time of 70 ns and the serial port with an access time of 20 ns.

In general, a display system used in a workstation or the like has a vertical synchronizing frequency of about 76 Hz, so if the display resolution is 1280 × 1024, the number of scan lines sent to the display per second is 76 ×. (1024 + α) ≈80,000 (lines / s), and the number of dots sent to the display per second is about 80,000 × (1280 + α) ≈11,000,000 (dots / s).

Therefore, the dot clock for display, that is, the time per dot required for the display clock is 1 / 110,000≈9.0 (ns / dot). Since there is no memory element that can output data at such a speed, it is usually designed by a method of sending 4 to 5 dots at a time. For example, 9 × 4 = 36 (ns).

As an example of the field memory that can be used as the display buffer 14, HM530281 is used.
There is a field memory of the model number (made by Hitachi). In the case of this memory, the access time of the asynchronous input / output serial port is 20 ns.

When the device shown in FIG. 1 is constructed using these elements, the serial port is connected to a 4-dot clock (36n).
When operated in s), the transfer of the image data of the entire screen from the drawing buffer 13 to the display buffer 14 can be performed at the same speed as the transmission of the image data for display.
It ends in 6 seconds.

[Embodiment 2] FIG. 8 shows the structure of an image display apparatus according to a second embodiment of the present invention. The image display device in FIG. 8 is configured as a triple buffer system, and includes a control circuit 21, a drawing circuit 22, a first drawing buffer (hereinafter, referred to as “drawing A buffer”) 23, and a second drawing buffer. A buffer (hereinafter referred to as “drawing B buffer”) 24, a first switching device 25, a second switching device 26, a display buffer 27, and a display 28 are provided.

The drawing A buffer 23 and the drawing B buffer 24 are buffers for drawing and forming an image by directly writing the image data by the drawing circuit 21, and are a general V-RAM as a frame buffer. Configure using. That is, the drawing A buffer 23 and the drawing B buffer 24 have a random access port and a serial port. Image data is drawn and written in the drawing A buffer 23 and the drawing B buffer 24 through the random access port, and the image data is output from the drawing A buffer 23 and the drawing B buffer 24. It is done through the serial port.

Some V-RAMs, for example, can be initialized at high speed by using a serial port by setting initialization data in advance and supplying a clock. The drawing A buffer 23 and the drawing B buffer 24 in FIG.
RAM is used. In this case, the drawing A buffer 23
And initialization of the drawing B buffer 24 (clearing the screen)
Is performed by the control circuit 21 rather than the drawing circuit 22 through the serial port.

The first switch 25 switches to which of the drawing A buffer 23 and the drawing B buffer 24 the drawing writing by the drawing circuit 22 is performed. Second
Switch 26 of the transfer output to the display buffer 27,
The drawing A buffer 23 or the drawing B buffer 24 is selected. These first and second
The switching operation of the switching devices 25 and 26 is performed by the control circuit 21.
Are controlled alternately and almost complementarily. Control circuit 2
1 indicates that when the first switch 25 selects the drawing A buffer 23, the second switch 26 selects the drawing B buffer 24 and transfers it, and then the drawing B buffer 2
Initialize 4 at high speed. When the high-speed initialization of the drawing B buffer 24 is completed, the control circuit 21 causes the first switching unit 2
5 and the second switch 26 are switched, and the drawing B
The buffer 24 and the drawing A buffer 23 are selected.
When the first switch 25 selects the drawing B buffer 24, the control circuit 21 controls the second switch 26 to select the drawing A buffer 23.

That is, the control circuit 21 controls the drawing circuit 22 in synchronization with the switching operation of the first switching device 25, and the drawing A buffer 22 or the drawing B buffer selected by the first switching device 25. The drawing A buffer 22 that causes the buffer 23 to perform drawing / writing and is selected by the second switch 26
Alternatively, the image data in the drawing B buffer 23 is transferred to the display buffer 27 for display, and the drawing A buffer 22 or the drawing B buffer 23, which has been transferred, is initialized at high speed.

In the display buffer 27, the image data formed in the drawing A buffer 23 or the drawing B buffer 24 is transferred to the drawing A buffer 23 via the second switch 26.
Alternatively, it is a buffer for transferring the image data transferred from the drawing B buffer 24, outputting the image data for display. As the display buffer 27, a normal VR is used.
A field memory is used that is relatively inexpensive and has a small size and shape as compared with the AM. That is, the display buffer 27 has two sets of serial ports that can be used as an input port and an output port, respectively. All input / output of image data of the display buffer 27 is performed via the serial port. Therefore, the image data is the drawing A buffer 23 or the drawing B buffer 24.
From the drawing A buffer 23 or the drawing B buffer 2
4 through the serial port, the second switch 26, the display buffer 27 serial port sequentially through the display buffer 2
7 to the display 28 via the serial port of the display buffer 27.
Transferred to.

The serial ports in the drawing A buffer 23, the drawing B buffer 24, and the display buffer 27 described above can input / output video data sequentially in accordance with display scanning and at a high video display rate.

The drawing circuit 22 writes the image data in the drawing A buffer 23 or the drawing B buffer 24 through the random access port and draws the image in the drawing A buffer 23 or the drawing B buffer 24. . The display 28 displays image data as a visible image using a display element such as a CRT (cathode ray tube) and a liquid crystal panel.

The control circuit 21 is, as described above, the first circuit.
Switching of the switching unit 25 and the second switching unit 26, the drawing circuit 22 draws an image in the drawing A buffer 23 or the drawing B buffer 24, the drawing A buffer 23 or the drawing B buffer 24 to the display buffer. It controls the operation and timing of the transfer of image data to the display 27 and the transfer of image data from the display buffer 27 to the display 28. That is, the control circuit 21 controls the drawing A
The drawing of the buffer 23 and the drawing B buffer 24 is alternately repeated, and while one of the drawing A buffer 23 and the drawing B buffer 24 is drawing, the image data of the other is transferred to the display buffer 27. And initialization. Drawing A buffer 23 or drawing B buffer 24 From drawing A buffer 23 or drawing B buffer 24 to display buffer 2 before the next initialization after drawing is completed
Image data is transferred to 7. Furthermore, the control circuit 21
Causes the image data transferred to the display buffer 27 to be repeatedly transferred to the display 28 almost constantly for display.

FIG. 9 shows initialization and drawing of the drawing A buffer 23, the drawing B buffer 24 and the display buffer 27.
The timing relationship between transfer and display is shown. The display of "r" and "s" in the drawing A buffer 23 and the drawing B buffer 24 respectively indicate the random access port and the serial port, and the display of "i" and "o" in the display buffer 27 is The input and output serial ports are shown respectively. Under the control of the control circuit 21, first, the drawing circuit 22 writes image data to the drawing A buffer 23 through the random access port to form an image, thereby performing drawing. During this drawing, the control circuit 21 performs high-speed initialization of the drawing B buffer 24 using the serial port. When the drawing and writing to the drawing A buffer 23 via the random access port is completed, the written image data is transferred from the drawing A buffer 23 to the display buffer 27 via the serial port under the control of the control circuit 21. It That is, the image data is transferred from the drawing A buffer 23 to the display buffer 27 via the serial port of the drawing A buffer 23 and the serial port of the display buffer 27. The image data transferred to the display buffer 27 is transferred from the serial port of the display buffer 27 to the display 28 for display. When the image data in the drawing A buffer 23 is transferred to the display buffer 27, the drawing A buffer 23 is initialized at high speed using the serial port in preparation for the next drawing. During the transfer and initialization of the drawing A buffer 23, the drawing B buffer 2
4 is drawn. After the initialization of the drawing A buffer 23, the next image data is drawn in the drawing A buffer 23. After that, the same operation is repeated.

The image data is transferred from the drawing A buffer 23 or the drawing B buffer 24 to the display buffer 27 at a high speed, and since the image data can be displayed during the transfer, the display buffer 27 can be used. The transfer and display of the image data to the display 28 is continuously and repeatedly performed.

In the image display apparatus shown in FIG. 8, the outputs of the normal double-buffered drawing A buffer 23 and drawing B buffer 24 are passed to the display 28 via the display buffer 27 to form a triple buffer structure. Therefore, while the drawing A buffer 23 and the drawing B buffer 24 are being drawn, the other data transfer and high-speed initialization can be performed to improve the overall performance.

The initialization of the drawing buffer using the serial port as described above is suitable for sequentially rewriting and displaying the entire screen. However, in the case of rewriting display of a part of the screen like rewriting display of some windows in a so-called multi-window system, initialization must be performed for a specific part of the screen, and the initialization is performed via a random port. I have to do it. Next, a preferred embodiment in such a case will be described.

[Third Embodiment] FIG. 10 shows the structure of an image display apparatus according to a third embodiment of the present invention. The image display device of FIG. 10 is configured as a triple buffer system, and includes a control circuit 31, a first drawing circuit (hereinafter, referred to as “A”).
"Drawing circuit" 32, second drawing circuit (hereinafter, referred to as "drawing circuit")
"B drawing circuit" 33, first drawing buffer (hereinafter called "drawing A buffer") 34, second drawing buffer (hereinafter called "drawing B buffer") 35, A switch 26, a display buffer 27, and a display 28 are provided. The switch 26, the display buffer 27, and the display 28 are substantially the same as those in FIG.

The drawing A buffer 34 and the drawing B buffer 35 are buffers for drawing and forming images by directly writing image data by the A drawing circuit 32 and the B drawing circuit 33, respectively, and serve as frame buffers. It is configured by using a general V-RAM. That is, the drawing A buffer 34 and the drawing B buffer 35 have a random access port and a serial port. Image data is drawn and written in the drawing A buffer 34 and the drawing B buffer 35 through the random access port, and the image data is output from the drawing A buffer 34 and the drawing B buffer 35. It is done through the serial port. In this case, the initialization of the drawing A buffer 34 and the drawing B buffer 35 (clearing of the screen) is performed by the A drawing circuit 32 and the B drawing circuit 33, respectively, as in the case of drawing, and the initialization data is set to a random access port. It is done by writing directly through.

The A drawing circuit 32 and the B drawing circuit 33 initialize and write the drawing A buffer 34 and the drawing B buffer 35 under the control of the control circuit 31. The switch 26 transfers the transfer output to the display buffer 27 to the drawing A buffer 23 and the drawing B buffer 24.
Switch from which to take out. The switching operation of the switch 26 is controlled by the control circuit 31.

When the A drawing circuit 32 is causing the drawing A buffer 23 to draw, the control circuit 31 selects the drawing B buffer 35 by the switch 26 and transfers the data to the display buffer 27. Then, the B drawing circuit 33 initializes the drawing B buffer 35.
When the B drawing circuit 33 completes the initialization of the drawing B buffer 35, the control circuit 31 continues to the B drawing circuit 3
3 causes the drawing B buffer 35 to draw. The control circuit 31 uses the drawing B buffer 3 by the B drawing circuit 33.
When the initialization of 5 is completed, the switch 26 is switched, the drawing A buffer 34 is selected, the contents of the drawing A buffer 34 are transferred to the display buffer 27, and when the child transfer is completed, the A drawing circuit By 32, the drawing A buffer 23 is initialized. The transfer initialization of the drawing A buffer 34 and the drawing of the drawing B buffer 35 are performed within the same period.

That is, the control circuit 31 uses the A drawing circuit 3
2. The B drawing circuit 33, the drawing A buffer 34, and the drawing B buffer 35 are controlled so that the A drawing circuit 32 and the B drawing circuit 33 alternately draw and write the drawing A buffer 34 and the drawing B buffer 35, respectively. The switching unit 26 selects the side of the drawing A buffer 34 and the drawing B buffer 35 which is not used for drawing, and transfers the image data to the display buffer 27 via the switching unit 26. Then, the drawing A buffer 34 and the drawing B buffer 35, which have been transferred, are initialized by the A drawing circuit 32 and the B drawing circuit 33, respectively.

In the display buffer 27, the image data formed in the drawing A buffer 34 or the drawing B buffer 35 is transferred via the switch 26, and the image data is taken out, outputted and provided for display. It is a buffer.
As the display buffer 27, a field memory which is relatively inexpensive, small in size and shape and compact as compared with a normal V-RAM is used. That is, the display buffer 27 has two sets of serial ports that can be used as an input port and an output port, respectively. All input / output of image data of the display buffer 27 is performed via the serial port.

Therefore, the image data is transferred from the serial port of the drawing A buffer 34 or the drawing B buffer 35 to the display buffer 27 through the switch 26 and the serial port of the display buffer 27 in order, and further displayed. Data is transferred from the display buffer 27 to the display 28 via the serial port of the display buffer 27. The serial ports in the drawing A buffer 34, the drawing B buffer 35, and the display buffer 27 can input / output video data sequentially in accordance with display scanning and at a high video display rate.

The A drawing circuit 32 and the B drawing circuit 33 are
The drawing A buffer 34 and the drawing B buffer 35 are initialized and the image data is drawn and written via the random access ports.

As described above, the control circuit 31 controls the switching of the switch 26, the A drawing circuit 32 and the B drawing circuit 3.
3 draws and writes images in the drawing A buffer 34 and the drawing B buffer 35, transfers image data from the drawing A buffer 34 or the drawing B buffer 35 to the display buffer 27, and from the display buffer 27 to the display. Controls the operation and timing of the transfer of image data to 28. That is, the control circuit 31 controls the drawing A buffer 3 by the A drawing circuit 32 and the B drawing circuit 33.
4 and the drawing B buffer 35 are alternately repeated to obtain the drawing A buffer 34 and the drawing B buffer 35.
While drawing one of the images, the image data of the other is transferred to the display buffer 27 and initialized. Drawing A buffer 34 or drawing B buffer 35
Drawing A buffer 34 before the next initialization after drawing is completed.
Alternatively, the image data is transferred from the drawing B buffer 35 to the display buffer 27. Further, the control circuit 31 repeatedly and repeatedly transfers the image data transferred to the display buffer 27 to the display 28 for display.

FIG. 11 shows a drawing A buffer 23 and a drawing B buffer.
The timing relationship of initialization, drawing, transfer, and display of the buffer 24 and the display buffer 27 is shown. A for drawing
"R" in the buffer 34 and the drawing B buffer 35
The symbols "s" and "s" indicate random access ports and serial ports, and the symbols "i" and "o" in the display buffer 27 indicate input and output serial ports, respectively. FIG. 11 is different from FIG. 9 in that the drawing A buffer 34 and the drawing B buffer 35 are initialized by a random port instead of the serial port.

When the screen range to be rewritten is a part of the screen, the time required for initialization and drawing is short, and when the screen range to be rewritten is the entire screen, the time required for initialization and drawing is long. Therefore, in this system, when the screen range to be rewritten is a part of the screen, the screen can be efficiently rewritten and displayed.

In the image display apparatus shown in FIG. 11 as well, the outputs of the drawing buffer A 34 and drawing buffer B 35 of the normal double buffer configuration are passed through the display buffer 27 to the display 28 to form a triple buffer configuration. The overall performance of the bird can be improved.

[0073]

As described above, according to the present invention,
At least one image buffer for drawing, which has at least a random access port that can be used for writing image data and a serial output port that can be used for serial output of image data, and respectively for serial input and serial output of image data An image buffer for display having usable first and second serial ports is used, and image data is drawn and formed in the image buffer for drawing by the drawing means through the random access port, and the image for display is displayed. The image data in the image buffer for drawing is transferred to the buffer from the serial output port via the first serial port, and the image data stored in the image buffer for display is transferred to the second serial port. And display the image data by transferring to display means via Unishi Te, with a simple configuration using a less expensive device, suppressing the scale of the buffer in the system, yet it is possible to provide an image display device capable of effectively achieving the high speed and stability.

That is, the image display device of the present invention has only a sequential input / output port like a so-called field memory and is relatively inexpensive as compared with a V-RAM generally used for an image buffer. Moreover, it is possible to configure an image buffer for display by using a memory having a small size and a compact shape, and a function substantially equivalent to a conventional double buffer or triple buffer using only V-RAM. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the principle of an image display device according to the present invention.

FIG. 2 is a schematic diagram for explaining the operation timing of the image display device of FIG.

FIG. 3 is a schematic diagram of an old image for explaining image display when the transfer speed is higher than the display scanning speed in the image display device of FIG.

FIG. 4 is a schematic diagram of a new image for explaining image display when the transfer speed is higher than the display scanning speed in the image display device of FIG.

5 is a schematic diagram of a display image for explaining the image display when the transfer speed is higher than the display scanning speed in the image display device of FIG.

6 is a schematic diagram of data transfer timing for explaining image display when the transfer speed is higher than the display scanning speed in the image display device of FIG.

7 is a schematic diagram of data transfer timing for explaining image display when the display scanning speed and the transfer speed are the same in the image display device of FIG.

FIG. 8 is a block diagram showing a configuration of a second embodiment of the image display device according to the present invention.

9 is a schematic diagram for explaining the timing of the operation of the image display device of FIG.

FIG. 10 is a block diagram showing a configuration of a third embodiment of the image display device according to the present invention.

11 is a schematic diagram for explaining the timing of the operation of the image display device of FIG.

FIG. 12 is a block diagram showing a general configuration of an image display device using a conventional double buffer system.

13 is a schematic diagram for explaining the timing of the operation of the image display device of FIG.

FIG. 14 is a schematic diagram for explaining the timing of the operation of an image display device that is normally considered using a triple buffer system.

[Explanation of symbols]

 11, 21, 31 ... Control circuit 12, 22, 32 ... Drawing circuit 13, 23, 24, 34, 35 ... Drawing buffer 14, 27 ... Display buffer 15, 28 ... Display 25, 26 ... Switching device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/36 510 M 0834-5H V 0834-5H

Claims (15)

[Claims] 1. A drawing means (12) for drawing image data, at least a random access port that can be used for writing image data, and a serial output port that can be used for serial output of image data. A first image buffer (13) on which image data is drawn and formed by the drawing means via a random access port, and first and second serial ports that can be used for serial input and serial output of image data, respectively. A second image buffer (1) which has image data stored in the first image buffer (13) and is transferred from the serial output port through the first serial port.
4), and image data stored in the second image buffer (14) transferred via the second serial port, and display means (15) for displaying the image data. An image display device characterized by. 2. Initialization of a first image buffer (13),
Image data drawing and forming and data transfer from the first image buffer (13) to the second image buffer (14) are cyclically and repeatedly performed, and the first image buffer ( 13) during initialization and image data drawing formation, the second image buffer (1
The image display device according to claim 1, wherein image display is performed by data transfer from 4) to the display means (15). 3. Image display device according to claim 2, further comprising means for associating the input and output data transfer rates of the second image buffer (14) with the display scan rate of the display means. 4. The first image buffer is composed of a plurality of image buffers (23, 24; 34, 35) in which drawing and formation of image data are alternately and complementarily performed. 1. The image display device of 1. 5. A drawing means (12) for drawing image data, a display means (15) for displaying an image, a random access port that can be used for writing the image data, and serial output of the image data. A first image buffer (13) having at least a serial output port that can be used for a second image buffer having first and second serial ports that can be used respectively for serial input and serial output of image data ( 14), the drawing means (12) draws and forms an image in the first image buffer (13) through the random access port, and the image data stored in the first image buffer (13) is displayed. The first through the serial output port
From the serial port of the second image buffer (14)
Transfer to the second image buffer (14)
An image display device comprising: a control unit (11) for transferring the image data stored in the second serial port to the display unit (15) for display. 6. A control means (11) initializes a first image buffer (13), draws and forms image data, and from the first image buffer (13) to a second image buffer (14). Means for cyclically repeating the data transfer of the first image buffer (13) and displaying means from the second image buffer (14) during the initialization of the first image buffer (13) after the data transfer and the drawing formation of the image data. The image display device according to claim 5, further comprising means for causing data transfer for display in (15). 7. The image display according to claim 6, wherein the control means (11) further includes means for making the input and output data transfer rates of the second image buffer correspond to the display scan rate of the display means. apparatus. 8. The first image buffer is composed of a plurality of image buffers (23, 24; 34, 35) in which drawing and formation of image data are alternately and complementarily performed. 5. The image display device of 5. 9. At least a drawing means (22) for drawing image data, a random access port that can be used for writing the image data, and a serial output port that can be used for serially outputting the image data, A first image buffer (23) in which image data is drawn and formed by the drawing means through a random access port, a random access port that can be used for writing image data, and a serial that can be used for serial output of image data. A second image buffer (24) which has at least an output port and which is alternately used with the first image buffer (23) to draw and form image data by the drawing means through the random access port; , First and second which may be used for serial input and serial output of image data, respectively Having two serial ports, said first and second image buffers (23, 24)
Third image buffers (2) that are transferred from the respective serial output ports via the first serial port alternately when the image data stored in
7), and image data stored in the third image buffer (27) are transferred through the second serial port, and display means (28) for displaying the image data. An image display device characterized by. 10. Transfer of image data from the second image buffer (24) to the third image buffer (27) while drawing and forming the image data of the first image buffer (23) and While the second image buffer (24) is being initialized and the image data of the second image buffer (24) is being drawn and formed, the first image buffer (2
3) The transfer of the image data from the third image buffer (27) to the third image buffer (27) and the initialization of the first image buffer (23) are performed, and these operations are repeated alternately, and the first or second Image display by data transfer from the third image buffer (27) to the display means (15) during the data transfer period from the image buffer (23, 24) to the third image buffer (27). The image display device according to claim 9, which is performed. 11. Image display device according to claim 10, further comprising means for associating the input and output data transfer rates of the third image buffer (27) with the display scan rate of the display means. 12. The drawing means comprises a first image buffer (3
4) a first drawing means (32) for initializing and drawing and a second drawing means (33) for initializing and drawing the second image buffer (35). The image display device according to claim 9. 13. A drawing means (22) for drawing image data, a display means (28) for displaying an image, a random access port which can be used for writing the image data, and a serial output of the image data. First and second image buffers (23, 24) having at least a serial output port that can be used for, and first and second serial ports that can be used for serial input and serial output of image data, respectively. 3 image buffer (27) and the drawing means (28) through the random access port to the first and second image buffers (23,
24) images are alternately drawn and formed, and the image data stored in the first and second image buffers (23, 24) are alternately output from the serial output ports and from the random access port. Is not being written, the image data stored in the third image buffer (27) is transferred to the second image buffer (27) from the first serial port, and the image data stored in the third image buffer (27) is transferred to the second image buffer (27). An image display device, comprising: a control means (21) for transferring the data from the serial port to the display means (28) for display. 14. The control means (21) controls the second image buffer (24) to the third image buffer (27) while drawing and forming the image data of the first image buffer (23). While the transfer of the image data to the second image buffer (24) and the initialization of the second image buffer (24) are performed and the image data of the second image buffer (24) is drawn and formed,
Means for transferring image data from the first image buffer (23) to the third image buffer (27) and initializing the first image buffer (23) to alternately repeat these operations. And the first or second image buffer (23, 24) to the third image buffer (2
Image display according to claim 13, characterized in that it comprises means for effecting image display by data transfer from the third image buffer (27) to display means during a data transfer period to 7). apparatus. 15. The control means (21) further comprises means for making the input and output data transfer rates of the third image buffer (27) correspond to the display scan rate of the display means. Item 14. The image display device according to item 14.