JPH04190285A - Display device - Google Patents

Abstract

PURPOSE:To realize a smooth scroll extending over the whole display means by providing a display means divided into plural display domains and an input means, responding to a signal sent from the input means through a synchronous control means, and synchronously sending a signal showing contents to be displayed in each display domain under a specified variation mode for driving the display means. CONSTITUTION:A letter, a symbol and a figure are inputted into an input means 11, which gives a signal corresponding to the contents of the display to a display synchronizing means 12, which gives a signal to show the contents of the display to plural display control means 13a-13d (a generic name is 13), which individually drive display means 14a-14d (a generic name is 14). The number of the picture elements of the display means 14 to be driven by each of the display control means 13 is selected to a scope where a variation mode specified in the input means 11 can be sufficiently realized, and smooth scroll in the combined display means 14 can thereby be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for displaying characters and figures on a display screen formed by combining a plurality of display areas.

Conventional technology FIG. 14 shows a schematic configuration of a conventional display device.

Characters and images to be displayed are set in accordance with input signals and operation results for the input means 1.

The input means 1 provides a signal corresponding to the set display content to the display control means 2. The display control means 2 includes an input means l
In response to a signal from the controller, the display means 3 is driven to display the display content represented by the signal.

FIG. 15 is a block diagram for explaining the configuration shown in FIG. 14 in more detail. As the input means 1, a personal computer 4 is used.6The personal computer 4 transmits signals representing characters or images such as letters, symbols, or figures to a transmission line in response to operations on a keyboard, etc., according to a preset program. 5 to the display control means 2. Transmission line 5 is R8232C or RS42
It is a serial transmission line that conforms to standards such as 2. Signals via the transmission line 5 are transmitted from the personal computer 4 to the host board 6 provided in the display control means 2 according to a predetermined protocol.

The display control means 2 includes a host board 6 and a plurality of sub-boards 7a to 7n. Host board 6 provides signals to each sub-board 7a-7n. Each sub board 7a
A signal for driving the display means 3 is derived from 7n.

The display means 3 is a dot-shaped light emitting diode ([LEDJ
(sometimes abbreviated as ) are arranged in a matrix as picture elements, and the LED display 8 is further arranged in a matrix.

Each sub-board 7a to 7n has an LE of such a display means.
Each row of the matrix made up of the D display 8 is driven.

The display contents of the display means 3 are displayed in various modes, such as a still image display, a scroll display, or an animation display, according to the designation made to the input means 1. Designation of such a change mode is given to the host board 6 from the input means 1 via the transmission line 5.

The host board 6 individually gives a signal representing the content to be displayed in each row of the display means 3 to each sub-board 7a to 7n according to the change mode specified by the input means 1,
A signal for each sub-board 7a to 7n to operate synchronously is commonly given. Each sub-board 7a-7n responds to a signal from the host board 6 and synchronously drives each row of the display means 3 constituted by an LED display 8.

FIGS. 16 and 17 show signals for displaying images in the configuration shown in FIG. 15. FIG.
NT signal is shown. This signal transmits the display content for one row when a plurality of LED display devices 8 each consisting of 16 dots of LED picture elements in each vertical column and horizontal row are connected in the horizontal direction. This is a synchronization signal for

In response to the rise of this INT signal, sub-boards 7a to
7n starts deriving a signal to the display means 3. FIGS. 16(2) to 16(5) are address signals LO to L3 representing which row in each LED display 8 is selected. The period W1 of the INT signal varies depending on the number of picture elements in each row, and is, for example, about 312 μsec. Therefore, the time W2 required to apply a signal to each row of the LED display 8 is about 5 msec, which is 16 times Wl. Sub-boards 7a-7n generate address signals LO-L3 in response to the INT signal. The signal representing the display content from the host board 6 to the sub-boards 7a to 7n is the 16th
The H/S signal shown in FIG. 5 is applied to the memories provided in the sub-boards 7a to 7n during the low level period. Note that Fig. 16 (6) is the same as Fig. 16 (1) to Fig. 16 (5).
The time axis is compressed and displayed. Each sub board 7
LEDs a to 7n read the stored contents of the memory when the H/S signal is at a high level, and output signals as shown in FIG. 17 in synchronization with the INT signal, making up each row of the display means 3.
It is given to the display 8. The period W3 of this H/S signal is, for example, 80 msec, and one stationary screen is displayed on the display means 3. When performing scroll display, a screen shifted by, for example, 1 to 4 dots is displayed every cycle W3. The deviation of 4 dots in 80 m seconds is 50 in 1 second.
Corresponds to the misalignment of dots.

FIG. 17(1) to FIG. 17(4) show the address signal LO
~ represents L3. The display signal shown in FIG. 17(5) becomes high level for a time W4 after the signal for each row is derived, and the display by the LED display 8 is erased. This time W
4, the load signal shown in FIG. 17(6) is derived, and a signal is given to the means for driving the LEDs forming the row specified by the address signals LO to L3.

Problems to be Solved by the Invention In a conventional display device as shown in FIG.
The number of LED indicators 8 constituting the display means 3 increases,
In particular, when a large number of LED indicators 8 are connected in the row direction, it becomes difficult to drive the sub-boards 7a to 7n. Particularly when controlling to change the display such as scrolling, it becomes difficult for each sub-board 7a to 7n to drive many LED displays 8. For example, 5 per second
When a scrolling speed of 0 dots is achieved by software using a 16-bit CPU such as the trademark V30 provided in the sub-boards 7a to 7n, the limit is 512 dots per line. Even if a plurality of display control means 2 are used to drive the display means 3 having many LED displays 8 in order to enlarge the display screen of the display means 3, the synchronization between each display control means 2 is difficult. Therefore, smooth scrolling through the entire combined display means 3 cannot be realized.

An object of the present invention is to divide a display screen into a plurality of display areas,
An object of the present invention is to provide a display device in which each display area can be driven individually, and characters and images displayed on the entire display screen can be smoothly scrolled, animated, and the like can be displayed.

Means for Solving the Problems The present invention provides a display means for displaying a character or an image on a display screen divided into a plurality of display areas, and a method for inputting the content to be displayed by the display means and the mode of change thereof. input means for individually deriving a signal representing the displayed content for each of the display areas and deriving a signal specifying a mode of change; and a plurality of synchronization control means provided corresponding to each of the display areas. Each synchronization control means responds to the signal from the input means, synchronously derives a signal representing the content to be displayed in each display area in a specified change mode, and drives the display means. This is a display device characterized by including a synchronization control means as shown in FIG.

Function According to the present invention, the display screen of the display means for displaying characters or images is divided into a plurality of display areas. The content to be displayed by the display means and the mode of change thereof are input to the input means. A signal representing the input display content is individually derived for each display area, and is given to a synchronization control means provided corresponding to each display area. A signal specifying the mode of change inputted to the input means is commonly given to the synchronization control means. Each synchronization control means synchronizes and derives a signal representing the content to be displayed in each display area in a designated variation manner, and drives the display means. By setting the size of each display area to a size that can be sufficiently driven by the corresponding synchronization control means and configuring a large screen by combining such display areas, characters and images can be displayed even on a large screen. The change mode specified by the input means,
For example, it can be smoothly displayed using scroll display or animation display.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention. Characters and images such as letters, symbols, or figures to be displayed are set by inputting a signal to the input means 11 or the like. The input means 11 generates a signal corresponding to the display content and supplies it to the display synchronization means 12. From the display synchronization means 12, a plurality of display control means 13a to 1
6 display control means 13a to 3d (hereinafter collectively referred to as reference numeral 13) to which a signal representing display content is given;
13d drives display means 14a to 14d (hereinafter collectively referred to as reference numeral 14). That is, the display means 14 is constituted by display means 14a to 14d for displaying display areas divided into a plurality of parts. The display means 14a to 14d corresponding to each display area receive a signal representing the display content to be displayed by each display means 14a to 14d from the zero display amount period means 12 which is individually driven by the display control means 13a to 13d. The zero display amount period means 12, which is individually given to the display control means 13a to 13d, generates a signal given to the display control means 13 in synchronization. The number of picture elements of the display means 14 to be driven by each display control means 13 is
By selecting a size within a range that can sufficiently realize the change mode specified in the input means 11, it is possible to realize change modes such as smooth scrolling and animation on the combined display means 14.

FIG. 2 is a block diagram for explaining the configuration of the embodiment shown in the first figure in more detail. The input means 11 is realized by a personal computer or the like, and sends a signal to a drive board 16 provided in the display synchronization means 12 via a general-purpose bus 15. In the drive board 16, signals representing the display contents of each of the display means 14a to 14d corresponding to each display area and signals for synchronization are transmitted through signal lines 17a to 17a.
17d to receive hoards 18a to 18d (hereinafter collectively referred to as reference numeral 18). The drive board 16 supplies the input means 11 with a signal PEI to start deriving a signal via the general-purpose bus 15 . This signal PEI is used in the input means 11 as an interrupt signal.

Signals from the receive boards 18a to 18d are transmitted through signal lines 1
The host boards 20a to 20d (hereinafter collectively referred to as reference numeral 20) constituting the display control means 13 are provided via the terminals 9a to 19d. Host board 20a~
20d is a sub-hoard 21a-2na, 21b-2nb, 21c for driving the display means 14a-14d.
~2. nc.

A signal is given to 21d to 2nd (hereinafter collectively referred to as reference numeral 21). In this way, in the display means 14, display is performed synchronously in each of the plurality of display areas.

FIG. 3 is a block diagram showing the electrical configuration of the display means 14. LED display 120.14'0°220.2
40 includes an LED matrix 126 having LEDs as picture elements.
．． 146 included. LED matrix 126.146
is constructed as shown in the fourth figure. Each picture element DOO is composed of a red LED DROO and a green LED DGOO. LED matrix 126
, 146 is such a picture element DOO or the row direction AO~A
15 and column directions RO to R15; Go to G15. The column direction is driven for each red or green color. In each picture element DOO, D which is a red LED
When only ROO is driven, a red display is performed.

When only the green LED DGOO is driven, a green display is performed. D which is red and green LED
When ROO and DGOO are driven simultaneously, an orange display is performed. In this way, the LED matrix 12
6.146 can display multiple colors using a pixel matrix of 16 rows and 16 columns. The driving of each LED matrix 126, 146 in the row direction AO to A15 is
This is performed by row drive circuits 127 and 149 provided for each ED display 120 and 140. This row driving is performed by so-called dynamic driving in which the rows AO to A15 are sequentially switched and driven. Row of red LEDs RO to R1
5, red shift drive circuits 136 and 156 are provided for each display panel 120 and 140. In order to drive the green LED array GO to G15,
Green shift drive circuits 137 and 157 are provided for each display panel 120 and 140. Shift drive circuit 13
6, 137 are serially supplied with signals representing display contents from the sub-board 21. Shift drive circuit 136.137
synchronizes with the clock signal from the sub-board 21 and sequentially derives signals representing display contents to the LED display 140 at the subsequent stage. In this way, each LED indicator 12
0,140 shift drive circuit 136.156;137.
When a signal indicating display content is given to the sub-board 157, a load signal is given from the sub-board 21. When the load signal is derived, the signal to be displayed in each LED matrix 126.146 is determined by the shift drive circuit 136.156;
Latch 123,124:1B included in 137.157
3,134. LED matrix 126.
146 is caused by the signal latched in this way.
From address signals LO to L3, row drive circuit 129.14
The picture elements of one row selected by the decoder 127 composing the picture element 9 are driven.

FIG. 5 is a block diagram showing the electrical configuration of the drive board 16. The signal from the input means 11 is sent to the input circuit 31
given to. Signals from the input circuit 31 are given to a plurality of boats 32a to B2d. A signal from an oscillation circuit 33 realized by a crystal oscillator or the like is given to a signal generation circuit 34. From the signal generation circuit 34, CLKI
The CLK2 signal, the PF3 signal and the PF2 signal are generated synchronously and provided to the receive board 18. P
The EI signal is also given to the input means 11 as a data transfer start signal. A signal is applied from the input means 11 to the input circuit 31 in response to the PEI signal.

The signal generation circuit 34 outputs the PEI signal as 1. A signal frequency-divided by '2 is applied to each boat 32a to B2d. The signal generation circuit 34 further outputs a data transfer clock signal CLKI and a reference clock signal CL of the sub-board 21.
K2 is derived. The CLKI signal is also given to counter 35.

Each boat 32a to 32d is provided with a first write data buffer 36 and a second write data buffer 37, and is supplied with a data signal from the input circuit 31. The first write data buffer 36 receives the inverted signal #! from the signal generation circuit 34. 38
Activated by a signal via. The second write data buffer 37 is activated directly by a signal from the signal generation circuit 34. Therefore, the first or second write data buffer 36,37 is activated alternately. The signals from the first and second write data buffers 36 and 37 are:
provided to first and second memories 39 and 40, respectively. Writing to the first and second memories 39 and 40 is as follows:
It is controlled by a signal applied from the input means 11 via the input circuit 31. When data is written to the memory 39.40, it is stored at an address specified by an address signal applied from the input means 11 via the input circuit 31 to the first and second write address buffers 41.42. Counter 35 provides an address for specifying the store contents to be read from memory 39.40 via first and second read address buffers 43.44. The store contents read in this way are stored in the first and second
The signal is applied to four output circuits and then to the receive board 18 via successive data buffers 46 and 47. Write address buffers 41, 42 . Read address buffer 43
．． 44 and write data buffers 52 and 53 are also activated in response to a signal from signal generation circuit 34. This switching involves writing into one memory 39, 40 using a signal from the input means 11, and writing into the other memory 39, 40.
．． 40 is read out in response to an address signal from the counter 35. That is, each boat 32a to 32d of the drive board has a pair of memories 39.40, and the memories 39.40 are switched in synchronization with the PEI signal.
40 store contents on each receive board 18a to 18d.
are derived individually. The input means 11 writes to the memory of the receive board 18 that is not being read for derivation.

FIG. 6 is a block diagram showing the electrical configuration of the receive board 18. Signals from the drive board 16 are applied to an input circuit 51. Signals representing display contents are sent as data signals to the first and second write data buffers 52 .
53.

The write data buffers 52 and 53 are switched by a signal obtained by dividing the PEI signal into 1/2 by a flip-flop 54 and an inversion circuit 55.

The outputs from the first and second verbal data buffers 52.53 are sent as data signals to the first and second memories 56.53.
57 is given. Address signals for writing data into memories 56 and 57 are provided by first and second write address buffers 58 and 59. Address signals for reading data from memory 56.57 are applied from first and second read address buffers 60.61. Address buffers 58, 59; 60, 61 are controlled by a signal from flip-flop 54 and a signal that is inverted by inverting circuit 62. The address for writing data to memory 66.57 is CLK.
It is derived from counter 63 responsive to the I signal and provided to write address buffers 58-59. Memory 56.5
The store contents read from 7 are provided to output circuit 67 from first and second read data buffers 64 and 65.

An address signal for reading stored contents from the memory 56.57 is applied from the host board 20 to the read address buffer array 0.61 via a bidirectional output circuit 67. In this way, the memories 56 and 57 of the host board 18 are alternately written to from the drive board 16 and read from the host board 20.

FIG. 7 is a block diagram showing a schematic electrical configuration of the host board 20. A signal from the receive board 18 is applied to a bidirectional input circuit 71. Input circuit 71
The PF3 signal from the CPU72 interrupt input terminal INT
and the drive board 1 to the receive board 18
It is recognized that the transfer of the signal from 6 has been completed. C.P.
U72 derives an address signal for reading the store contents from the memory 56, 57 of the receive board according to a program stored in advance in the ROM 73, and temporarily stores the read store contents in the RAM 74.

The host board 22 is provided with an H/S circuit 75, which generates an H/S signal to be applied to the sub-board 21 via an output circuit 76. This H/S signal is sent to lines 77 and 78.
It is created based on the signal on CLK2 via .

FIG. 8 is a block diagram showing a schematic electrical configuration of the sub-board 21. FIG. A signal from host stock 20 is applied to input circuit 81 . Atosis and data signals from host hoard 20 are provided to select circuit 82 . Data and address signals from select circuit 82 are applied to memory 83. The select circuit 82 has a C
Address and data signals from PU 84 are also provided.

The CPU 84 reads out the stored contents of the memory 83 according to a program preset in the ROM 85, and stores the red color LE.
Data for driving the LED is stored in VRAM MB2, and data for driving the green LED is stored in VRAM8.
Store in 8. The contents stored in the VRAMs 87 and 88 are read out by the CPU 84, converted into serial data by the parallel-to-serial conversion circuits 89 and 90, and provided to the LED indicators 120 and 220. Such operations of the CPU 84 are performed in response to a signal applied from the input circuit 81 via the line 91.

Switching of address and data signals by select circuit 82 is performed in response to an H/S signal applied via line 92. ) (When the /S signal is low level,
The select circuit 82 provides the address signal and data signal from the host board 20 to the memory 83. When the H/S signal is at high level, the stored contents of the memory 83 are read out by the address signal from the CPtJ84.

When performing scroll display, a signal corresponding to the display content to be displayed in each display area and the display area adjacent in the scroll direction is applied to the memory 83 during the period when the H/S signal is at a low level. The CPU 84 reads the stored contents of the memory 83 while the H/S signal is at high level,
Separate colors for red and green are stored in VRAM87.88 respectively. The stored contents of the VRAMs 87 and 88 are sequentially read out and sent to the parallel-to-serial converter circuit 89.
．． 90 to the LED indicators 120, 220. When displaying animation, H/S signal 1
A signal whose display contents change little by little every cycle is stored in memory 8.
3, the CPU 84 reads the stored contents of the memory 83 and outputs it to the LED display 120.220.

FIG. 9 is a time chart showing signals derived from the drive board 16. FIG. 9(1) shows the PEI signal, and its period Wll is, for example, 80 msec. When displaying an animation, one cycle per cycle of this signal.
The displayed images are changed one by one. When performing a scroll display every 4 dots, one LED display 120.220 is displayed at a cycle W12 of 320 msec, for example.
Scrolling is performed. Figure 9 (2) shows the PF
3 signal, indicating that the data transfer from the drive board 16 to the receive board 18 is completed when W13 time has elapsed since the PEI signal.

FIG. 9(3) shows the clock signal CL for data transfer.
Indicates KI signal. The frequency of this signal is approximately IMHz. FIG. 9(4) shows the H/S signal. Figure 9 (5)
is an enlarged view of the time axis of the H/S signal. Figure 9 (6) ~
FIG. 9 (10) shows the time axis further enlarged. 9(6) to 9(9) show the LED matrix 126.1
Address signals LO to L for specifying one row of 46
3 is shown. FIG. 9(10) shows the PE2 signal which is the reference clock signal to the sub-board 18. This cycle w14
is, for example, 312 μsec. In this way, PE2.
PEI and CLK2 signals are synchronized.

FIG. 10 shows that the display means 14a to 14d display a display screen of 20 by combining four display areas of 512 dots in each row.
FIG. 4 is a diagram for explaining scroll control when used as 48 dots. FIG. 10(1) shows the configuration of the display means 14. FIG. 10 (2) shows the PEI signal, and this first signal indicates the ports 32a to 32d of the drive board 16.
A signal corresponding to one screen's worth of display content to be displayed and one screen's display content to be displayed next is given to each of the display means 14a to 14d, and at the 12,828th number, a signal corresponding to the next display content is given. to indicate scrolling by subboard.

FIG. 11 is a schematic block diagram showing the configuration of another embodiment of the present invention. Parts corresponding to those in the embodiment shown in the second figure are given the same reference numerals. What is noteworthy is the horizontal 512 dots.
The display means 14a to 14d each consisting of 272 vertical dots are combined in a matrix of 2 rows and 2 columns. Even on such a display screen 14, smooth display can be achieved by providing data in synchronization with the PEI signal as shown in FIG. For example, when scrolling in the vertical direction, the first PE1 signal provides signals for two screens to the boats 32b and 32d. With the 68th PEI signal, a signal for a new screen is given to the boats 32b and 32d, and the signal given to the boats 32b and 32d with the first PEI signal is given to the boats 32a and 32C. When scrolling in the horizontal direction, please refer to Figure 10 (2).
), a signal is given to every 128 boats 32a, 32b and 32c, 32d.

FIG. 13 shows the appearance of the display device 101 of each of the above embodiments. Characters and image signals from the personal computer 102 are displayed on a large screen display 103.

In each of the embodiments described above, two colors of LEDs are used for display, but it is of course possible to use one color of LEDs. Of course, display may also be performed using a liquid crystal display element or a cathode ray tube.

Effects of the Invention As described above, according to the present invention, a large screen display means can be constructed by combining a plurality of display areas. Each display area is synchronized by a display control means that receives a signal representing the content to be displayed individually corresponding to each display area from the input means, and a signal that specifies the change mode of the display content in common. Therefore, the display contents of the entire display screen can be smoothly changed according to the specified change mode. Therefore, by using a large display screen, it is possible to effectively display information to a large number of people over a large area such as outdoors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an electrical configuration of an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of an LED display. 4 is an electric circuit diagram showing the structure of the LED matrix, FIG. 5 is a block diagram showing the structure of the drive board 16, FIG. 6 is a block diagram showing the structure of the receive board 18, and FIG. 7 is a host block diagram. A block diagram showing the configuration of the board 20,
FIG. 8 is a block diagram showing the configuration of the sub-board 21, and FIG.
The figure is a time chart for explaining the operation of the embodiment shown in the first figure, FIG. 10 is a diagram for explaining the operation when performing scroll display in the embodiment illustrated in the first figure, and FIG. Block diagram showing the configuration of another embodiment, No. 12
11 is a diagram for explaining the operation in the embodiment shown in FIG. 13, FIG. 13 is a perspective view showing the embodiment of the present invention, FIG. 14 is a block diagram showing the configuration of a conventional display device, and FIG.
The figure is a block diagram showing the electrical configuration of the configuration shown in FIG. 14,
16 and 17 are time charts for explaining the operation of the configuration shown in FIG. 14. 11... Input means, 12... Display synchronization means, 13゜1
3 a ~ 13 d - display control means, 14.14 a ~
14d...Display means, 16...Drive board, 1
8°18a to 18d - Receive board, 20.
20a-20d...Host board, 21.21a-
21d. 2na to 2nd... Sub board, 34... Signal generation circuit, 39.40, 56.57.83... Memory, 7
2.84... CPU Agent Patent attorney Number of strokes Keiichi Figure 1 Figure 4 Figure 11 Figure 12 Figure 15 Procedural amendment (method) % formula % 2. Invention title display device 3, amendment Relationship with the case filed by the applicant Applicant Address 1048 Kadoma, Kadoma City, Osaka Name (58
3) Matsushita Electric Works Co., Ltd. Representative: Toshio Miyoshi 4, Agent address: 1-13-38 Nishihonmachi, Nishi-ku, Osaka Shinko Sangyo Building Country Equipment EX 0525-5985 INTAPT
J International FAX (06)538-0247 (Representative)
6. Drawing to be amended 7. Contents of amendment: An engraving of Figure 3 of the drawing (no change in content). that's all

Claims (1)

[Claims] Display means for displaying a character or an image on a display screen divided into a plurality of display areas; and inputting the content to be displayed by the display means and the mode of change thereof, and displaying the input display content. an input means for individually deriving a signal representing each of the display areas and deriving a signal specifying a mode of change; and a plurality of synchronization control means provided corresponding to each of the display areas, each of which The synchronous control means is
and synchronous control means for driving the display means by synchronously deriving, in response to a signal from the input means, a signal representing content to be displayed in each display area in a specified variation mode. A display device characterized by: