JPH07327257A - Method and device for communication control and mobile communication terminal - Google Patents

Abstract

PURPOSE:To provide a communication control technique which easily changes or adds a control signal given from a control block to a function block. CONSTITUTION:The timing generating circuit which outputs the control signals to control plural function blocks consists of a counter circuit 201 (counter circuit 203), which is preset by a synchronous detection signal 13 and is operated by a reception clock (a transmission clock and a synchronizing clock), and a pulse storage circuit 202 (pulse storage circuit 204) which takes the output of the counter circuit as the address, and control signals 14, 15, 16, and 17 (control signals 22, 21, 20, 19, and 18) to be given to respective function blocks are outputted correspondingly to the read address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control technique and a mobile communication terminal using the same, and more particularly to a technique effectively applied to the construction of a serial interface in a digital communication system for serial communication.

[0002]

2. Description of the Related Art Slots in serial data communication,
As a method of analyzing the frame data and generating and supplying a control signal to each functional block used in the assembling circuit, there is a method in which the bit stream counter and its output are decoded by a logic gate in the configuration shown in FIG. . For the method of constructing the decoding circuit, see Ohmsha Co., Ltd., 1
Published on September 1, 988, OHM University lecture "Digital Circuit" by Akira Kawamata, P171, Fig. 5.15, etc.

[0003]

However, when a control signal is generated by a combination of logic gates as in the prior art, (1) it is difficult to change the control timing, and (2) it is difficult to generate a control signal with a special timing. (3) There are various problems such as unstable operation of the system due to noise generated by the gate delay.

Further, since the number of control signal lines connecting the logic gates increases, (1) it is difficult to add or reduce functional blocks, and (2) the delay difference between the signal lines becomes large.
(3) Problems such as poor layout efficiency occur.

An object of the present invention is to provide a communication control technique capable of easily changing or adding a control signal given from a control block to a functional block.

Another object of the present invention is to provide a communication control technique capable of eliminating noise and a difference in transmission delay of control signals with respect to each functional block and performing stable operation. .

Still another object of the present invention is to provide a communication control technique capable of improving the layout efficiency in the circuit design of control blocks, functional blocks and the like.

Still another object of the present invention is to provide a mobile communication terminal whose specifications of hardware and software can be easily changed.

Still another object of the present invention is to provide a mobile communication terminal capable of realizing stable operation, miniaturization, and cost reduction.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, in the communication control technique of the present invention, in the control block, the control timing corresponding to the bit stream is directly read and generated from the memory circuit whose address is the counter output for counting the clock corresponding to the bit stream. The configuration is given to each functional block. Further, the control signal given from the control block to each functional block is multiplexed, and the multiplexed control signal is discriminated and separated into individual control signals in the vicinity of or inside each functional block. .

Further, the mobile communication terminal of the present invention has a structure internally having the communication control technology having such a structure.

[0014]

According to the communication control technique of the present invention described above, if a ROM, for example, is used as the memory circuit, a control signal at an arbitrary timing can be easily generated by rewriting the pattern in the ROM. Further, by using the RAM, it is possible to dynamically change the timing of the control signal during operation. Further, since the control signal is directly read from the memory circuit, noise generated by the gate delay difference can be reduced. Further, by multiplexing and storing a plurality of control signals as the pattern of the ROM or RAM, the number of signal lines connecting the control block and the functional block can be greatly reduced, and it is easy to cope with circuit correction and layout correction. it can. Further, by multiplexing the control signals, the number of signal lines is unified so that the delay difference between the control signal lines due to the layout can be minimized and the layout efficiency can be improved.

Further, according to the mobile communication terminal of the present invention having the above-mentioned communication control technology built-in, it is possible to easily change the specifications, stabilize the operation, reduce the size, and reduce the cost. it can.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of the configuration of a mobile communication terminal which is an embodiment of the present invention, and FIGS. 2 and 3 are conceptual diagrams showing an example of the format of communication data handled by the mobile communication terminal. 4, FIG. 5, FIG. 6 and FIG. 7 are conceptual diagrams showing an example of the configuration of a communication control device used therein, and FIG. 8 is a diagram showing an example of its action.

The mobile communication terminals of this embodiment are roughly classified into
A radio control unit including a high frequency unit 101 and an intermediate frequency unit 102, a modem 103, a buffer 104, a TDMA
The time control unit 105 (communication control device), ISDN interface control, and Adaptive Differential Pulse Co
It is composed of a baseband processing unit including a peripheral interface circuit 106 that encodes and decodes an audio signal using a technique such as de Modulation, and a system control unit including a microprocessor 107, a program ROM 108, a data RAM 109, and the like. Are connected via the system bus 110.

In the radio control unit, based on the oscillator of an analog circuit such as the high frequency unit 101 and the intermediate frequency unit 102, for example, the generation, modulation / demodulation, switching of carrier frequency and reception level detection of a communication carrier in the frequency band of 1.9 GHz are performed. And so on.

In the baseband processing unit, in addition to baseband conversion processing such as modulation / demodulation of digital data and reception clock reproduction, TDMA slot timing control is performed to identify and separate functional channel data from data in the slot.
Or assemble.

Microprocessor 10 of system control unit
Reference numeral 7 reads out a control program stored in the program ROM 108 and performs control operations such as control of hardware such as a baseband processing unit and control of a serial data communication protocol. In addition, in the data RAM 109,
Management information of the serial data communication protocol and system monitor information are stored and used for the control operation.

FIG. 2 shows a TDMA slot format standardized by RCR as an example of serial data communication handled by the mobile communication terminal of this embodiment.

In this example, a frame is composed of four slots each for transmission and reception, and the data in the slot is a guard bit consisting of R, SS, PR, and G, and synchronization detection used for synchronization detection. UW (unique word) as a pattern, channel identification code C indicating the channel type
I, function channel data SACC indicating service type
H, net information I, and a total of 240 bits of these and CRC, which is a set of serial data (bit stream).

FIG. 3 shows the scrambling and CRC calculation range applied to the slots. In addition to assembling and disassembling the above data, 176 bits of scrambling and 180 bits of CRC calculation are performed.

FIG. 4 shows a TDM for communicating slot data.
The example of a structure of the A time control part 105 is shown. The TDMA time control unit 105 of this embodiment is provided with the timing generation circuit 2 including the CPU input / output unit 1. The timing generation circuit 2 includes a synchronization word detector 3, a descrambling circuit 4, an S / P conversion circuit 5, a peripheral LSI input / output circuit 6, and a CR on the reception system side that processes the reception data 23.
Each functional block of the C check circuit 7 includes a signal line 13a,
Signal line 14a, signal line 15a, signal line 16a, signal line 1
It is connected via 7a.

Similarly, on the transmission side that processes transmission data, the frame assembling circuit 8, the scrambling circuit 9 and the CRC are provided.
Each functional block of the generation circuit 10, the P / S conversion circuit 11, and the peripheral LSI input / output circuit 12 includes a signal line 22a and a signal line 2
1a, a signal line 20a, a signal line 19a, and a signal line 18a.

The P / S conversion circuit 11 includes a system bus 11
The parallel digital data 33 input from the microprocessor 107 via 0 is converted into serial data and output as serial transmission data 32 to the CRC generation circuit 10. The peripheral LSI input / output circuit 12 is a peripheral I
The transmission input 34 from C is output to the CRC generation circuit 10 as serial transmission data 32. CRC generation circuit 10
Adds the CRC code generated from the transmission data 32 to the end of the transmission data 32 and inputs it to the scramble circuit 9 as the transmission data 31. The scramble circuit 9
The transmission data 31 is scrambled and input to the frame assembling circuit 8 as the transmission data 30. Frame assembly circuit 8
2 adds data specified by a predetermined transmission protocol so as to have a transmission format as illustrated in FIG. 2 and outputs it as transmission data 29 to the modem 103 via the buffer 104.

The sync word detector 3 detects UW from the received data 23, and notifies the timing generation circuit 2 of the slot and frame start point by the sync detection signal 13. The timing generation circuit 2 has a burst counter and a slot counter, and the operation start point of the counter is set by the synchronization detection signal 13 and the timing for decomposing and extracting the received data according to the number of received bits of the data is used for each of the functional blocks. Supply to. The descrambling circuit 4 uses the control signal 14
At the timing given by, the scramble of the received data 24 is descrambled, and it is output as serial unscrambled received data 25. The S / P conversion circuit 5 that serves as an interface of the system bus 110 and transfers the parallel data 26 to the upper microprocessor 107, the peripheral LSI input / output circuit 6 that supplies the received data 27 to the peripheral LSIs having different processing speeds, the received data The CRC check circuit 7 which performs the CRC check on 25 and sets the CRC check result 28 in the flag register similarly executes the respective functions at the timings given by the control signals 15, 16 and 17. The functional block on the transmission side operates under the same control.

FIG. 5 shows the configuration of the timing generation circuit 2. The reception system includes a counter circuit 201 preset with the synchronization detection signal 13 and operated by the reception clock, and a pulse storage circuit 202 having this output as a read address. The signals read from this are the control signal 14, the control signal 15, and the control signal. The signal 16 and the preset signal 35 are supplied to each functional block such as the S / P conversion circuit 5, the peripheral LSI input / output circuit 6 and the CRC check circuit 7 in FIG.

The transmission system has a counter circuit 203 and a pulse storage circuit 204, which are driven by a transmission clock. The control signal 22, the control signal 21, the control signal 20, the control signal 19, the control signal 18, and the preset signal 36 as the output of the pulse storage circuit 204 are the frame assembly circuit 8, the scramble circuit 9, and the CRC generation circuit 10 in FIG. , Around L
It is supplied to each functional block such as the SI input / output circuit 12 and the P / S conversion circuit 11.

FIG. 6 shows a pulse storage circuit 2 composed of a ROM.
02, an example of data to be written to the pulse storage circuit 204 is shown. CRC check circuit 7 in FIG.
A method of creating data will be described below by taking the control signal 17 supplied to the above as an example. The ROM forming the pulse storage circuit 202 has a storage capacity of 240 words corresponding to the number of data in the slot, and has a data structure of 5 bits per word corresponding to the number of control blocks. The control signal 17 corresponds to the first bit of data, which has 240 bits in the word direction.

As shown in the applicable area of FIG. 3, the control of the CRC check circuit 7 requires the operation start point (29th bit), the operation end / bit comparison start point (209th bit), and the judgment point (225th bit). The above three timings are required, and these timings can be multiplexed and sent to one signal line 17a. As a pattern required at this time, "1" corresponding to the pulse is stored in the address 28, the address 208, and the address 224 corresponding thereto, and "0" is stored in the other addresses. Since it suffices that this pattern be read out in a pulse form, "1" and "0" may be mixed and stored. Patterns can be stored in other blocks in a similar manner.

The pulse memory circuit 202 and the pulse memory circuit 204 are dynamically rewritable memory circuits (for example, R
AM), and by writing a desired pattern by accessing the microprocessor 107, the operating specifications can be changed at any time during operation.

Further, as illustrated in FIG. 9, a plurality of planes (addresses 000 to 239: plane 1, plane 1; Address 240 to 479: plane 2), and the access to the plane 2 may be performed by giving an offset value of 240 to the input address value.

Further, as illustrated in FIG. 10, a memory such as a ROM which constitutes the pulse storage circuit 202 is expanded in the bit direction of one word to form a plurality of planes (bits 0 to 4:
Plane 1, bits 5 to 9: plane 2) may be configured, and a plane for an arbitrary address may be selected by a selection circuit (not shown) provided in the memory.

FIG. 7 shows an example of the structure of the CRC check circuit 7. A counter circuit 701, C to which the control signal 17 and the preset signal 35 from the timing generation circuit 2 are input
An RC operation circuit 702, a selection circuit 703 for selecting an input to the CRC operation circuit 702, and a determination circuit 704 for performing a CRC match determination. CRC calculation circuit 70
2, the preset signal 35 and the start / stop signal 705 are input. The selection circuit 703 includes a CRC calculation circuit 702.
The input switching signal 706, and the determination timing signal 707 and the preset signal 35 are input to the determination circuit 704. The counter circuit 701 starts counting by the pulse of the control signal 17 after presetting by the preset signal 35. Since this pulse is sequentially sent in synchronization with the CRC control timing, the start / stop which is the output of the counter circuit 701. Signal 705, input switching signal 70
6. The determination timing signal 707 can be generated in synchronization with this.

Incidentally, instead of the counter circuit 701, a state transition circuit for changing the state by the input of the control signal 17 and generating the start / stop signal 705, the input switching signal 706, the judgment timing signal 707, etc. according to each state. It is obvious that the equivalent operation can be realized by providing the.

FIG. 8 shows an example of the operation of the counter circuit 701 provided in the CRC check circuit 7. When a preset pulse is generated at the ROM address 027, each unit is reset, and the start / stop signal 705 and the input switching signal 7
06, the determination timing signal 707 becomes “LOW”.
At the ROM address 028, the first pulse is generated in the control signal 17 of the signal line 17a, and the start / stop signal 705 output from the counter circuit 701 becomes "HIGH". Start as ROM addresses 208, 224 become
The stop signal 705, the input switching signal 706, and the determination timing signal 707 are sequentially changed as shown in the figure, and each part such as the CRC calculation circuit 702, the selection circuit 703, and the determination circuit 704 is controlled. As described above, the control signal 17 can be multiplexed and sent from the timing generation circuit 2 to one signal line 17a. On the other hand, in each functional block such as the CRC check circuit 7 or the like, the timing is separated by the counter circuit 701. As a result, it becomes possible to generate a plurality of control signals.

As described above, according to the communication control apparatus of the present embodiment, the timing generation circuit 2 counts up with the reception clock (transmission clock) in response to the synchronization detection signal 13 (synchronization clock).
The value of the (counter circuit 203) is used as a read address, and the pulse storage circuit 202 (pulse storage circuit 20) that generates the control signals 14 to 17 and the preset signal 35 (control signals 18 to 22, preset signal 36) corresponding to the addresses.
4) is provided, various control signals can be easily generated at arbitrary timings synchronized with the received data and the transmitted data by merely rewriting the stored contents of the pulse storage circuit 202 and the pulse storage circuit 204. . Also,
As in the case of using the logic gate, the operation is stabilized without generating noise.

Further, since each control signal is multiplexed and each functional block to which this control signal is input is provided with a counter circuit 701 or the like for discriminating each multiplexed control signal, the timing generation circuit 2 and , Peripheral descrambling circuit 4, S / P conversion circuit 5, peripheral LSI input / output circuit 6,
The number of signal lines connecting the functional blocks such as the CRC check circuit 7, the frame assembly circuit 8, the scramble circuit 9, the CRC generation circuit 10, the peripheral LSI input / output circuit 12, the P / S conversion circuit 11 can be reduced, It is possible to improve layout efficiency in design. In addition, since the control signals that are multiplexed inside or near each functional block are discriminated,
The delay between the signal lines is eliminated.

Further, according to the mobile communication terminal of the present embodiment, since the TDMA time control section 105 having the above-mentioned function is provided, it becomes easy to change the specifications of software and hardware and stabilize the operation. Downsizing and downsizing,
Further, cost reduction can be realized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0043]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the communication control method and apparatus of the present invention, it is possible to easily change or add a control signal given from a control block to a functional block. Further, it is possible to eliminate the occurrence of noise and the transmission delay difference of the control signal with respect to each functional block, and obtain an effect that a stable operation can be performed. Further, there is an effect that the layout efficiency in the circuit design of the control block, the functional block, etc. can be improved.

According to the mobile communication terminal of the present invention,
The effect is that the specifications of hardware and software can be easily changed. Further, it is possible to obtain the effect that the operation can be stabilized, the size can be reduced, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an example of a configuration of a mobile communication terminal which is an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of a format of communication data handled by it.

FIG. 3 is a conceptual diagram showing an example of a format of communication data handled by it.

FIG. 4 is a conceptual diagram showing an example of a communication control device used therein.

FIG. 5 is a conceptual diagram showing an example of a communication control device used therein.

FIG. 6 is a conceptual diagram showing an example of a communication control device used therein.

FIG. 7 is a conceptual diagram showing an example of a communication control device used therein.

FIG. 8 is a diagram showing an example of the operation.

FIG. 9 is a conceptual diagram showing an example of a communication control device used therein.

FIG. 10 is a conceptual diagram showing an example of a communication control device used therein.

FIG. 11 is a conceptual diagram showing an example of a conventional technique.

[Explanation of symbols]

 1 CPU input / output unit 2 Timing generation circuit (control block) 3 Synchronous word detector 4 Scrambling deactivation circuit (functional block) 5 S / P conversion circuit (functional block) 6 Peripheral LSI input / output circuit (functional block) 7 CRC check circuit (Function block) 8 Frame assembly circuit (Function block) 9 Scramble circuit (Function block) 10 CRC generation circuit (Function block) 11 P / S conversion circuit (Function block) 12 Peripheral LSI input / output circuit (Function block) 13 Sync detection Signal 13a Signal line 14-17 Control signal 14a-17a Signal line 18-22 Control signal 18a-22a Control signal 35 Preset signal 36 Preset signal 101 High frequency part 102 Intermediate frequency part 103 Modem 104 Buffer 105 TDMA time control part (communication control device ) 1 6 Peripheral Interface Circuit 107 Microprocessor 108 Program ROM 109 Data RAM 110 System Bus 201 Counter Circuit 202 Pulse Memory Circuit (Memory Circuit) 203 Counter Circuit 204 Pulse Memory Circuit (Memory Circuit) 701 Counter Circuit 702 CRC Calculation Circuit 703 Selection Circuit 704 Judgment Circuit 705 Start / Stop signal 706 Input switching signal 707 Judgment timing signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuki Igarashi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Information & Communication Division

Claims (9)

[Claims] 1. In a serial communication system, a memory circuit having the same or an integer multiple of the number of words as a burst-like bit stream is provided, and data read by applying the bit stream to the memory circuit as an address input is read. A communication control method characterized by being used as various control signals. 2. In a serial communication system, a control block including a memory circuit having the same or an integer multiple of the number of words as the burst bit stream, and the memory circuit is supplied with the bit stream as an address input. A communication control device comprising: a plurality of functional blocks that operate on the basis of data read from the storage circuit as a control signal. 3. The ROM or RA having a configuration in which the memory circuit can read from a specific address by detecting a specific bit pattern included in the bit stream.
The communication control device according to claim 2, wherein the communication control device is M. 4. The communication control device according to claim 2, wherein the memory circuit is composed of a plurality of planes, and switching of the planes is selected by an addressing method. 5. The communication according to claim 2, wherein the storage circuit comprises a plurality of planes extended in the bit direction of one word, and switching of each plane is performed by an output selection circuit. Control device. 6. The data used as the control signal is multiplexed and stored in the storage circuit, and the plurality of control signals are provided by a single signal line connecting the control block and each of the functional blocks. 6. The communication control device according to claim 2, 3, 4, or 5, wherein the communication control device is provided to each of the functional blocks via the above. 7. Each of the plurality of functional blocks includes a counter circuit that separates the control signal that arrives after being multiplexed via the signal line, or a state transition circuit that operates using the control signal as a transition clock. 7. The communication control device according to claim 2, wherein the counter circuit or the state transition circuit discriminates individual control signals. 8. The control signal given from the control block to a plurality of the functional blocks is a reset signal for resetting each of the functional blocks. Alternatively, the communication control device according to 7. 9. Claims 2, 3, 4, 5, 6, 7 or 8
A mobile communication terminal comprising the communication control device described.